guangzong/stm32-data
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Remove enum_read, enum_write.

Browse Source
This commit is contained in:
Dario Nieuwenhuis 2023-06-28 22:36:19 +02:00
parent 0d958def0e
commit 3f01ff4545
52 changed files with 231 additions and 2152 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
data/registers/adc_f1.yaml
View File

@ -171,12 +171,10 @@ fieldset/CR2:
description: Start conversion of injected channels description: Start conversion of injected channels
bit_offset: 21 bit_offset: 21
bit_size: 1 bit_size: 1
enum_write: JSWSTARTW
- name: SWSTART - name: SWSTART
description: Start conversion of regular channels description: Start conversion of regular channels
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
enum_write: SWSTARTW
- name: TSVREFE - name: TSVREFE
description: Temperature sensor and VREFINT enable description: Temperature sensor and VREFINT enable
bit_offset: 23 bit_offset: 23

103
data/registers/adc_v1.yaml
View File

@ -154,32 +154,22 @@ fieldset/CR:
description: ADC enable command description: ADC enable command
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum_read: ADENR
enum_write: ADENW
- name: ADDIS - name: ADDIS
description: ADC disable command description: ADC disable command
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
enum_read: ADDISR
enum_write: ADDISW
- name: ADSTART - name: ADSTART
description: ADC start conversion command description: ADC start conversion command
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: ADSTARTR
enum_write: ADSTARTW
- name: ADSTP - name: ADSTP
description: ADC stop conversion command description: ADC stop conversion command
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: ADSTPR
enum_write: ADSTPW
- name: ADCAL - name: ADCAL
description: ADC calibration description: ADC calibration
bit_offset: 31 bit_offset: 31
bit_size: 1 bit_size: 1
enum_read: ADCALR
enum_write: ADCALW
fieldset/DR: fieldset/DR:
description: data register description: data register
fields: fields:
@ -260,81 +250,6 @@ fieldset/TR:
description: Analog watchdog higher threshold description: Analog watchdog higher threshold
bit_offset: 16 bit_offset: 16
bit_size: 12 bit_size: 12
enum/ADCALR:
bit_size: 1
variants:
- name: NotCalibrating
description: ADC calibration either not yet performed or completed
value: 0
- name: Calibrating
description: ADC calibration in progress
value: 1
enum/ADCALW:
bit_size: 1
variants:
- name: StartCalibration
description: Start the ADC calibration sequence
value: 1
enum/ADDISR:
bit_size: 1
variants:
- name: NotDisabling
description: No disable command active
value: 0
- name: Disabling
description: ADC disabling
value: 1
enum/ADDISW:
bit_size: 1
variants:
- name: Disable
description: Disable the ADC
value: 1
enum/ADENR:
bit_size: 1
variants:
- name: Disabled
description: ADC disabled
value: 0
- name: Enabled
description: ADC enabled
value: 1
enum/ADENW:
bit_size: 1
variants:
- name: Enabled
description: Enable the ADC
value: 1
enum/ADSTARTR:
bit_size: 1
variants:
- name: NotActive
description: No conversion ongoing
value: 0
- name: Active
description: ADC operating and may be converting
value: 1
enum/ADSTARTW:
bit_size: 1
variants:
- name: StartConversion
description: Start the ADC conversion (may be delayed for hardware triggers)
value: 1
enum/ADSTPR:
bit_size: 1
variants:
- name: NotStopping
description: No stop command active
value: 0
- name: Stopping
description: ADC stopping conversion
value: 1
enum/ADSTPW:
bit_size: 1
variants:
- name: StopConversion
description: Stop the active conversion
value: 1
enum/ALIGN: enum/ALIGN:
bit_size: 1 bit_size: 1
variants: variants:
@ -467,21 +382,3 @@ enum/SCANDIR:
- name: Backward - name: Backward
description: Backward scan (from CHSEL18 to CHSEL0) description: Backward scan (from CHSEL18 to CHSEL0)
value: 1 value: 1
enum/TSEN:
bit_size: 1
variants:
- name: Disabled
description: Temperature sensor disabled
value: 0
- name: Enabled
description: Temperature sensor enabled
value: 1
enum/VBATEN:
bit_size: 1
variants:
- name: Disabled
description: V_BAT channel disabled
value: 0
- name: Enabled
description: V_BAT channel enabled
value: 1

14
data/registers/adc_v2.yaml
View File

@ -184,7 +184,6 @@ fieldset/CR2:
description: Start conversion of injected channels description: Start conversion of injected channels
bit_offset: 22 bit_offset: 22
bit_size: 1 bit_size: 1
enum_write: JSWSTARTW
- name: EXTSEL - name: EXTSEL
description: External event select for regular group description: External event select for regular group
bit_offset: 24 bit_offset: 24
@ -199,7 +198,6 @@ fieldset/CR2:
description: Start conversion of regular channels description: Start conversion of regular channels
bit_offset: 30 bit_offset: 30
bit_size: 1 bit_size: 1
enum_write: SWSTARTW
fieldset/DR: fieldset/DR:
description: regular data register description: regular data register
fields: fields:
@ -618,12 +616,6 @@ enum/JSTRT:
- name: Started - name: Started
description: Injected channel conversion has started description: Injected channel conversion has started
value: 1 value: 1
enum/JSWSTARTW:
bit_size: 1
variants:
- name: Start
description: Starts conversion of injected channels
value: 1
enum/OVR: enum/OVR:
bit_size: 1 bit_size: 1
variants: variants:
@ -729,9 +721,3 @@ enum/STRT:
- name: Started - name: Started
description: Regular channel conversion has started description: Regular channel conversion has started
value: 1 value: 1
enum/SWSTARTW:
bit_size: 1
variants:
- name: Start
description: Starts conversion of regular channels
value: 1

14
data/registers/adc_v4.yaml
View File

@ -289,12 +289,10 @@ fieldset/CR:
description: enable description: enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum_write: ADENW
- name: ADDIS - name: ADDIS
description: disable description: disable
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
enum_write: ADDISW
- name: ADSTART - name: ADSTART
description: group regular conversion start description: group regular conversion start
bit_offset: 2 bit_offset: 2
@ -642,18 +640,6 @@ enum/ADCALDIF:
- name: Differential - name: Differential
description: Calibration for differential mode description: Calibration for differential mode
value: 1 value: 1
enum/ADDISW:
bit_size: 1
variants:
- name: Disable
description: Disable conversion and go to power down mode
value: 0
enum/ADENW:
bit_size: 1
variants:
- name: Enable
description: Enable ADC
value: 1
enum/ADSTP: enum/ADSTP:
bit_size: 1 bit_size: 1
variants: variants:

14
data/registers/bkp_v1.yaml
View File

@ -81,12 +81,10 @@ fieldset/CSR:
description: Clear Tamper event description: Clear Tamper event
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum_write: CTEW
- name: CTI - name: CTI
description: Clear Tamper Interrupt description: Clear Tamper Interrupt
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
enum_write: CTIW
- name: TPIE - name: TPIE
description: Tamper Pin interrupt enable description: Tamper Pin interrupt enable
bit_offset: 2 bit_offset: 2
@ -135,18 +133,6 @@ enum/ASOS:
- name: Second - name: Second
description: RTC Second pulse output selected description: RTC Second pulse output selected
value: 1 value: 1
enum/CTEW:
bit_size: 1
variants:
- name: Reset
description: Reset the TEF Tamper event flag (and the Tamper detector)
value: 1
enum/CTIW:
bit_size: 1
variants:
- name: Clear
description: Clear the Tamper interrupt and the TIF Tamper interrupt flag
value: 1
enum/TPAL: enum/TPAL:
bit_size: 1 bit_size: 1
variants: variants:

41
data/registers/can_bxcan.yaml
View File

@ -449,19 +449,14 @@ fieldset/RFR:
description: FULL0 description: FULL0
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
enum_read: FULLR
enum_write: FULLW
- name: FOVR - name: FOVR
description: FOVR0 description: FOVR0
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: FOVRR
enum_write: FOVRW
- name: RFOM - name: RFOM
description: RFOM0 description: RFOM0
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_write: RFOMW
fieldset/RIR: fieldset/RIR:
description: receive FIFO mailbox identifier register description: receive FIFO mailbox identifier register
fields: fields:
@ -662,36 +657,6 @@ enum/FOVIE:
- name: Enabled - name: Enabled
description: Interrupt generated when FOVR bit is set description: Interrupt generated when FOVR bit is set
value: 1 value: 1
enum/FOVRR:
bit_size: 1
variants:
- name: NoOverrun
description: No FIFO x overrun
value: 0
- name: Overrun
description: FIFO x overrun
value: 1
enum/FOVRW:
bit_size: 1
variants:
- name: Clear
description: Clear flag
value: 1
enum/FULLR:
bit_size: 1
variants:
- name: NotFull
description: FIFO x is not full
value: 0
- name: Full
description: FIFO x is full
value: 1
enum/FULLW:
bit_size: 1
variants:
- name: Clear
description: Clear flag
value: 1
enum/LBKM: enum/LBKM:
bit_size: 1 bit_size: 1
variants: variants:
@ -737,12 +702,6 @@ enum/LECIE:
- name: Enabled - name: Enabled
description: "ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection" description: "ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection"
value: 1 value: 1
enum/RFOMW:
bit_size: 1
variants:
- name: Release
description: Set by software to release the output mailbox of the FIFO
value: 1
enum/RIR_IDE: enum/RIR_IDE:
bit_size: 1 bit_size: 1
variants: variants:

27
data/registers/crs_v1.yaml
View File

@ -136,33 +136,6 @@ fieldset/ISR:
description: Frequency error capture description: Frequency error capture
bit_offset: 16 bit_offset: 16
bit_size: 16 bit_size: 16
enum/SYNCDIV:
bit_size: 3
variants:
- name: DIV1
description: f(SYNCDIV) = f(SYNCSRC)
value: 0
- name: DIV2
description: f(SYNCDIV) = f(SYNCSRC)/2
value: 1
- name: DIV4
description: f(SYNCDIV) = f(SYNCSRC)/4
value: 2
- name: DIV8
description: f(SYNCDIV) = f(SYNCSRC)/8
value: 3
- name: DIV16
description: f(SYNCDIV) = f(SYNCSRC)/16
value: 4
- name: DIV32
description: f(SYNCDIV) = f(SYNCSRC)/32
value: 5
- name: DIV64
description: f(SYNCDIV) = f(SYNCSRC)/64
value: 6
- name: DIV128
description: f(SYNCDIV) = f(SYNCSRC)/128
value: 7
enum/SYNCSRC: enum/SYNCSRC:
bit_size: 2 bit_size: 2
variants: variants:

24
data/registers/eth_v1a.yaml
View File

@ -1462,12 +1462,6 @@ enum/DM:
- name: FullDuplex - name: FullDuplex
description: MAC operates in full-duplex mode description: MAC operates in full-duplex mode
value: 1 value: 1
enum/DMABMR_SR:
bit_size: 1
variants:
- name: Reset
description: Reset all MAC subsystem internal registers and logic. Cleared automatically
value: 1
enum/DMAOMR_SR: enum/DMAOMR_SR:
bit_size: 1 bit_size: 1
variants: variants:
@ -1825,15 +1819,6 @@ enum/RDP:
- name: RDP32 - name: RDP32
description: 32 beats per RxDMA transaction description: 32 beats per RxDMA transaction
value: 32 value: 32
enum/RE:
bit_size: 1
variants:
- name: Disabled
description: MAC receive state machine is disabled after the completion of the reception of the current frame
value: 0
- name: Enabled
description: MAC receive state machine is enabled
value: 1
enum/RFAEM: enum/RFAEM:
bit_size: 1 bit_size: 1
variants: variants:
@ -1963,15 +1948,6 @@ enum/ST:
- name: Started - name: Started
description: Transmission is placed in Running state description: Transmission is placed in Running state
value: 1 value: 1
enum/TE:
bit_size: 1
variants:
- name: Disabled
description: MAC transmit state machine is disabled after completion of the transmission of the current frame
value: 0
- name: Enabled
description: MAC transmit state machine is enabled
value: 1
enum/TFCE: enum/TFCE:
bit_size: 1 bit_size: 1
variants: variants:

24
data/registers/eth_v1b.yaml
View File

@ -1507,12 +1507,6 @@ enum/DM:
- name: FullDuplex - name: FullDuplex
description: MAC operates in full-duplex mode description: MAC operates in full-duplex mode
value: 1 value: 1
enum/DMABMR_SR:
bit_size: 1
variants:
- name: Reset
description: Reset all MAC subsystem internal registers and logic. Cleared automatically
value: 1
enum/DMAOMR_SR: enum/DMAOMR_SR:
bit_size: 1 bit_size: 1
variants: variants:
@ -1903,15 +1897,6 @@ enum/RDP:
- name: RDP32 - name: RDP32
description: 32 beats per RxDMA transaction description: 32 beats per RxDMA transaction
value: 32 value: 32
enum/RE:
bit_size: 1
variants:
- name: Disabled
description: MAC receive state machine is disabled after the completion of the reception of the current frame
value: 0
- name: Enabled
description: MAC receive state machine is enabled
value: 1
enum/RFAEM: enum/RFAEM:
bit_size: 1 bit_size: 1
variants: variants:
@ -2041,15 +2026,6 @@ enum/ST:
- name: Started - name: Started
description: Transmission is placed in Running state description: Transmission is placed in Running state
value: 1 value: 1
enum/TE:
bit_size: 1
variants:
- name: Disabled
description: MAC transmit state machine is disabled after completion of the transmission of the current frame
value: 0
- name: Enabled
description: MAC transmit state machine is enabled
value: 1
enum/TFCE: enum/TFCE:
bit_size: 1 bit_size: 1
variants: variants:

24
data/registers/eth_v1c.yaml
View File

@ -1507,12 +1507,6 @@ enum/DM:
- name: FullDuplex - name: FullDuplex
description: MAC operates in full-duplex mode description: MAC operates in full-duplex mode
value: 1 value: 1
enum/DMABMR_SR:
bit_size: 1
variants:
- name: Reset
description: Reset all MAC subsystem internal registers and logic. Cleared automatically
value: 1
enum/DMAOMR_SR: enum/DMAOMR_SR:
bit_size: 1 bit_size: 1
variants: variants:
@ -1903,15 +1897,6 @@ enum/RDP:
- name: RDP32 - name: RDP32
description: 32 beats per RxDMA transaction description: 32 beats per RxDMA transaction
value: 32 value: 32
enum/RE:
bit_size: 1
variants:
- name: Disabled
description: MAC receive state machine is disabled after the completion of the reception of the current frame
value: 0
- name: Enabled
description: MAC receive state machine is enabled
value: 1
enum/RFAEM: enum/RFAEM:
bit_size: 1 bit_size: 1
variants: variants:
@ -2041,15 +2026,6 @@ enum/ST:
- name: Started - name: Started
description: Transmission is placed in Running state description: Transmission is placed in Running state
value: 1 value: 1
enum/TE:
bit_size: 1
variants:
- name: Disabled
description: MAC transmit state machine is disabled after completion of the transmission of the current frame
value: 0
- name: Enabled
description: MAC transmit state machine is enabled
value: 1
enum/TFCE: enum/TFCE:
bit_size: 1 bit_size: 1
variants: variants:

1
data/registers/flash_l0.yaml
View File

@ -156,7 +156,6 @@ fieldset/PECR:
description: Launch the option byte loading description: Launch the option byte loading
bit_offset: 18 bit_offset: 18
bit_size: 1 bit_size: 1
enum_write: OBL_LAUNCHW
fieldset/PEKEYR: fieldset/PEKEYR:
description: Program/erase key register description: Program/erase key register
fields: fields:

13
data/registers/fmc_v1x3.yaml
View File

@ -399,7 +399,7 @@ fieldset/SDCMR:
description: Command mode description: Command mode
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
enum_write: MODE enum: MODE
- name: CTB2 - name: CTB2
description: Command target bank 2 description: Command target bank 2
bit_offset: 3 bit_offset: 3
@ -469,7 +469,6 @@ fieldset/SDRTR:
description: Clear Refresh error flag description: Clear Refresh error flag
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum_write: CRE
- name: COUNT - name: COUNT
description: Refresh Timer Count description: Refresh Timer Count
bit_offset: 1 bit_offset: 1
@ -489,12 +488,12 @@ fieldset/SDSR:
description: Status Mode for Bank 1 description: Status Mode for Bank 1
bit_offset: 1 bit_offset: 1
bit_size: 2 bit_size: 2
enum_read: MODES enum: MODES
- name: MODES2 - name: MODES2
description: Status Mode for Bank 2 description: Status Mode for Bank 2
bit_offset: 3 bit_offset: 3
bit_size: 2 bit_size: 2
enum_read: MODES enum: MODES
- name: BUSY - name: BUSY
description: Busy status description: Busy status
bit_offset: 5 bit_offset: 5
@ -606,12 +605,6 @@ enum/CPSIZE:
- name: Bytes1024 - name: Bytes1024
description: 1024 bytes CRAM page size description: 1024 bytes CRAM page size
value: 4 value: 4
enum/CRE:
bit_size: 1
variants:
- name: Clear
description: Refresh Error Flag is cleared
value: 1
enum/ECCPS: enum/ECCPS:
bit_size: 3 bit_size: 3
variants: variants:

13
data/registers/fmc_v2x1.yaml
View File

@ -357,7 +357,7 @@ fieldset/SDCMR:
description: Command mode description: Command mode
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
enum_write: MODE enum: MODE
- name: CTB2 - name: CTB2
description: Command target bank 2 description: Command target bank 2
bit_offset: 3 bit_offset: 3
@ -427,7 +427,6 @@ fieldset/SDRTR:
description: Clear Refresh error flag description: Clear Refresh error flag
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum_write: CRE
- name: COUNT - name: COUNT
description: Refresh Timer Count description: Refresh Timer Count
bit_offset: 1 bit_offset: 1
@ -447,12 +446,12 @@ fieldset/SDSR:
description: Status Mode for Bank 1 description: Status Mode for Bank 1
bit_offset: 1 bit_offset: 1
bit_size: 2 bit_size: 2
enum_read: MODES enum: MODES
- name: MODES2 - name: MODES2
description: Status Mode for Bank 2 description: Status Mode for Bank 2
bit_offset: 3 bit_offset: 3
bit_size: 2 bit_size: 2
enum_read: MODES enum: MODES
- name: BUSY - name: BUSY
description: Busy status description: Busy status
bit_offset: 5 bit_offset: 5
@ -564,12 +563,6 @@ enum/CPSIZE:
- name: Bytes1024 - name: Bytes1024
description: 1024 bytes CRAM page size description: 1024 bytes CRAM page size
value: 4 value: 4
enum/CRE:
bit_size: 1
variants:
- name: Clear
description: Refresh Error Flag is cleared
value: 1
enum/ECCPS: enum/ECCPS:
bit_size: 3 bit_size: 3
variants: variants:

13
data/registers/fmc_v3x1.yaml
View File

@ -360,7 +360,7 @@ fieldset/SDCMR:
description: Command mode description: Command mode
bit_offset: 0 bit_offset: 0
bit_size: 3 bit_size: 3
enum_write: MODE enum: MODE
- name: CTB2 - name: CTB2
description: Command target bank 2 description: Command target bank 2
bit_offset: 3 bit_offset: 3
@ -430,7 +430,6 @@ fieldset/SDRTR:
description: Clear Refresh error flag description: Clear Refresh error flag
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum_write: CRE
- name: COUNT - name: COUNT
description: Refresh Timer Count description: Refresh Timer Count
bit_offset: 1 bit_offset: 1
@ -450,12 +449,12 @@ fieldset/SDSR:
description: Status Mode for Bank 1 description: Status Mode for Bank 1
bit_offset: 1 bit_offset: 1
bit_size: 2 bit_size: 2
enum_read: MODES enum: MODES
- name: MODES2 - name: MODES2
description: Status Mode for Bank 2 description: Status Mode for Bank 2
bit_offset: 3 bit_offset: 3
bit_size: 2 bit_size: 2
enum_read: MODES enum: MODES
fieldset/SDTR: fieldset/SDTR:
description: SDRAM Timing register description: SDRAM Timing register
fields: fields:
@ -563,12 +562,6 @@ enum/CPSIZE:
- name: Bytes1024 - name: Bytes1024
description: 1024 bytes CRAM page size description: 1024 bytes CRAM page size
value: 4 value: 4
enum/CRE:
bit_size: 1
variants:
- name: Clear
description: Refresh Error Flag is cleared
value: 1
enum/ECCPS: enum/ECCPS:
bit_size: 3 bit_size: 3
variants: variants:

1
data/registers/gpio_v1.yaml
View File

@ -42,7 +42,6 @@ fieldset/BRR:
array: array:
len: 16 len: 16
stride: 1 stride: 1
enum_write: BRW
fieldset/BSRR: fieldset/BSRR:
description: Port bit set/reset register (GPIOn_BSRR) description: Port bit set/reset register (GPIOn_BSRR)
fields: fields:

50
data/registers/hrtim_v1.yaml
View File

@ -296,22 +296,18 @@ fieldset/MICR:
array: array:
len: 4 len: 4
stride: 1 stride: 1
enum_write: ICR
- name: MREPC - name: MREPC
description: Repetition Interrupt flag clear description: Repetition Interrupt flag clear
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_write: ICR
- name: SYNCC - name: SYNCC
description: Sync Input Interrupt flag clear description: Sync Input Interrupt flag clear
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_write: ICR
- name: MUPDC - name: MUPDC
description: Master update Interrupt flag clear description: Master update Interrupt flag clear
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_write: ICR
fieldset/MISR: fieldset/MISR:
description: Master Timer Interrupt Status Register description: Master Timer Interrupt Status Register
fields: fields:
@ -322,22 +318,22 @@ fieldset/MISR:
array: array:
len: 4 len: 4
stride: 1 stride: 1
enum_read: EVENT enum: EVENT
- name: MREP - name: MREP
description: Master Repetition Interrupt Flag description: Master Repetition Interrupt Flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: EVENT enum: EVENT
- name: SYNC - name: SYNC
description: Sync Input Interrupt Flag description: Sync Input Interrupt Flag
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: EVENT enum: EVENT
- name: MUPD - name: MUPD
description: Master Update Interrupt Flag description: Master Update Interrupt Flag
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: EVENT enum: EVENT
fieldset/MPER: fieldset/MPER:
description: Master Timer Period Register description: Master Timer Period Register
fields: fields:
@ -766,17 +762,14 @@ fieldset/TIMXICR:
array: array:
len: 4 len: 4
stride: 1 stride: 1
enum_write: ICR
- name: REPC - name: REPC
description: Repetition Interrupt flag Clear description: Repetition Interrupt flag Clear
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_write: ICR
- name: UPDC - name: UPDC
description: Update Interrupt flag Clear description: Update Interrupt flag Clear
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_write: ICR
- name: CPTC - name: CPTC
description: Capture X Interrupt flag Clear description: Capture X Interrupt flag Clear
bit_offset: 7 bit_offset: 7
@ -784,7 +777,6 @@ fieldset/TIMXICR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_write: ICR
- name: SETRC - name: SETRC
description: Output X Set flag Clear description: Output X Set flag Clear
bit_offset: 9 bit_offset: 9
@ -793,7 +785,6 @@ fieldset/TIMXICR:
offsets: offsets:
- 0 - 0
- 2 - 2
enum_write: ICR
- name: RSTRC - name: RSTRC
description: Output X Reset flag Clear description: Output X Reset flag Clear
bit_offset: 10 bit_offset: 10
@ -802,17 +793,14 @@ fieldset/TIMXICR:
offsets: offsets:
- 0 - 0
- 2 - 2
enum_write: ICR
- name: RSTC - name: RSTC
description: Reset Interrupt flag Clear description: Reset Interrupt flag Clear
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
enum_write: ICR
- name: DLYPRTC - name: DLYPRTC
description: Delayed Protection Flag Clear description: Delayed Protection Flag Clear
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
enum_write: ICR
fieldset/TIMXISR: fieldset/TIMXISR:
description: Timerx Interrupt Status Register description: Timerx Interrupt Status Register
fields: fields:
@ -823,17 +811,17 @@ fieldset/TIMXISR:
array: array:
len: 4 len: 4
stride: 1 stride: 1
enum_read: EVENT enum: EVENT
- name: REP - name: REP
description: Repetition Interrupt Flag description: Repetition Interrupt Flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: EVENT enum: EVENT
- name: UPD - name: UPD
description: Update Interrupt Flag description: Update Interrupt Flag
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: EVENT enum: EVENT
- name: CPT - name: CPT
description: Capture X Interrupt Flag description: Capture X Interrupt Flag
bit_offset: 7 bit_offset: 7
@ -841,7 +829,7 @@ fieldset/TIMXISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: EVENT enum: EVENT
- name: SETR - name: SETR
description: Output X Set Interrupt Flag description: Output X Set Interrupt Flag
bit_offset: 9 bit_offset: 9
@ -850,7 +838,7 @@ fieldset/TIMXISR:
offsets: offsets:
- 0 - 0
- 2 - 2
enum_read: EVENT enum: EVENT
- name: RSTR - name: RSTR
description: Output X Reset Interrupt Flag description: Output X Reset Interrupt Flag
bit_offset: 10 bit_offset: 10
@ -859,27 +847,27 @@ fieldset/TIMXISR:
offsets: offsets:
- 0 - 0
- 2 - 2
enum_read: EVENT enum: EVENT
- name: RST - name: RST
description: Reset Interrupt Flag description: Reset Interrupt Flag
bit_offset: 13 bit_offset: 13
bit_size: 1 bit_size: 1
enum_read: EVENT enum: EVENT
- name: DLYPRT - name: DLYPRT
description: Delayed Protection Flag description: Delayed Protection Flag
bit_offset: 14 bit_offset: 14
bit_size: 1 bit_size: 1
enum_read: TIMAISR_DLYPRT enum: TIMAISR_DLYPRT
- name: CPPSTAT - name: CPPSTAT
description: Current Push Pull Status description: Current Push Pull Status
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum_read: CPPSTAT enum: CPPSTAT
- name: IPPSTAT - name: IPPSTAT
description: Idle Push Pull Status description: Idle Push Pull Status
bit_offset: 17 bit_offset: 17
bit_size: 1 bit_size: 1
enum_read: IPPSTAT enum: IPPSTAT
- name: OSTAT - name: OSTAT
description: Output X State description: Output X State
bit_offset: 18 bit_offset: 18
@ -887,7 +875,7 @@ fieldset/TIMXISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: OUTPUTSTATE enum: OUTPUTSTATE
- name: OCPY - name: OCPY
description: Output X Copy description: Output X Copy
bit_offset: 20 bit_offset: 20
@ -895,7 +883,7 @@ fieldset/TIMXISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: OUTPUTSTATE enum: OUTPUTSTATE
fieldset/TIMXOUTR: fieldset/TIMXOUTR:
description: Timerx Output Register description: Timerx Output Register
fields: fields:
@ -1356,12 +1344,6 @@ enum/FLTEN:
- name: Active - name: Active
description: Fault input is active and can disable HRTIM outputs description: Fault input is active and can disable HRTIM outputs
value: 1 value: 1
enum/ICR:
bit_size: 1
variants:
- name: Clear
description: Clears associated flag in ISR register
value: 1
enum/IDLEM: enum/IDLEM:
bit_size: 1 bit_size: 1
variants: variants:

9
data/registers/ltdc_v1.yaml
View File

@ -488,15 +488,6 @@ fieldset/WVPCR:
description: Window Vertical Stop Position description: Window Vertical Stop Position
bit_offset: 16 bit_offset: 16
bit_size: 11 bit_size: 11
enum/BF1:
bit_size: 3
variants:
- name: Constant
description: BF1 = constant alpha
value: 4
- name: Pixel
description: BF1 = pixel alpha * constant alpha
value: 6
enum/BF2: enum/BF2:
bit_size: 3 bit_size: 3
variants: variants:

100
data/registers/pwr_wl5.yaml
View File

@ -279,7 +279,6 @@ fieldset/EXTSCR:
description: Clear CPU1 Stop Standby flags description: Clear CPU1 Stop Standby flags
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum_write: CCSSFW
- name: C2CSSF - name: C2CSSF
description: lear CPU2 Stop Standby flags description: lear CPU2 Stop Standby flags
bit_offset: 1 bit_offset: 1
@ -347,17 +346,14 @@ fieldset/SCR:
array: array:
len: 3 len: 3
stride: 1 stride: 1
enum_write: CWUFW
- name: CWPVDF - name: CWPVDF
description: Clear wakeup PVD interrupt flag description: Clear wakeup PVD interrupt flag
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
enum_write: CWPVDFW
- name: CWRFBUSYF - name: CWRFBUSYF
description: Clear wakeup Radio BUSY flag description: Clear wakeup Radio BUSY flag
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
enum_write: CWRFBUSYFW
- name: CC2HF - name: CC2HF
description: lear CPU2 Hold interrupt flag description: lear CPU2 Hold interrupt flag
bit_offset: 14 bit_offset: 14
@ -486,12 +482,6 @@ enum/APC:
- name: Enabled - name: Enabled
description: PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os description: PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os
value: 1 value: 1
enum/CCSSFW:
bit_size: 1
variants:
- name: Clear
description: Setting this bit clears the C1STOPF and C1SBF bits
value: 1
enum/CDS: enum/CDS:
bit_size: 1 bit_size: 1
variants: variants:
@ -519,24 +509,6 @@ enum/CSTOPF:
- name: Stop - name: Stop
description: System has been in Stop 2 mode description: System has been in Stop 2 mode
value: 1 value: 1
enum/CWPVDFW:
bit_size: 1
variants:
- name: Clear
description: Setting this bit clears the WPVDF flag in the PWR_SR1. This bit is always read as 0.
value: 1
enum/CWRFBUSYFW:
bit_size: 1
variants:
- name: Clear
description: Setting this bit clears the WRFBUSYF flag in the PWR_SR1. This bit is always read 0.
value: 1
enum/CWUFW:
bit_size: 1
variants:
- name: Clear
description: Setting this bit clears the WUF2 flag in the PWR_SR1 register. This bit is always read as 0.
value: 1
enum/DBP: enum/DBP:
bit_size: 1 bit_size: 1
variants: variants:
@ -672,42 +644,6 @@ enum/NSS:
- name: High - name: High
description: Sub-GHz SPI NSS signal is at level high description: Sub-GHz SPI NSS signal is at level high
value: 1 value: 1
enum/PD:
bit_size: 1
variants:
- name: Disabled
description: "Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"
value: 0
- name: Enabled
description: "Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"
value: 1
enum/PDCRA_PD:
bit_size: 1
variants:
- name: Disabled
description: "Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"
value: 0
- name: Enabled
description: "Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"
value: 1
enum/PDCRB_PD:
bit_size: 1
variants:
- name: Disabled
description: "Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"
value: 0
- name: Enabled
description: "Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"
value: 1
enum/PDCRC_PD:
bit_size: 1
variants:
- name: Disabled
description: "Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"
value: 0
- name: Enabled
description: "Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"
value: 1
enum/PLS: enum/PLS:
bit_size: 3 bit_size: 3
variants: variants:
@ -735,42 +671,6 @@ enum/PLS:
- name: External - name: External
description: External input analog voltage PVD_IN (compared internally to VREFINT) description: External input analog voltage PVD_IN (compared internally to VREFINT)
value: 7 value: 7
enum/PU:
bit_size: 1
variants:
- name: Disabled
description: "Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"
value: 0
- name: Enabled
description: "Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set"
value: 1
enum/PUCRA_PU:
bit_size: 1
variants:
- name: Disabled
description: "Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"
value: 0
- name: Enabled
description: "Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set"
value: 1
enum/PUCRB_PU:
bit_size: 1
variants:
- name: Disabled
description: "Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"
value: 0
- name: Enabled
description: "Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set"
value: 1
enum/PUCRC_PU:
bit_size: 1
variants:
- name: Disabled
description: "Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"
value: 0
- name: Enabled
description: "Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set"
value: 1
enum/PVDE: enum/PVDE:
bit_size: 1 bit_size: 1
variants: variants:

4
data/registers/rcc_f0.yaml
View File

@ -445,7 +445,7 @@ fieldset/CFGR:
description: System Clock Switch Status description: System Clock Switch Status
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
enum_read: SWSR enum: SWS
- name: HPRE - name: HPRE
description: AHB prescaler description: AHB prescaler
bit_offset: 4 bit_offset: 4
@ -1058,7 +1058,7 @@ enum/SW:
- name: HSI48 - name: HSI48
description: HSI48 selected as system clock (when available) description: HSI48 selected as system clock (when available)
value: 3 value: 3
enum/SWSR: enum/SWS:
bit_size: 2 bit_size: 2
variants: variants:
- name: HSI - name: HSI

4
data/registers/rcc_f1.yaml
View File

@ -453,7 +453,7 @@ fieldset/CFGR:
description: System Clock Switch Status description: System Clock Switch Status
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
enum_read: SWSR enum: SWS
- name: HPRE - name: HPRE
description: AHB prescaler description: AHB prescaler
bit_offset: 4 bit_offset: 4
@ -829,7 +829,7 @@ enum/SW:
- name: PLL - name: PLL
description: PLL selected as system clock description: PLL selected as system clock
value: 2 value: 2
enum/SWSR: enum/SWS:
bit_size: 2 bit_size: 2
variants: variants:
- name: HSI - name: HSI

4
data/registers/rcc_f100.yaml
View File

@ -421,7 +421,7 @@ fieldset/CFGR:
description: System Clock Switch Status description: System Clock Switch Status
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
enum_read: SWSR enum: SWS
- name: HPRE - name: HPRE
description: AHB prescaler description: AHB prescaler
bit_offset: 4 bit_offset: 4
@ -851,7 +851,7 @@ enum/SW:
- name: PLL - name: PLL
description: PLL selected as system clock description: PLL selected as system clock
value: 2 value: 2
enum/SWSR: enum/SWS:
bit_size: 2 bit_size: 2
variants: variants:
- name: HSI - name: HSI

4
data/registers/rcc_f1cl.yaml
View File

@ -400,7 +400,7 @@ fieldset/CFGR:
description: System Clock Switch Status description: System Clock Switch Status
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
enum_read: SWSR enum: SWS
- name: HPRE - name: HPRE
description: AHB prescaler description: AHB prescaler
bit_offset: 4 bit_offset: 4
@ -938,7 +938,7 @@ enum/SW:
- name: PLL - name: PLL
description: PLL selected as system clock description: PLL selected as system clock
value: 2 value: 2
enum/SWSR: enum/SWS:
bit_size: 2 bit_size: 2
variants: variants:
- name: HSI - name: HSI

4
data/registers/rcc_f2.yaml
View File

@ -895,7 +895,7 @@ fieldset/CFGR:
description: System clock switch status description: System clock switch status
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
enum_read: SWSR enum: SWS
- name: HPRE - name: HPRE
description: AHB prescaler description: AHB prescaler
bit_offset: 4 bit_offset: 4
@ -1338,7 +1338,7 @@ enum/SW:
- name: PLL - name: PLL
description: PLL selected as system clock description: PLL selected as system clock
value: 2 value: 2
enum/SWSR: enum/SWS:
bit_size: 2 bit_size: 2
variants: variants:
- name: HSI - name: HSI

4
data/registers/rcc_f3.yaml
View File

@ -581,7 +581,7 @@ fieldset/CFGR:
description: System Clock Switch Status description: System Clock Switch Status
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
enum_read: SWSR enum: SWS
- name: HPRE - name: HPRE
description: AHB prescaler description: AHB prescaler
bit_offset: 4 bit_offset: 4
@ -1327,7 +1327,7 @@ enum/SW:
- name: PLL - name: PLL
description: PLL selected as system clock description: PLL selected as system clock
value: 2 value: 2
enum/SWSR: enum/SWS:
bit_size: 2 bit_size: 2
variants: variants:
- name: HSI - name: HSI

13
data/registers/rcc_f4.yaml
View File

@ -1224,7 +1224,7 @@ fieldset/CFGR:
description: System clock switch status description: System clock switch status
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
enum_read: SWSR enum: SWS
- name: HPRE - name: HPRE
description: AHB prescaler description: AHB prescaler
bit_offset: 4 bit_offset: 4
@ -1844,15 +1844,6 @@ enum/I2S1SRC:
- name: HSI_HSE - name: HSI_HSE
description: "I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])" description: "I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])"
value: 3 value: 3
enum/I2SSRC:
bit_size: 1
variants:
- name: PLLI2S
description: PLLI2S clock used as I2S clock source
value: 0
- name: CKIN
description: External clock mapped on the I2S_CKIN pin used as I2S clock source
value: 1
enum/ISSRC: enum/ISSRC:
bit_size: 1 bit_size: 1
variants: variants:
@ -2534,7 +2525,7 @@ enum/SW:
- name: PLL - name: PLL
description: PLL selected as system clock description: PLL selected as system clock
value: 2 value: 2
enum/SWSR: enum/SWS:
bit_size: 2 bit_size: 2
variants: variants:
- name: HSI - name: HSI

4
data/registers/rcc_f410.yaml
View File

@ -505,7 +505,7 @@ fieldset/CFGR:
description: System clock switch status description: System clock switch status
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
enum_read: SWSR enum: SWS
- name: HPRE - name: HPRE
description: AHB prescaler description: AHB prescaler
bit_offset: 4 bit_offset: 4
@ -984,7 +984,7 @@ enum/SW:
- name: PLL - name: PLL
description: PLL selected as system clock description: PLL selected as system clock
value: 2 value: 2
enum/SWSR: enum/SWS:
bit_size: 2 bit_size: 2
variants: variants:
- name: HSI - name: HSI

4
data/registers/rcc_f7.yaml
View File

@ -1216,7 +1216,7 @@ fieldset/CFGR:
description: System clock switch status description: System clock switch status
bit_offset: 2 bit_offset: 2
bit_size: 2 bit_size: 2
enum_read: SWSR enum: SWS
- name: HPRE - name: HPRE
description: AHB prescaler description: AHB prescaler
bit_offset: 4 bit_offset: 4
@ -2202,7 +2202,7 @@ enum/SW:
- name: PLL - name: PLL
description: PLL selected as system clock description: PLL selected as system clock
value: 2 value: 2
enum/SWSR: enum/SWS:
bit_size: 2 bit_size: 2
variants: variants:
- name: HSI - name: HSI

4
data/registers/rcc_h7.yaml
View File

@ -2761,7 +2761,7 @@ fieldset/CFGR:
description: System clock switch status description: System clock switch status
bit_offset: 3 bit_offset: 3
bit_size: 3 bit_size: 3
enum_read: SWSR enum: SWS
- name: STOPWUCK - name: STOPWUCK
description: System clock selection after a wake up from system Stop description: System clock selection after a wake up from system Stop
bit_offset: 6 bit_offset: 6
@ -4236,7 +4236,7 @@ enum/SWPSEL:
- name: HSI_KER - name: HSI_KER
description: hsi_ker selected as peripheral clock description: hsi_ker selected as peripheral clock
value: 1 value: 1
enum/SWSR: enum/SWS:
bit_size: 3 bit_size: 3
variants: variants:
- name: HSI - name: HSI

4
data/registers/rcc_h7ab.yaml
View File

@ -1728,7 +1728,7 @@ fieldset/CFGR:
description: System clock switch status description: System clock switch status
bit_offset: 3 bit_offset: 3
bit_size: 3 bit_size: 3
enum_read: SWSR enum: SWS
- name: STOPWUCK - name: STOPWUCK
description: System clock selection after a wake up from system Stop description: System clock selection after a wake up from system Stop
bit_offset: 6 bit_offset: 6
@ -3171,7 +3171,7 @@ enum/SWPSEL:
- name: HSI_KER - name: HSI_KER
description: hsi_ker selected as peripheral clock description: hsi_ker selected as peripheral clock
value: 1 value: 1
enum/SWSR: enum/SWS:
bit_size: 3 bit_size: 3
variants: variants:
- name: HSI - name: HSI

110
data/registers/rtc_v2f0.yaml
View File

@ -319,12 +319,12 @@ fieldset/ISR:
array: array:
len: 1 len: 1
stride: 1 stride: 1
enum_read: ALRWFR enum: ALRWF
- name: WUTWF - name: WUTWF
description: Wakeup timer write flag description: Wakeup timer write flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WUTWFR enum: WUTWF
- name: SHPF - name: SHPF
description: Shift operation pending description: Shift operation pending
bit_offset: 3 bit_offset: 3
@ -333,18 +333,16 @@ fieldset/ISR:
description: Initialization status flag description: Initialization status flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: INITSR enum: INITS
- name: RSF - name: RSF
description: Registers synchronization flag description: Registers synchronization flag
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: RSFR
enum_write: RSFW
- name: INITF - name: INITF
description: Initialization flag description: Initialization flag
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: INITFR enum: INITF
- name: INIT - name: INIT
description: Initialization mode description: Initialization mode
bit_offset: 7 bit_offset: 7
@ -357,26 +355,18 @@ fieldset/ISR:
array: array:
len: 1 len: 1
stride: 1 stride: 1
enum_read: ALRFR
enum_write: ALRFW
- name: WUTF - name: WUTF
description: Wakeup timer flag description: Wakeup timer flag
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
enum_read: WUTFR
enum_write: WUTFW
- name: TSF - name: TSF
description: Timestamp flag description: Timestamp flag
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
enum_read: TSFR
enum_write: TSFW
- name: TSOVF - name: TSOVF
description: Timestamp overflow flag description: Timestamp overflow flag
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
enum_read: TSOVFR
enum_write: TSOVFW
- name: TAMPF - name: TAMPF
description: Tamper detection flag description: Tamper detection flag
bit_offset: 13 bit_offset: 13
@ -384,13 +374,10 @@ fieldset/ISR:
array: array:
len: 3 len: 3
stride: 1 stride: 1
enum_read: TAMPFR
enum_write: TAMPFW
- name: RECALPF - name: RECALPF
description: Recalibration pending flag description: Recalibration pending flag
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum_read: RECALPFR
fieldset/PRER: fieldset/PRER:
description: Prescaler register description: Prescaler register
fields: fields:
@ -608,18 +595,6 @@ fieldset/WUTR:
description: Wakeup auto-reload value bits description: Wakeup auto-reload value bits
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/ALRFR:
bit_size: 1
variants:
- name: Match
description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
value: 1
enum/ALRFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/ALRMR_MSK: enum/ALRMR_MSK:
bit_size: 1 bit_size: 1
variants: variants:
@ -647,7 +622,7 @@ enum/ALRMR_WDSEL:
- name: WeekDay - name: WeekDay
description: "DU[3:0] represents the week day. DT[1:0] is don’t care" description: "DU[3:0] represents the week day. DT[1:0] is don’t care"
value: 1 value: 1
enum/ALRWFR: enum/ALRWF:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed
@ -713,7 +688,7 @@ enum/INIT:
- name: InitMode - name: InitMode
description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."
value: 1 value: 1
enum/INITFR: enum/INITF:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotAllowed - name: NotAllowed
@ -722,7 +697,7 @@ enum/INITFR:
- name: Allowed - name: Allowed
description: Calendar registers update is allowed description: Calendar registers update is allowed
value: 1 value: 1
enum/INITSR: enum/INITS:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotInitalized - name: NotInitalized
@ -770,12 +745,6 @@ enum/POL:
- name: Low - name: Low
description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
value: 1 value: 1
enum/RECALPFR:
bit_size: 1
variants:
- name: Pending
description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0"
value: 1
enum/REFCKON: enum/REFCKON:
bit_size: 1 bit_size: 1
variants: variants:
@ -785,21 +754,6 @@ enum/REFCKON:
- name: Enabled - name: Enabled
description: RTC_REFIN detection enabled description: RTC_REFIN detection enabled
value: 1 value: 1
enum/RSFR:
bit_size: 1
variants:
- name: NotSynced
description: Calendar shadow registers not yet synchronized
value: 0
- name: Synced
description: Calendar shadow registers synchronized
value: 1
enum/RSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TAMPFLT: enum/TAMPFLT:
bit_size: 2 bit_size: 2
variants: variants:
@ -815,12 +769,6 @@ enum/TAMPFLT:
- name: Samples8 - name: Samples8
description: Tamper event is activated after 8 consecutive samples at the active level description: Tamper event is activated after 8 consecutive samples at the active level
value: 3 value: 3
enum/TAMPFR:
bit_size: 1
variants:
- name: Tampered
description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
value: 1
enum/TAMPFREQ: enum/TAMPFREQ:
bit_size: 3 bit_size: 3
variants: variants:
@ -848,12 +796,6 @@ enum/TAMPFREQ:
- name: Div256 - name: Div256
description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
value: 7 value: 7
enum/TAMPFW:
bit_size: 1
variants:
- name: Clear
description: Flag cleared by software writing 0
value: 0
enum/TAMPPRCH: enum/TAMPPRCH:
bit_size: 2 bit_size: 2
variants: variants:
@ -896,30 +838,6 @@ enum/TSEDGE:
- name: FallingEdge - name: FallingEdge
description: RTC_TS input falling edge generates a time-stamp event description: RTC_TS input falling edge generates a time-stamp event
value: 1 value: 1
enum/TSFR:
bit_size: 1
variants:
- name: TimestampEvent
description: This flag is set by hardware when a time-stamp event occurs
value: 1
enum/TSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TSOVFR:
bit_size: 1
variants:
- name: Overflow
description: This flag is set by hardware when a timestamp event occurs while TSF is already set
value: 1
enum/TSOVFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUCKSEL: enum/WUCKSEL:
bit_size: 3 bit_size: 3
variants: variants:
@ -941,19 +859,7 @@ enum/WUCKSEL:
- name: ClockSpareWithOffset - name: ClockSpareWithOffset
description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
value: 6 value: 6
enum/WUTFR: enum/WUTWF:
bit_size: 1
variants:
- name: Zero
description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
value: 1
enum/WUTFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUTWFR:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed

133
data/registers/rtc_v2f2.yaml
View File

@ -269,28 +269,26 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRWFR enum: ALRWF
- name: WUTWF - name: WUTWF
description: Wakeup timer write flag description: Wakeup timer write flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WUTWFR enum: WUTWF
- name: INITS - name: INITS
description: Initialization status flag description: Initialization status flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: INITSR enum: INITS
- name: RSF - name: RSF
description: Registers synchronization flag description: Registers synchronization flag
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: RSFR
enum_write: RSFW
- name: INITF - name: INITF
description: Initialization flag description: Initialization flag
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: INITFR enum: INITF
- name: INIT - name: INIT
description: Initialization mode description: Initialization mode
bit_offset: 7 bit_offset: 7
@ -303,26 +301,18 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRFR
enum_write: ALRFW
- name: WUTF - name: WUTF
description: Wakeup timer flag description: Wakeup timer flag
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
enum_read: WUTFR
enum_write: WUTFW
- name: TSF - name: TSF
description: Timestamp flag description: Timestamp flag
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
enum_read: TSFR
enum_write: TSFW
- name: TSOVF - name: TSOVF
description: Timestamp overflow flag description: Timestamp overflow flag
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
enum_read: TSOVFR
enum_write: TSOVFW
- name: TAMPF - name: TAMPF
description: Tamper detection flag description: Tamper detection flag
bit_offset: 13 bit_offset: 13
@ -330,8 +320,6 @@ fieldset/ISR:
array: array:
len: 1 len: 1
stride: 1 stride: 1
enum_read: TAMPFR
enum_write: TAMPFW
fieldset/PRER: fieldset/PRER:
description: Prescaler register description: Prescaler register
fields: fields:
@ -478,18 +466,6 @@ fieldset/WUTR:
description: Wakeup auto-reload value bits description: Wakeup auto-reload value bits
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/ALRFR:
bit_size: 1
variants:
- name: Match
description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
value: 1
enum/ALRFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/ALRMR_MSK: enum/ALRMR_MSK:
bit_size: 1 bit_size: 1
variants: variants:
@ -517,7 +493,7 @@ enum/ALRMR_WDSEL:
- name: WeekDay - name: WeekDay
description: "DU[3:0] represents the week day. DT[1:0] is don’t care" description: "DU[3:0] represents the week day. DT[1:0] is don’t care"
value: 1 value: 1
enum/ALRWFR: enum/ALRWF:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed
@ -535,36 +511,6 @@ enum/AMPM:
- name: PM - name: PM
description: PM description: PM
value: 1 value: 1
enum/CALP:
bit_size: 1
variants:
- name: NoChange
description: No RTCCLK pulses are added
value: 0
- name: IncreaseFreq
description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)
value: 1
enum/CALW16:
bit_size: 1
variants:
- name: Sixteen_Second
description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1"
value: 1
enum/CALW8:
bit_size: 1
variants:
- name: Eight_Second
description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected"
value: 1
enum/FMT:
bit_size: 1
variants:
- name: Twenty_Four_Hour
description: 24 hour/day format
value: 0
- name: AM_PM
description: AM/PM hour format
value: 1
enum/INIT: enum/INIT:
bit_size: 1 bit_size: 1
variants: variants:
@ -574,7 +520,7 @@ enum/INIT:
- name: InitMode - name: InitMode
description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."
value: 1 value: 1
enum/INITFR: enum/INITF:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotAllowed - name: NotAllowed
@ -583,7 +529,7 @@ enum/INITFR:
- name: Allowed - name: Allowed
description: Calendar registers update is allowed description: Calendar registers update is allowed
value: 1 value: 1
enum/INITSR: enum/INITS:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotInitalized - name: NotInitalized
@ -625,33 +571,6 @@ enum/REFCKON:
- name: Enabled - name: Enabled
description: RTC_REFIN detection enabled description: RTC_REFIN detection enabled
value: 1 value: 1
enum/RSFR:
bit_size: 1
variants:
- name: NotSynced
description: Calendar shadow registers not yet synchronized
value: 0
- name: Synced
description: Calendar shadow registers synchronized
value: 1
enum/RSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TAMPFR:
bit_size: 1
variants:
- name: Tampered
description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
value: 1
enum/TAMPFW:
bit_size: 1
variants:
- name: Clear
description: Flag cleared by software writing 0
value: 0
enum/TAMPTRG: enum/TAMPTRG:
bit_size: 1 bit_size: 1
variants: variants:
@ -670,30 +589,6 @@ enum/TSEDGE:
- name: FallingEdge - name: FallingEdge
description: RTC_TS input falling edge generates a time-stamp event description: RTC_TS input falling edge generates a time-stamp event
value: 1 value: 1
enum/TSFR:
bit_size: 1
variants:
- name: TimestampEvent
description: This flag is set by hardware when a time-stamp event occurs
value: 1
enum/TSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TSOVFR:
bit_size: 1
variants:
- name: Overflow
description: This flag is set by hardware when a timestamp event occurs while TSF is already set
value: 1
enum/TSOVFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUCKSEL: enum/WUCKSEL:
bit_size: 3 bit_size: 3
variants: variants:
@ -715,19 +610,7 @@ enum/WUCKSEL:
- name: ClockSpareWithOffset - name: ClockSpareWithOffset
description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
value: 6 value: 6
enum/WUTFR: enum/WUTWF:
bit_size: 1
variants:
- name: Zero
description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
value: 1
enum/WUTFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUTWFR:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed

107
data/registers/rtc_v2f3.yaml
View File

@ -319,12 +319,12 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRWFR enum: ALRWF
- name: WUTWF - name: WUTWF
description: Wakeup timer write flag description: Wakeup timer write flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WUTWFR enum: WUTWF
- name: SHPF - name: SHPF
description: Shift operation pending description: Shift operation pending
bit_offset: 3 bit_offset: 3
@ -333,18 +333,16 @@ fieldset/ISR:
description: Initialization status flag description: Initialization status flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: INITSR enum: INITS
- name: RSF - name: RSF
description: Registers synchronization flag description: Registers synchronization flag
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: RSFR
enum_write: RSFW
- name: INITF - name: INITF
description: Initialization flag description: Initialization flag
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: INITFR enum: INITF
- name: INIT - name: INIT
description: Initialization mode description: Initialization mode
bit_offset: 7 bit_offset: 7
@ -357,26 +355,18 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRFR
enum_write: ALRFW
- name: WUTF - name: WUTF
description: Wakeup timer flag description: Wakeup timer flag
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
enum_read: WUTFR
enum_write: WUTFW
- name: TSF - name: TSF
description: Timestamp flag description: Timestamp flag
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
enum_read: TSFR
enum_write: TSFW
- name: TSOVF - name: TSOVF
description: Timestamp overflow flag description: Timestamp overflow flag
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
enum_read: TSOVFR
enum_write: TSOVFW
- name: TAMPF - name: TAMPF
description: Tamper detection flag description: Tamper detection flag
bit_offset: 13 bit_offset: 13
@ -384,13 +374,11 @@ fieldset/ISR:
array: array:
len: 3 len: 3
stride: 1 stride: 1
enum_read: TAMPFR
enum_write: TAMPFW
- name: RECALPF - name: RECALPF
description: Recalibration pending flag description: Recalibration pending flag
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum_read: RECALPFR enum: RECALPF
fieldset/PRER: fieldset/PRER:
description: Prescaler register description: Prescaler register
fields: fields:
@ -606,18 +594,6 @@ fieldset/WUTR:
description: Wakeup auto-reload value bits description: Wakeup auto-reload value bits
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/ALRFR:
bit_size: 1
variants:
- name: Match
description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
value: 1
enum/ALRFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/ALRMR_MSK: enum/ALRMR_MSK:
bit_size: 1 bit_size: 1
variants: variants:
@ -645,7 +621,7 @@ enum/ALRMR_WDSEL:
- name: WeekDay - name: WeekDay
description: "DU[3:0] represents the week day. DT[1:0] is don’t care" description: "DU[3:0] represents the week day. DT[1:0] is don’t care"
value: 1 value: 1
enum/ALRWFR: enum/ALRWF:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed
@ -711,7 +687,7 @@ enum/INIT:
- name: InitMode - name: InitMode
description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."
value: 1 value: 1
enum/INITFR: enum/INITF:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotAllowed - name: NotAllowed
@ -720,7 +696,7 @@ enum/INITFR:
- name: Allowed - name: Allowed
description: Calendar registers update is allowed description: Calendar registers update is allowed
value: 1 value: 1
enum/INITSR: enum/INITS:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotInitalized - name: NotInitalized
@ -771,7 +747,7 @@ enum/POL:
- name: Low - name: Low
description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
value: 1 value: 1
enum/RECALPFR: enum/RECALPF:
bit_size: 1 bit_size: 1
variants: variants:
- name: Pending - name: Pending
@ -786,21 +762,6 @@ enum/REFCKON:
- name: Enabled - name: Enabled
description: RTC_REFIN detection enabled description: RTC_REFIN detection enabled
value: 1 value: 1
enum/RSFR:
bit_size: 1
variants:
- name: NotSynced
description: Calendar shadow registers not yet synchronized
value: 0
- name: Synced
description: Calendar shadow registers synchronized
value: 1
enum/RSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TAMPFLT: enum/TAMPFLT:
bit_size: 2 bit_size: 2
variants: variants:
@ -816,12 +777,6 @@ enum/TAMPFLT:
- name: Samples8 - name: Samples8
description: Tamper event is activated after 8 consecutive samples at the active level description: Tamper event is activated after 8 consecutive samples at the active level
value: 3 value: 3
enum/TAMPFR:
bit_size: 1
variants:
- name: Tampered
description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
value: 1
enum/TAMPFREQ: enum/TAMPFREQ:
bit_size: 3 bit_size: 3
variants: variants:
@ -849,12 +804,6 @@ enum/TAMPFREQ:
- name: Div256 - name: Div256
description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
value: 7 value: 7
enum/TAMPFW:
bit_size: 1
variants:
- name: Clear
description: Flag cleared by software writing 0
value: 0
enum/TAMPPRCH: enum/TAMPPRCH:
bit_size: 2 bit_size: 2
variants: variants:
@ -897,30 +846,6 @@ enum/TSEDGE:
- name: FallingEdge - name: FallingEdge
description: RTC_TS input falling edge generates a time-stamp event description: RTC_TS input falling edge generates a time-stamp event
value: 1 value: 1
enum/TSFR:
bit_size: 1
variants:
- name: TimestampEvent
description: This flag is set by hardware when a time-stamp event occurs
value: 1
enum/TSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TSOVFR:
bit_size: 1
variants:
- name: Overflow
description: This flag is set by hardware when a timestamp event occurs while TSF is already set
value: 1
enum/TSOVFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUCKSEL: enum/WUCKSEL:
bit_size: 3 bit_size: 3
variants: variants:
@ -942,19 +867,7 @@ enum/WUCKSEL:
- name: ClockSpareWithOffset - name: ClockSpareWithOffset
description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
value: 6 value: 6
enum/WUTFR: enum/WUTWF:
bit_size: 1
variants:
- name: Zero
description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
value: 1
enum/WUTFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUTWFR:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed

122
data/registers/rtc_v2f4.yaml
View File

@ -338,12 +338,12 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRWFR enum: ALRWF
- name: WUTWF - name: WUTWF
description: Wakeup timer write flag description: Wakeup timer write flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WUTWFR enum: WUTWF
- name: SHPF - name: SHPF
description: Shift operation pending description: Shift operation pending
bit_offset: 3 bit_offset: 3
@ -352,18 +352,16 @@ fieldset/ISR:
description: Initialization status flag description: Initialization status flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: INITSR enum: INITS
- name: RSF - name: RSF
description: Registers synchronization flag description: Registers synchronization flag
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: RSFR
enum_write: RSFW
- name: INITF - name: INITF
description: Initialization flag description: Initialization flag
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: INITFR enum: INITF
- name: INIT - name: INIT
description: Initialization mode description: Initialization mode
bit_offset: 7 bit_offset: 7
@ -376,26 +374,18 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRFR
enum_write: ALRFW
- name: WUTF - name: WUTF
description: Wakeup timer flag description: Wakeup timer flag
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
enum_read: WUTFR
enum_write: WUTFW
- name: TSF - name: TSF
description: Timestamp flag description: Timestamp flag
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
enum_read: TSFR
enum_write: TSFW
- name: TSOVF - name: TSOVF
description: Timestamp overflow flag description: Timestamp overflow flag
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
enum_read: TSOVFR
enum_write: TSOVFW
- name: TAMPF - name: TAMPF
description: Tamper detection flag description: Tamper detection flag
bit_offset: 13 bit_offset: 13
@ -403,13 +393,11 @@ fieldset/ISR:
array: array:
len: 3 len: 3
stride: 1 stride: 1
enum_read: TAMPFR
enum_write: TAMPFW
- name: RECALPF - name: RECALPF
description: Recalibration pending flag description: Recalibration pending flag
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum_read: RECALPFR enum: RECALPF
fieldset/PRER: fieldset/PRER:
description: Prescaler register description: Prescaler register
fields: fields:
@ -607,18 +595,6 @@ fieldset/WUTR:
description: Wakeup auto-reload value bits description: Wakeup auto-reload value bits
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/ALRFR:
bit_size: 1
variants:
- name: Match
description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
value: 1
enum/ALRFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/ALRMR_MSK: enum/ALRMR_MSK:
bit_size: 1 bit_size: 1
variants: variants:
@ -646,7 +622,7 @@ enum/ALRMR_WDSEL:
- name: WeekDay - name: WeekDay
description: "DU[3:0] represents the week day. DT[1:0] is don’t care" description: "DU[3:0] represents the week day. DT[1:0] is don’t care"
value: 1 value: 1
enum/ALRWFR: enum/ALRWF:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed
@ -712,7 +688,7 @@ enum/INIT:
- name: InitMode - name: InitMode
description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."
value: 1 value: 1
enum/INITFR: enum/INITF:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotAllowed - name: NotAllowed
@ -721,7 +697,7 @@ enum/INITFR:
- name: Allowed - name: Allowed
description: Calendar registers update is allowed description: Calendar registers update is allowed
value: 1 value: 1
enum/INITSR: enum/INITS:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotInitalized - name: NotInitalized
@ -754,7 +730,7 @@ enum/POL:
- name: Low - name: Low
description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
value: 1 value: 1
enum/RECALPFR: enum/RECALPF:
bit_size: 1 bit_size: 1
variants: variants:
- name: Pending - name: Pending
@ -769,36 +745,6 @@ enum/REFCKON:
- name: Enabled - name: Enabled
description: RTC_REFIN detection enabled description: RTC_REFIN detection enabled
value: 1 value: 1
enum/RSFR:
bit_size: 1
variants:
- name: NotSynced
description: Calendar shadow registers not yet synchronized
value: 0
- name: Synced
description: Calendar shadow registers synchronized
value: 1
enum/RSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/SHPFR:
bit_size: 1
variants:
- name: NoShiftPending
description: No shift operation is pending
value: 0
- name: ShiftPending
description: A shift operation is pending
value: 1
enum/SUB1HW:
bit_size: 1
variants:
- name: Sub1
description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
value: 1
enum/TAMPFLT: enum/TAMPFLT:
bit_size: 2 bit_size: 2
variants: variants:
@ -814,12 +760,6 @@ enum/TAMPFLT:
- name: Samples8 - name: Samples8
description: Tamper event is activated after 8 consecutive samples at the active level description: Tamper event is activated after 8 consecutive samples at the active level
value: 3 value: 3
enum/TAMPFR:
bit_size: 1
variants:
- name: Tampered
description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
value: 1
enum/TAMPFREQ: enum/TAMPFREQ:
bit_size: 3 bit_size: 3
variants: variants:
@ -847,12 +787,6 @@ enum/TAMPFREQ:
- name: Div256 - name: Div256
description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
value: 7 value: 7
enum/TAMPFW:
bit_size: 1
variants:
- name: Clear
description: Flag cleared by software writing 0
value: 0
enum/TAMPPRCH: enum/TAMPPRCH:
bit_size: 2 bit_size: 2
variants: variants:
@ -895,30 +829,6 @@ enum/TSEDGE:
- name: FallingEdge - name: FallingEdge
description: RTC_TS input falling edge generates a time-stamp event description: RTC_TS input falling edge generates a time-stamp event
value: 1 value: 1
enum/TSFR:
bit_size: 1
variants:
- name: TimestampEvent
description: This flag is set by hardware when a time-stamp event occurs
value: 1
enum/TSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TSOVFR:
bit_size: 1
variants:
- name: Overflow
description: This flag is set by hardware when a timestamp event occurs while TSF is already set
value: 1
enum/TSOVFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUCKSEL: enum/WUCKSEL:
bit_size: 3 bit_size: 3
variants: variants:
@ -940,19 +850,7 @@ enum/WUCKSEL:
- name: ClockSpareWithOffset - name: ClockSpareWithOffset
description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
value: 6 value: 6
enum/WUTFR: enum/WUTWF:
bit_size: 1
variants:
- name: Zero
description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
value: 1
enum/WUTFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUTWFR:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed

107
data/registers/rtc_v2f7.yaml
View File

@ -327,12 +327,12 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRWFR enum: ALRWF
- name: WUTWF - name: WUTWF
description: Wakeup timer write flag description: Wakeup timer write flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WUTWFR enum: WUTWF
- name: SHPF - name: SHPF
description: Shift operation pending description: Shift operation pending
bit_offset: 3 bit_offset: 3
@ -341,18 +341,16 @@ fieldset/ISR:
description: Initialization status flag description: Initialization status flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: INITSR enum: INITS
- name: RSF - name: RSF
description: Registers synchronization flag description: Registers synchronization flag
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: RSFR
enum_write: RSFW
- name: INITF - name: INITF
description: Initialization flag description: Initialization flag
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: INITFR enum: INITF
- name: INIT - name: INIT
description: Initialization mode description: Initialization mode
bit_offset: 7 bit_offset: 7
@ -365,26 +363,18 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRFR
enum_write: ALRFW
- name: WUTF - name: WUTF
description: Wakeup timer flag description: Wakeup timer flag
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
enum_read: WUTFR
enum_write: WUTFW
- name: TSF - name: TSF
description: Timestamp flag description: Timestamp flag
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
enum_read: TSFR
enum_write: TSFW
- name: TSOVF - name: TSOVF
description: Timestamp overflow flag description: Timestamp overflow flag
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
enum_read: TSOVFR
enum_write: TSOVFW
- name: TAMPF - name: TAMPF
description: Tamper detection flag description: Tamper detection flag
bit_offset: 13 bit_offset: 13
@ -392,13 +382,11 @@ fieldset/ISR:
array: array:
len: 3 len: 3
stride: 1 stride: 1
enum_read: TAMPFR
enum_write: TAMPFW
- name: RECALPF - name: RECALPF
description: Recalibration pending flag description: Recalibration pending flag
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum_read: RECALPFR enum: RECALPF
- name: ITSF - name: ITSF
description: Internal time-stamp flag description: Internal time-stamp flag
bit_offset: 17 bit_offset: 17
@ -622,18 +610,6 @@ fieldset/WUTR:
description: Wakeup auto-reload value bits description: Wakeup auto-reload value bits
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/ALRFR:
bit_size: 1
variants:
- name: Match
description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
value: 1
enum/ALRFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/ALRMR_MSK: enum/ALRMR_MSK:
bit_size: 1 bit_size: 1
variants: variants:
@ -661,7 +637,7 @@ enum/ALRMR_WDSEL:
- name: WeekDay - name: WeekDay
description: "DU[3:0] represents the week day. DT[1:0] is don’t care" description: "DU[3:0] represents the week day. DT[1:0] is don’t care"
value: 1 value: 1
enum/ALRWFR: enum/ALRWF:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed
@ -727,7 +703,7 @@ enum/INIT:
- name: InitMode - name: InitMode
description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."
value: 1 value: 1
enum/INITFR: enum/INITF:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotAllowed - name: NotAllowed
@ -736,7 +712,7 @@ enum/INITFR:
- name: Allowed - name: Allowed
description: Calendar registers update is allowed description: Calendar registers update is allowed
value: 1 value: 1
enum/INITSR: enum/INITS:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotInitalized - name: NotInitalized
@ -769,7 +745,7 @@ enum/POL:
- name: Low - name: Low
description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
value: 1 value: 1
enum/RECALPFR: enum/RECALPF:
bit_size: 1 bit_size: 1
variants: variants:
- name: Pending - name: Pending
@ -784,21 +760,6 @@ enum/REFCKON:
- name: Enabled - name: Enabled
description: RTC_REFIN detection enabled description: RTC_REFIN detection enabled
value: 1 value: 1
enum/RSFR:
bit_size: 1
variants:
- name: NotSynced
description: Calendar shadow registers not yet synchronized
value: 0
- name: Synced
description: Calendar shadow registers synchronized
value: 1
enum/RSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TAMPFLT: enum/TAMPFLT:
bit_size: 2 bit_size: 2
variants: variants:
@ -814,12 +775,6 @@ enum/TAMPFLT:
- name: Samples8 - name: Samples8
description: Tamper event is activated after 8 consecutive samples at the active level description: Tamper event is activated after 8 consecutive samples at the active level
value: 3 value: 3
enum/TAMPFR:
bit_size: 1
variants:
- name: Tampered
description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
value: 1
enum/TAMPFREQ: enum/TAMPFREQ:
bit_size: 3 bit_size: 3
variants: variants:
@ -847,12 +802,6 @@ enum/TAMPFREQ:
- name: Div256 - name: Div256
description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
value: 7 value: 7
enum/TAMPFW:
bit_size: 1
variants:
- name: Clear
description: Flag cleared by software writing 0
value: 0
enum/TAMPPRCH: enum/TAMPPRCH:
bit_size: 2 bit_size: 2
variants: variants:
@ -895,30 +844,6 @@ enum/TSEDGE:
- name: FallingEdge - name: FallingEdge
description: RTC_TS input falling edge generates a time-stamp event description: RTC_TS input falling edge generates a time-stamp event
value: 1 value: 1
enum/TSFR:
bit_size: 1
variants:
- name: TimestampEvent
description: This flag is set by hardware when a time-stamp event occurs
value: 1
enum/TSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TSOVFR:
bit_size: 1
variants:
- name: Overflow
description: This flag is set by hardware when a timestamp event occurs while TSF is already set
value: 1
enum/TSOVFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUCKSEL: enum/WUCKSEL:
bit_size: 3 bit_size: 3
variants: variants:
@ -940,19 +865,7 @@ enum/WUCKSEL:
- name: ClockSpareWithOffset - name: ClockSpareWithOffset
description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
value: 6 value: 6
enum/WUTFR: enum/WUTWF:
bit_size: 1
variants:
- name: Zero
description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
value: 1
enum/WUTFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUTWFR:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed

107
data/registers/rtc_v2h7.yaml
View File

@ -327,12 +327,12 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRWFR enum: ALRWF
- name: WUTWF - name: WUTWF
description: Wakeup timer write flag description: Wakeup timer write flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WUTWFR enum: WUTWF
- name: SHPF - name: SHPF
description: Shift operation pending description: Shift operation pending
bit_offset: 3 bit_offset: 3
@ -341,18 +341,16 @@ fieldset/ISR:
description: Initialization status flag description: Initialization status flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: INITSR enum: INITS
- name: RSF - name: RSF
description: Registers synchronization flag description: Registers synchronization flag
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: RSFR
enum_write: RSFW
- name: INITF - name: INITF
description: Initialization flag description: Initialization flag
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: INITFR enum: INITF
- name: INIT - name: INIT
description: Initialization mode description: Initialization mode
bit_offset: 7 bit_offset: 7
@ -365,26 +363,18 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRFR
enum_write: ALRFW
- name: WUTF - name: WUTF
description: Wakeup timer flag description: Wakeup timer flag
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
enum_read: WUTFR
enum_write: WUTFW
- name: TSF - name: TSF
description: Timestamp flag description: Timestamp flag
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
enum_read: TSFR
enum_write: TSFW
- name: TSOVF - name: TSOVF
description: Timestamp overflow flag description: Timestamp overflow flag
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
enum_read: TSOVFR
enum_write: TSOVFW
- name: TAMPF - name: TAMPF
description: Tamper detection flag description: Tamper detection flag
bit_offset: 13 bit_offset: 13
@ -392,13 +382,11 @@ fieldset/ISR:
array: array:
len: 3 len: 3
stride: 1 stride: 1
enum_read: TAMPFR
enum_write: TAMPFW
- name: RECALPF - name: RECALPF
description: Recalibration pending flag description: Recalibration pending flag
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum_read: RECALPFR enum: RECALPF
- name: ITSF - name: ITSF
description: Internal time-stamp flag description: Internal time-stamp flag
bit_offset: 17 bit_offset: 17
@ -622,18 +610,6 @@ fieldset/WUTR:
description: Wakeup auto-reload value bits description: Wakeup auto-reload value bits
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/ALRFR:
bit_size: 1
variants:
- name: Match
description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
value: 1
enum/ALRFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/ALRMR_MSK: enum/ALRMR_MSK:
bit_size: 1 bit_size: 1
variants: variants:
@ -661,7 +637,7 @@ enum/ALRMR_WDSEL:
- name: WeekDay - name: WeekDay
description: "DU[3:0] represents the week day. DT[1:0] is don’t care" description: "DU[3:0] represents the week day. DT[1:0] is don’t care"
value: 1 value: 1
enum/ALRWFR: enum/ALRWF:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed
@ -727,7 +703,7 @@ enum/INIT:
- name: InitMode - name: InitMode
description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."
value: 1 value: 1
enum/INITFR: enum/INITF:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotAllowed - name: NotAllowed
@ -736,7 +712,7 @@ enum/INITFR:
- name: Allowed - name: Allowed
description: Calendar registers update is allowed description: Calendar registers update is allowed
value: 1 value: 1
enum/INITSR: enum/INITS:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotInitalized - name: NotInitalized
@ -769,7 +745,7 @@ enum/POL:
- name: Low - name: Low
description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
value: 1 value: 1
enum/RECALPFR: enum/RECALPF:
bit_size: 1 bit_size: 1
variants: variants:
- name: Pending - name: Pending
@ -784,21 +760,6 @@ enum/REFCKON:
- name: Enabled - name: Enabled
description: RTC_REFIN detection enabled description: RTC_REFIN detection enabled
value: 1 value: 1
enum/RSFR:
bit_size: 1
variants:
- name: NotSynced
description: Calendar shadow registers not yet synchronized
value: 0
- name: Synced
description: Calendar shadow registers synchronized
value: 1
enum/RSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TAMPFLT: enum/TAMPFLT:
bit_size: 2 bit_size: 2
variants: variants:
@ -814,12 +775,6 @@ enum/TAMPFLT:
- name: Samples8 - name: Samples8
description: Tamper event is activated after 8 consecutive samples at the active level description: Tamper event is activated after 8 consecutive samples at the active level
value: 3 value: 3
enum/TAMPFR:
bit_size: 1
variants:
- name: Tampered
description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
value: 1
enum/TAMPFREQ: enum/TAMPFREQ:
bit_size: 3 bit_size: 3
variants: variants:
@ -847,12 +802,6 @@ enum/TAMPFREQ:
- name: Div256 - name: Div256
description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
value: 7 value: 7
enum/TAMPFW:
bit_size: 1
variants:
- name: Clear
description: Flag cleared by software writing 0
value: 0
enum/TAMPPRCH: enum/TAMPPRCH:
bit_size: 2 bit_size: 2
variants: variants:
@ -895,30 +844,6 @@ enum/TSEDGE:
- name: FallingEdge - name: FallingEdge
description: RTC_TS input falling edge generates a time-stamp event description: RTC_TS input falling edge generates a time-stamp event
value: 1 value: 1
enum/TSFR:
bit_size: 1
variants:
- name: TimestampEvent
description: This flag is set by hardware when a time-stamp event occurs
value: 1
enum/TSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TSOVFR:
bit_size: 1
variants:
- name: Overflow
description: This flag is set by hardware when a timestamp event occurs while TSF is already set
value: 1
enum/TSOVFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUCKSEL: enum/WUCKSEL:
bit_size: 3 bit_size: 3
variants: variants:
@ -940,19 +865,7 @@ enum/WUCKSEL:
- name: ClockSpareWithOffset - name: ClockSpareWithOffset
description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
value: 6 value: 6
enum/WUTFR: enum/WUTWF:
bit_size: 1
variants:
- name: Zero
description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
value: 1
enum/WUTFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUTWFR:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed

107
data/registers/rtc_v2l0.yaml
View File

@ -323,12 +323,12 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRWFR enum: ALRWF
- name: WUTWF - name: WUTWF
description: Wakeup timer write flag description: Wakeup timer write flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WUTWFR enum: WUTWF
- name: SHPF - name: SHPF
description: Shift operation pending description: Shift operation pending
bit_offset: 3 bit_offset: 3
@ -337,18 +337,16 @@ fieldset/ISR:
description: Initialization status flag description: Initialization status flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: INITSR enum: INITS
- name: RSF - name: RSF
description: Registers synchronization flag description: Registers synchronization flag
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: RSFR
enum_write: RSFW
- name: INITF - name: INITF
description: Initialization flag description: Initialization flag
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: INITFR enum: INITF
- name: INIT - name: INIT
description: Initialization mode description: Initialization mode
bit_offset: 7 bit_offset: 7
@ -361,26 +359,18 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRFR
enum_write: ALRFW
- name: WUTF - name: WUTF
description: Wakeup timer flag description: Wakeup timer flag
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
enum_read: WUTFR
enum_write: WUTFW
- name: TSF - name: TSF
description: Timestamp flag description: Timestamp flag
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
enum_read: TSFR
enum_write: TSFW
- name: TSOVF - name: TSOVF
description: Timestamp overflow flag description: Timestamp overflow flag
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
enum_read: TSOVFR
enum_write: TSOVFW
- name: TAMPF - name: TAMPF
description: Tamper detection flag description: Tamper detection flag
bit_offset: 13 bit_offset: 13
@ -388,13 +378,11 @@ fieldset/ISR:
array: array:
len: 3 len: 3
stride: 1 stride: 1
enum_read: TAMPFR
enum_write: TAMPFW
- name: RECALPF - name: RECALPF
description: Recalibration pending flag description: Recalibration pending flag
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum_read: RECALPFR enum: RECALPF
fieldset/OR: fieldset/OR:
description: Option register description: Option register
fields: fields:
@ -614,18 +602,6 @@ fieldset/WUTR:
description: Wakeup auto-reload value bits description: Wakeup auto-reload value bits
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/ALRFR:
bit_size: 1
variants:
- name: Match
description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
value: 1
enum/ALRFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/ALRMR_MSK: enum/ALRMR_MSK:
bit_size: 1 bit_size: 1
variants: variants:
@ -653,7 +629,7 @@ enum/ALRMR_WDSEL:
- name: WeekDay - name: WeekDay
description: "DU[3:0] represents the week day. DT[1:0] is don’t care" description: "DU[3:0] represents the week day. DT[1:0] is don’t care"
value: 1 value: 1
enum/ALRWFR: enum/ALRWF:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed
@ -719,7 +695,7 @@ enum/INIT:
- name: InitMode - name: InitMode
description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."
value: 1 value: 1
enum/INITFR: enum/INITF:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotAllowed - name: NotAllowed
@ -728,7 +704,7 @@ enum/INITFR:
- name: Allowed - name: Allowed
description: Calendar registers update is allowed description: Calendar registers update is allowed
value: 1 value: 1
enum/INITSR: enum/INITS:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotInitalized - name: NotInitalized
@ -761,7 +737,7 @@ enum/POL:
- name: Low - name: Low
description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
value: 1 value: 1
enum/RECALPFR: enum/RECALPF:
bit_size: 1 bit_size: 1
variants: variants:
- name: Pending - name: Pending
@ -776,21 +752,6 @@ enum/REFCKON:
- name: Enabled - name: Enabled
description: RTC_REFIN detection enabled description: RTC_REFIN detection enabled
value: 1 value: 1
enum/RSFR:
bit_size: 1
variants:
- name: NotSynced
description: Calendar shadow registers not yet synchronized
value: 0
- name: Synced
description: Calendar shadow registers synchronized
value: 1
enum/RSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TAMPFLT: enum/TAMPFLT:
bit_size: 2 bit_size: 2
variants: variants:
@ -806,12 +767,6 @@ enum/TAMPFLT:
- name: Samples8 - name: Samples8
description: Tamper event is activated after 8 consecutive samples at the active level description: Tamper event is activated after 8 consecutive samples at the active level
value: 3 value: 3
enum/TAMPFR:
bit_size: 1
variants:
- name: Tampered
description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
value: 1
enum/TAMPFREQ: enum/TAMPFREQ:
bit_size: 3 bit_size: 3
variants: variants:
@ -839,12 +794,6 @@ enum/TAMPFREQ:
- name: Div256 - name: Div256
description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
value: 7 value: 7
enum/TAMPFW:
bit_size: 1
variants:
- name: Clear
description: Flag cleared by software writing 0
value: 0
enum/TAMPPRCH: enum/TAMPPRCH:
bit_size: 2 bit_size: 2
variants: variants:
@ -887,30 +836,6 @@ enum/TSEDGE:
- name: FallingEdge - name: FallingEdge
description: RTC_TS input falling edge generates a time-stamp event description: RTC_TS input falling edge generates a time-stamp event
value: 1 value: 1
enum/TSFR:
bit_size: 1
variants:
- name: TimestampEvent
description: This flag is set by hardware when a time-stamp event occurs
value: 1
enum/TSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TSOVFR:
bit_size: 1
variants:
- name: Overflow
description: This flag is set by hardware when a timestamp event occurs while TSF is already set
value: 1
enum/TSOVFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUCKSEL: enum/WUCKSEL:
bit_size: 3 bit_size: 3
variants: variants:
@ -932,19 +857,7 @@ enum/WUCKSEL:
- name: ClockSpareWithOffset - name: ClockSpareWithOffset
description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
value: 6 value: 6
enum/WUTFR: enum/WUTWF:
bit_size: 1
variants:
- name: Zero
description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
value: 1
enum/WUTFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUTWFR:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed

107
data/registers/rtc_v2l1.yaml
View File

@ -338,12 +338,12 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRWFR enum: ALRWF
- name: WUTWF - name: WUTWF
description: Wakeup timer write flag description: Wakeup timer write flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WUTWFR enum: WUTWF
- name: SHPF - name: SHPF
description: Shift operation pending description: Shift operation pending
bit_offset: 3 bit_offset: 3
@ -352,18 +352,16 @@ fieldset/ISR:
description: Initialization status flag description: Initialization status flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: INITSR enum: INITS
- name: RSF - name: RSF
description: Registers synchronization flag description: Registers synchronization flag
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: RSFR
enum_write: RSFW
- name: INITF - name: INITF
description: Initialization flag description: Initialization flag
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: INITFR enum: INITF
- name: INIT - name: INIT
description: Initialization mode description: Initialization mode
bit_offset: 7 bit_offset: 7
@ -376,26 +374,18 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRFR
enum_write: ALRFW
- name: WUTF - name: WUTF
description: Wakeup timer flag description: Wakeup timer flag
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
enum_read: WUTFR
enum_write: WUTFW
- name: TSF - name: TSF
description: Timestamp flag description: Timestamp flag
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
enum_read: TSFR
enum_write: TSFW
- name: TSOVF - name: TSOVF
description: Timestamp overflow flag description: Timestamp overflow flag
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
enum_read: TSOVFR
enum_write: TSOVFW
- name: TAMPF - name: TAMPF
description: Tamper detection flag description: Tamper detection flag
bit_offset: 13 bit_offset: 13
@ -403,13 +393,11 @@ fieldset/ISR:
array: array:
len: 3 len: 3
stride: 1 stride: 1
enum_read: TAMPFR
enum_write: TAMPFW
- name: RECALPF - name: RECALPF
description: Recalibration pending flag description: Recalibration pending flag
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum_read: RECALPFR enum: RECALPF
fieldset/PRER: fieldset/PRER:
description: Prescaler register description: Prescaler register
fields: fields:
@ -601,18 +589,6 @@ fieldset/WUTR:
description: Wakeup auto-reload value bits description: Wakeup auto-reload value bits
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/ALRFR:
bit_size: 1
variants:
- name: Match
description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
value: 1
enum/ALRFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/ALRMR_MSK: enum/ALRMR_MSK:
bit_size: 1 bit_size: 1
variants: variants:
@ -640,7 +616,7 @@ enum/ALRMR_WDSEL:
- name: WeekDay - name: WeekDay
description: "DU[3:0] represents the week day. DT[1:0] is don’t care" description: "DU[3:0] represents the week day. DT[1:0] is don’t care"
value: 1 value: 1
enum/ALRWFR: enum/ALRWF:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed
@ -706,7 +682,7 @@ enum/INIT:
- name: InitMode - name: InitMode
description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."
value: 1 value: 1
enum/INITFR: enum/INITF:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotAllowed - name: NotAllowed
@ -715,7 +691,7 @@ enum/INITFR:
- name: Allowed - name: Allowed
description: Calendar registers update is allowed description: Calendar registers update is allowed
value: 1 value: 1
enum/INITSR: enum/INITS:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotInitalized - name: NotInitalized
@ -748,7 +724,7 @@ enum/POL:
- name: Low - name: Low
description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
value: 1 value: 1
enum/RECALPFR: enum/RECALPF:
bit_size: 1 bit_size: 1
variants: variants:
- name: Pending - name: Pending
@ -763,21 +739,6 @@ enum/REFCKON:
- name: Enabled - name: Enabled
description: RTC_REFIN detection enabled description: RTC_REFIN detection enabled
value: 1 value: 1
enum/RSFR:
bit_size: 1
variants:
- name: NotSynced
description: Calendar shadow registers not yet synchronized
value: 0
- name: Synced
description: Calendar shadow registers synchronized
value: 1
enum/RSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TAMPFLT: enum/TAMPFLT:
bit_size: 2 bit_size: 2
variants: variants:
@ -793,12 +754,6 @@ enum/TAMPFLT:
- name: Samples8 - name: Samples8
description: Tamper event is activated after 8 consecutive samples at the active level description: Tamper event is activated after 8 consecutive samples at the active level
value: 3 value: 3
enum/TAMPFR:
bit_size: 1
variants:
- name: Tampered
description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
value: 1
enum/TAMPFREQ: enum/TAMPFREQ:
bit_size: 3 bit_size: 3
variants: variants:
@ -826,12 +781,6 @@ enum/TAMPFREQ:
- name: Div256 - name: Div256
description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
value: 7 value: 7
enum/TAMPFW:
bit_size: 1
variants:
- name: Clear
description: Flag cleared by software writing 0
value: 0
enum/TAMPPRCH: enum/TAMPPRCH:
bit_size: 2 bit_size: 2
variants: variants:
@ -874,30 +823,6 @@ enum/TSEDGE:
- name: FallingEdge - name: FallingEdge
description: RTC_TS input falling edge generates a time-stamp event description: RTC_TS input falling edge generates a time-stamp event
value: 1 value: 1
enum/TSFR:
bit_size: 1
variants:
- name: TimestampEvent
description: This flag is set by hardware when a time-stamp event occurs
value: 1
enum/TSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TSOVFR:
bit_size: 1
variants:
- name: Overflow
description: This flag is set by hardware when a timestamp event occurs while TSF is already set
value: 1
enum/TSOVFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUCKSEL: enum/WUCKSEL:
bit_size: 3 bit_size: 3
variants: variants:
@ -919,19 +844,7 @@ enum/WUCKSEL:
- name: ClockSpareWithOffset - name: ClockSpareWithOffset
description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
value: 6 value: 6
enum/WUTFR: enum/WUTWF:
bit_size: 1
variants:
- name: Zero
description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
value: 1
enum/WUTFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUTWFR:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed

107
data/registers/rtc_v2l4.yaml
View File

@ -327,12 +327,12 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRWFR enum: ALRWF
- name: WUTWF - name: WUTWF
description: Wakeup timer write flag description: Wakeup timer write flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WUTWFR enum: WUTWF
- name: SHPF - name: SHPF
description: Shift operation pending description: Shift operation pending
bit_offset: 3 bit_offset: 3
@ -341,18 +341,16 @@ fieldset/ISR:
description: Initialization status flag description: Initialization status flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: INITSR enum: INITS
- name: RSF - name: RSF
description: Registers synchronization flag description: Registers synchronization flag
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: RSFR
enum_write: RSFW
- name: INITF - name: INITF
description: Initialization flag description: Initialization flag
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: INITFR enum: INITF
- name: INIT - name: INIT
description: Initialization mode description: Initialization mode
bit_offset: 7 bit_offset: 7
@ -365,26 +363,18 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRFR
enum_write: ALRFW
- name: WUTF - name: WUTF
description: Wakeup timer flag description: Wakeup timer flag
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
enum_read: WUTFR
enum_write: WUTFW
- name: TSF - name: TSF
description: Timestamp flag description: Timestamp flag
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
enum_read: TSFR
enum_write: TSFW
- name: TSOVF - name: TSOVF
description: Timestamp overflow flag description: Timestamp overflow flag
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
enum_read: TSOVFR
enum_write: TSOVFW
- name: TAMPF - name: TAMPF
description: Tamper detection flag description: Tamper detection flag
bit_offset: 13 bit_offset: 13
@ -392,13 +382,11 @@ fieldset/ISR:
array: array:
len: 3 len: 3
stride: 1 stride: 1
enum_read: TAMPFR
enum_write: TAMPFW
- name: RECALPF - name: RECALPF
description: Recalibration pending flag description: Recalibration pending flag
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum_read: RECALPFR enum: RECALPF
fieldset/OR: fieldset/OR:
description: Option register description: Option register
fields: fields:
@ -618,18 +606,6 @@ fieldset/WUTR:
description: Wakeup auto-reload value bits description: Wakeup auto-reload value bits
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/ALRFR:
bit_size: 1
variants:
- name: Match
description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
value: 1
enum/ALRFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/ALRMR_MSK: enum/ALRMR_MSK:
bit_size: 1 bit_size: 1
variants: variants:
@ -657,7 +633,7 @@ enum/ALRMR_WDSEL:
- name: WeekDay - name: WeekDay
description: "DU[3:0] represents the week day. DT[1:0] is don’t care" description: "DU[3:0] represents the week day. DT[1:0] is don’t care"
value: 1 value: 1
enum/ALRWFR: enum/ALRWF:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed
@ -723,7 +699,7 @@ enum/INIT:
- name: InitMode - name: InitMode
description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."
value: 1 value: 1
enum/INITFR: enum/INITF:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotAllowed - name: NotAllowed
@ -732,7 +708,7 @@ enum/INITFR:
- name: Allowed - name: Allowed
description: Calendar registers update is allowed description: Calendar registers update is allowed
value: 1 value: 1
enum/INITSR: enum/INITS:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotInitalized - name: NotInitalized
@ -765,7 +741,7 @@ enum/POL:
- name: Low - name: Low
description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
value: 1 value: 1
enum/RECALPFR: enum/RECALPF:
bit_size: 1 bit_size: 1
variants: variants:
- name: Pending - name: Pending
@ -780,21 +756,6 @@ enum/REFCKON:
- name: Enabled - name: Enabled
description: RTC_REFIN detection enabled description: RTC_REFIN detection enabled
value: 1 value: 1
enum/RSFR:
bit_size: 1
variants:
- name: NotSynced
description: Calendar shadow registers not yet synchronized
value: 0
- name: Synced
description: Calendar shadow registers synchronized
value: 1
enum/RSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TAMPFLT: enum/TAMPFLT:
bit_size: 2 bit_size: 2
variants: variants:
@ -810,12 +771,6 @@ enum/TAMPFLT:
- name: Samples8 - name: Samples8
description: Tamper event is activated after 8 consecutive samples at the active level description: Tamper event is activated after 8 consecutive samples at the active level
value: 3 value: 3
enum/TAMPFR:
bit_size: 1
variants:
- name: Tampered
description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
value: 1
enum/TAMPFREQ: enum/TAMPFREQ:
bit_size: 3 bit_size: 3
variants: variants:
@ -843,12 +798,6 @@ enum/TAMPFREQ:
- name: Div256 - name: Div256
description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
value: 7 value: 7
enum/TAMPFW:
bit_size: 1
variants:
- name: Clear
description: Flag cleared by software writing 0
value: 0
enum/TAMPPRCH: enum/TAMPPRCH:
bit_size: 2 bit_size: 2
variants: variants:
@ -891,30 +840,6 @@ enum/TSEDGE:
- name: FallingEdge - name: FallingEdge
description: RTC_TS input falling edge generates a time-stamp event description: RTC_TS input falling edge generates a time-stamp event
value: 1 value: 1
enum/TSFR:
bit_size: 1
variants:
- name: TimestampEvent
description: This flag is set by hardware when a time-stamp event occurs
value: 1
enum/TSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TSOVFR:
bit_size: 1
variants:
- name: Overflow
description: This flag is set by hardware when a timestamp event occurs while TSF is already set
value: 1
enum/TSOVFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUCKSEL: enum/WUCKSEL:
bit_size: 3 bit_size: 3
variants: variants:
@ -936,19 +861,7 @@ enum/WUCKSEL:
- name: ClockSpareWithOffset - name: ClockSpareWithOffset
description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
value: 6 value: 6
enum/WUTFR: enum/WUTWF:
bit_size: 1
variants:
- name: Zero
description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
value: 1
enum/WUTFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUTWFR:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed

107
data/registers/rtc_v2wb.yaml
View File

@ -327,12 +327,12 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRWFR enum: ALRWF
- name: WUTWF - name: WUTWF
description: Wakeup timer write flag description: Wakeup timer write flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WUTWFR enum: WUTWF
- name: SHPF - name: SHPF
description: Shift operation pending description: Shift operation pending
bit_offset: 3 bit_offset: 3
@ -341,18 +341,16 @@ fieldset/ISR:
description: Initialization status flag description: Initialization status flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: INITSR enum: INITS
- name: RSF - name: RSF
description: Registers synchronization flag description: Registers synchronization flag
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: RSFR
enum_write: RSFW
- name: INITF - name: INITF
description: Initialization flag description: Initialization flag
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: INITFR enum: INITF
- name: INIT - name: INIT
description: Initialization mode description: Initialization mode
bit_offset: 7 bit_offset: 7
@ -365,26 +363,18 @@ fieldset/ISR:
array: array:
len: 2 len: 2
stride: 1 stride: 1
enum_read: ALRFR
enum_write: ALRFW
- name: WUTF - name: WUTF
description: Wakeup timer flag description: Wakeup timer flag
bit_offset: 10 bit_offset: 10
bit_size: 1 bit_size: 1
enum_read: WUTFR
enum_write: WUTFW
- name: TSF - name: TSF
description: Timestamp flag description: Timestamp flag
bit_offset: 11 bit_offset: 11
bit_size: 1 bit_size: 1
enum_read: TSFR
enum_write: TSFW
- name: TSOVF - name: TSOVF
description: Timestamp overflow flag description: Timestamp overflow flag
bit_offset: 12 bit_offset: 12
bit_size: 1 bit_size: 1
enum_read: TSOVFR
enum_write: TSOVFW
- name: TAMPF - name: TAMPF
description: Tamper detection flag description: Tamper detection flag
bit_offset: 13 bit_offset: 13
@ -392,13 +382,11 @@ fieldset/ISR:
array: array:
len: 3 len: 3
stride: 1 stride: 1
enum_read: TAMPFR
enum_write: TAMPFW
- name: RECALPF - name: RECALPF
description: Recalibration pending flag description: Recalibration pending flag
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum_read: RECALPFR enum: RECALPF
- name: ITSF - name: ITSF
description: Internal time-stamp flag description: Internal time-stamp flag
bit_offset: 17 bit_offset: 17
@ -622,18 +610,6 @@ fieldset/WUTR:
description: Wakeup auto-reload value bits description: Wakeup auto-reload value bits
bit_offset: 0 bit_offset: 0
bit_size: 16 bit_size: 16
enum/ALRFR:
bit_size: 1
variants:
- name: Match
description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
value: 1
enum/ALRFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/ALRMR_MSK: enum/ALRMR_MSK:
bit_size: 1 bit_size: 1
variants: variants:
@ -661,7 +637,7 @@ enum/ALRMR_WDSEL:
- name: WeekDay - name: WeekDay
description: "DU[3:0] represents the week day. DT[1:0] is don’t care" description: "DU[3:0] represents the week day. DT[1:0] is don’t care"
value: 1 value: 1
enum/ALRWFR: enum/ALRWF:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed
@ -727,7 +703,7 @@ enum/INIT:
- name: InitMode - name: InitMode
description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."
value: 1 value: 1
enum/INITFR: enum/INITF:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotAllowed - name: NotAllowed
@ -736,7 +712,7 @@ enum/INITFR:
- name: Allowed - name: Allowed
description: Calendar registers update is allowed description: Calendar registers update is allowed
value: 1 value: 1
enum/INITSR: enum/INITS:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotInitalized - name: NotInitalized
@ -769,7 +745,7 @@ enum/POL:
- name: Low - name: Low
description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
value: 1 value: 1
enum/RECALPFR: enum/RECALPF:
bit_size: 1 bit_size: 1
variants: variants:
- name: Pending - name: Pending
@ -784,21 +760,6 @@ enum/REFCKON:
- name: Enabled - name: Enabled
description: RTC_REFIN detection enabled description: RTC_REFIN detection enabled
value: 1 value: 1
enum/RSFR:
bit_size: 1
variants:
- name: NotSynced
description: Calendar shadow registers not yet synchronized
value: 0
- name: Synced
description: Calendar shadow registers synchronized
value: 1
enum/RSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TAMPFLT: enum/TAMPFLT:
bit_size: 2 bit_size: 2
variants: variants:
@ -814,12 +775,6 @@ enum/TAMPFLT:
- name: Samples8 - name: Samples8
description: Tamper event is activated after 8 consecutive samples at the active level description: Tamper event is activated after 8 consecutive samples at the active level
value: 3 value: 3
enum/TAMPFR:
bit_size: 1
variants:
- name: Tampered
description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
value: 1
enum/TAMPFREQ: enum/TAMPFREQ:
bit_size: 3 bit_size: 3
variants: variants:
@ -847,12 +802,6 @@ enum/TAMPFREQ:
- name: Div256 - name: Div256
description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
value: 7 value: 7
enum/TAMPFW:
bit_size: 1
variants:
- name: Clear
description: Flag cleared by software writing 0
value: 0
enum/TAMPPRCH: enum/TAMPPRCH:
bit_size: 2 bit_size: 2
variants: variants:
@ -895,30 +844,6 @@ enum/TSEDGE:
- name: FallingEdge - name: FallingEdge
description: RTC_TS input falling edge generates a time-stamp event description: RTC_TS input falling edge generates a time-stamp event
value: 1 value: 1
enum/TSFR:
bit_size: 1
variants:
- name: TimestampEvent
description: This flag is set by hardware when a time-stamp event occurs
value: 1
enum/TSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/TSOVFR:
bit_size: 1
variants:
- name: Overflow
description: This flag is set by hardware when a timestamp event occurs while TSF is already set
value: 1
enum/TSOVFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUCKSEL: enum/WUCKSEL:
bit_size: 3 bit_size: 3
variants: variants:
@ -940,19 +865,7 @@ enum/WUCKSEL:
- name: ClockSpareWithOffset - name: ClockSpareWithOffset
description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
value: 6 value: 6
enum/WUTFR: enum/WUTWF:
bit_size: 1
variants:
- name: Zero
description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
value: 1
enum/WUTFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/WUTWFR:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed

51
data/registers/rtc_v3.yaml
View File

@ -367,7 +367,7 @@ fieldset/ICSR:
description: Wakeup timer write flag description: Wakeup timer write flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WUTWFR enum: WUTWF
- name: SHPF - name: SHPF
description: Shift operation pending description: Shift operation pending
bit_offset: 3 bit_offset: 3
@ -376,18 +376,16 @@ fieldset/ICSR:
description: Initialization status flag description: Initialization status flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: INITSR enum: INITS
- name: RSF - name: RSF
description: Registers synchronization flag description: Registers synchronization flag
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: RSFR
enum_write: RSFW
- name: INITF - name: INITF
description: Initialization flag description: Initialization flag
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: INITFR enum: INITF
- name: INIT - name: INIT
description: Initialization mode description: Initialization mode
bit_offset: 7 bit_offset: 7
@ -407,7 +405,7 @@ fieldset/ICSR:
description: Recalibration pending Flag description: Recalibration pending Flag
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum_read: RECALPFR enum: RECALPF
fieldset/MISR: fieldset/MISR:
description: Masked interrupt status register description: Masked interrupt status register
fields: fields:
@ -810,7 +808,7 @@ enum/INIT:
- name: InitMode - name: InitMode
description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."
value: 1 value: 1
enum/INITFR: enum/INITF:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotAllowed - name: NotAllowed
@ -819,7 +817,7 @@ enum/INITFR:
- name: Allowed - name: Allowed
description: Calendar registers update is allowed description: Calendar registers update is allowed
value: 1 value: 1
enum/INITSR: enum/INITS:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotInitalized - name: NotInitalized
@ -885,7 +883,7 @@ enum/POL:
- name: Low - name: Low
description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
value: 1 value: 1
enum/RECALPFR: enum/RECALPF:
bit_size: 1 bit_size: 1
variants: variants:
- name: Pending - name: Pending
@ -900,45 +898,12 @@ enum/REFCKON:
- name: Enabled - name: Enabled
description: RTC_REFIN detection enabled description: RTC_REFIN detection enabled
value: 1 value: 1
enum/RSFR:
bit_size: 1
variants:
- name: NotSynced
description: Calendar shadow registers not yet synchronized
value: 0
- name: Synced
description: Calendar shadow registers synchronized
value: 1
enum/RSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/SHPFR:
bit_size: 1
variants:
- name: NoShiftPending
description: No shift operation is pending
value: 0
- name: ShiftPending
description: A shift operation is pending
value: 1
enum/SSRUF: enum/SSRUF:
bit_size: 1 bit_size: 1
variants: variants:
- name: Underflow - name: Underflow
description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1
value: 1 value: 1
enum/SSRUIE:
bit_size: 1
variants:
- name: Disabled
description: SSR underflow interrupt disabled
value: 0
- name: Enabled
description: SSR underflow interrupt enabled
value: 1
enum/SSRUMF: enum/SSRUMF:
bit_size: 1 bit_size: 1
variants: variants:
@ -1029,7 +994,7 @@ enum/WUTMF:
- name: Zero - name: Zero
description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
value: 1 value: 1
enum/WUTWFR: enum/WUTWF:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed

51
data/registers/rtc_v3u5.yaml
View File

@ -387,7 +387,7 @@ fieldset/ICSR:
description: Wakeup timer write flag description: Wakeup timer write flag
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WUTWFR enum: WUTWF
- name: SHPF - name: SHPF
description: Shift operation pending description: Shift operation pending
bit_offset: 3 bit_offset: 3
@ -396,18 +396,16 @@ fieldset/ICSR:
description: Initialization status flag description: Initialization status flag
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: INITSR enum: INITS
- name: RSF - name: RSF
description: Registers synchronization flag description: Registers synchronization flag
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: RSFR
enum_write: RSFW
- name: INITF - name: INITF
description: Initialization flag description: Initialization flag
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: INITFR enum: INITF
- name: INIT - name: INIT
description: Initialization mode description: Initialization mode
bit_offset: 7 bit_offset: 7
@ -427,7 +425,7 @@ fieldset/ICSR:
description: Recalibration pending Flag description: Recalibration pending Flag
bit_offset: 16 bit_offset: 16
bit_size: 1 bit_size: 1
enum_read: RECALPFR enum: RECALPF
fieldset/MISR: fieldset/MISR:
description: Masked interrupt status register description: Masked interrupt status register
fields: fields:
@ -923,7 +921,7 @@ enum/INIT:
- name: InitMode - name: InitMode
description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."
value: 1 value: 1
enum/INITFR: enum/INITF:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotAllowed - name: NotAllowed
@ -932,7 +930,7 @@ enum/INITFR:
- name: Allowed - name: Allowed
description: Calendar registers update is allowed description: Calendar registers update is allowed
value: 1 value: 1
enum/INITSR: enum/INITS:
bit_size: 1 bit_size: 1
variants: variants:
- name: NotInitalized - name: NotInitalized
@ -998,7 +996,7 @@ enum/POL:
- name: Low - name: Low
description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
value: 1 value: 1
enum/RECALPFR: enum/RECALPF:
bit_size: 1 bit_size: 1
variants: variants:
- name: Pending - name: Pending
@ -1013,45 +1011,12 @@ enum/REFCKON:
- name: Enabled - name: Enabled
description: RTC_REFIN detection enabled description: RTC_REFIN detection enabled
value: 1 value: 1
enum/RSFR:
bit_size: 1
variants:
- name: NotSynced
description: Calendar shadow registers not yet synchronized
value: 0
- name: Synced
description: Calendar shadow registers synchronized
value: 1
enum/RSFW:
bit_size: 1
variants:
- name: Clear
description: This flag is cleared by software by writing 0
value: 0
enum/SHPFR:
bit_size: 1
variants:
- name: NoShiftPending
description: No shift operation is pending
value: 0
- name: ShiftPending
description: A shift operation is pending
value: 1
enum/SSRUF: enum/SSRUF:
bit_size: 1 bit_size: 1
variants: variants:
- name: Underflow - name: Underflow
description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1
value: 1 value: 1
enum/SSRUIE:
bit_size: 1
variants:
- name: Disabled
description: SSR underflow interrupt disabled
value: 0
- name: Enabled
description: SSR underflow interrupt enabled
value: 1
enum/SSRUMF: enum/SSRUMF:
bit_size: 1 bit_size: 1
variants: variants:
@ -1142,7 +1107,7 @@ enum/WUTMF:
- name: Zero - name: Zero
description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 description: This flag is set by hardware when the wakeup auto-reload counter reaches 0
value: 1 value: 1
enum/WUTWFR: enum/WUTWF:
bit_size: 1 bit_size: 1
variants: variants:
- name: UpdateNotAllowed - name: UpdateNotAllowed

32
data/registers/sai_v1.yaml
View File

@ -264,43 +264,43 @@ fieldset/SR:
description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register."
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum_read: OVRUDRR enum: OVRUDR
- name: MUTEDET - name: MUTEDET
description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register.
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
enum_read: MUTEDETR enum: MUTEDET
- name: WCKCFG - name: WCKCFG
description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register."
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WCKCFGR enum: WCKCFG
- name: FREQ - name: FREQ
description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register."
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
enum_read: FREQR enum: FREQ
- name: CNRDY - name: CNRDY
description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register.
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: CNRDYR enum: CNRDY
- name: AFSDET - name: AFSDET
description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register.
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: AFSDETR enum: AFSDET
- name: LFSDET - name: LFSDET
description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: LFSDETR enum: LFSDET
- name: FLVL - name: FLVL
description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:"
bit_offset: 16 bit_offset: 16
bit_size: 3 bit_size: 3
enum_read: FLVLR enum: FLVL
enum/AFSDETR: enum/AFSDET:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoError - name: NoError
@ -318,7 +318,7 @@ enum/CKSTR:
- name: RisingEdge - name: RisingEdge
description: Data strobing edge is rising edge of SCK description: Data strobing edge is rising edge of SCK
value: 1 value: 1
enum/CNRDYR: enum/CNRDY:
bit_size: 1 bit_size: 1
variants: variants:
- name: Ready - name: Ready
@ -378,7 +378,7 @@ enum/FFLUSH:
- name: Flush - name: Flush
description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared
value: 1 value: 1
enum/FLVLR: enum/FLVL:
bit_size: 3 bit_size: 3
variants: variants:
- name: Empty - name: Empty
@ -399,7 +399,7 @@ enum/FLVLR:
- name: Full - name: Full
description: FIFO full description: FIFO full
value: 5 value: 5
enum/FREQR: enum/FREQ:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoRequest - name: NoRequest
@ -444,7 +444,7 @@ enum/FTH:
- name: Full - name: Full
description: FIFO full description: FIFO full
value: 4 value: 4
enum/LFSDETR: enum/LFSDET:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoError - name: NoError
@ -486,7 +486,7 @@ enum/MONO:
- name: Mono - name: Mono
description: Mono mode description: Mono mode
value: 1 value: 1
enum/MUTEDETR: enum/MUTEDET:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoMute - name: NoMute
@ -522,7 +522,7 @@ enum/OUTDRIV:
- name: Immediately - name: Immediately
description: Audio block output driven immediately after the setting of this bit description: Audio block output driven immediately after the setting of this bit
value: 1 value: 1
enum/OVRUDRR: enum/OVRUDR:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoError - name: NoError
@ -576,7 +576,7 @@ enum/SYNCEN:
- name: External - name: External
description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode
value: 2 value: 2
enum/WCKCFGR: enum/WCKCFG:
bit_size: 1 bit_size: 1
variants: variants:
- name: Correct - name: Correct

32
data/registers/sai_v2.yaml
View File

@ -279,43 +279,43 @@ fieldset/SR:
description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register."
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum_read: OVRUDRR enum: OVRUDR
- name: MUTEDET - name: MUTEDET
description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register.
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
enum_read: MUTEDETR enum: MUTEDET
- name: WCKCFG - name: WCKCFG
description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register."
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WCKCFGR enum: WCKCFG
- name: FREQ - name: FREQ
description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register."
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
enum_read: FREQR enum: FREQ
- name: CNRDY - name: CNRDY
description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register.
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: CNRDYR enum: CNRDY
- name: AFSDET - name: AFSDET
description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register.
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: AFSDETR enum: AFSDET
- name: LFSDET - name: LFSDET
description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: LFSDETR enum: LFSDET
- name: FLVL - name: FLVL
description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:"
bit_offset: 16 bit_offset: 16
bit_size: 3 bit_size: 3
enum_read: FLVLR enum: FLVL
enum/AFSDETR: enum/AFSDET:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoError - name: NoError
@ -333,7 +333,7 @@ enum/CKSTR:
- name: RisingEdge - name: RisingEdge
description: Data strobing edge is rising edge of SCK description: Data strobing edge is rising edge of SCK
value: 1 value: 1
enum/CNRDYR: enum/CNRDY:
bit_size: 1 bit_size: 1
variants: variants:
- name: Ready - name: Ready
@ -393,7 +393,7 @@ enum/FFLUSH:
- name: Flush - name: Flush
description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared
value: 1 value: 1
enum/FLVLR: enum/FLVL:
bit_size: 3 bit_size: 3
variants: variants:
- name: Empty - name: Empty
@ -414,7 +414,7 @@ enum/FLVLR:
- name: Full - name: Full
description: FIFO full description: FIFO full
value: 5 value: 5
enum/FREQR: enum/FREQ:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoRequest - name: NoRequest
@ -459,7 +459,7 @@ enum/FTH:
- name: Full - name: Full
description: FIFO full description: FIFO full
value: 4 value: 4
enum/LFSDETR: enum/LFSDET:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoError - name: NoError
@ -501,7 +501,7 @@ enum/MONO:
- name: Mono - name: Mono
description: Mono mode description: Mono mode
value: 1 value: 1
enum/MUTEDETR: enum/MUTEDET:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoMute - name: NoMute
@ -537,7 +537,7 @@ enum/OUTDRIV:
- name: Immediately - name: Immediately
description: Audio block output driven immediately after the setting of this bit description: Audio block output driven immediately after the setting of this bit
value: 1 value: 1
enum/OVRUDRR: enum/OVRUDR:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoError - name: NoError
@ -591,7 +591,7 @@ enum/SYNCEN:
- name: External - name: External
description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode
value: 2 value: 2
enum/WCKCFGR: enum/WCKCFG:
bit_size: 1 bit_size: 1
variants: variants:
- name: Correct - name: Correct

42
data/registers/sai_v3.yaml
View File

@ -161,7 +161,6 @@ fieldset/CR2:
description: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. description: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled.
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
enum_write: FFLUSH
- name: TRIS - name: TRIS
description: "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details." description: "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details."
bit_offset: 4 bit_offset: 4
@ -353,43 +352,43 @@ fieldset/SR:
description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register."
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum_read: OVRUDRR enum: OVRUDR
- name: MUTEDET - name: MUTEDET
description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register.
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
enum_read: MUTEDETR enum: MUTEDET
- name: WCKCFG - name: WCKCFG
description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register."
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WCKCFGR enum: WCKCFG
- name: FREQ - name: FREQ
description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register."
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
enum_read: FREQR enum: FREQ
- name: CNRDY - name: CNRDY
description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register.
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: CNRDYR enum: CNRDY
- name: AFSDET - name: AFSDET
description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register.
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: AFSDETR enum: AFSDET
- name: LFSDET - name: LFSDET
description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: LFSDETR enum: LFSDET
- name: FLVL - name: FLVL
description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:"
bit_offset: 16 bit_offset: 16
bit_size: 3 bit_size: 3
enum_read: FLVLR enum: FLVL
enum/AFSDETR: enum/AFSDET:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoError - name: NoError
@ -407,7 +406,7 @@ enum/CKSTR:
- name: RisingEdge - name: RisingEdge
description: Data strobing edge is rising edge of SCK description: Data strobing edge is rising edge of SCK
value: 1 value: 1
enum/CNRDYR: enum/CNRDY:
bit_size: 1 bit_size: 1
variants: variants:
- name: Ready - name: Ready
@ -458,16 +457,7 @@ enum/DS:
- name: Bit32 - name: Bit32
description: 32 bits description: 32 bits
value: 7 value: 7
enum/FFLUSH: enum/FLVL:
bit_size: 1
variants:
- name: NoFlush
description: No FIFO flush
value: 0
- name: Flush
description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared
value: 1
enum/FLVLR:
bit_size: 3 bit_size: 3
variants: variants:
- name: Empty - name: Empty
@ -488,7 +478,7 @@ enum/FLVLR:
- name: Full - name: Full
description: FIFO full description: FIFO full
value: 5 value: 5
enum/FREQR: enum/FREQ:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoRequest - name: NoRequest
@ -533,7 +523,7 @@ enum/FTH:
- name: Full - name: Full
description: FIFO full description: FIFO full
value: 4 value: 4
enum/LFSDETR: enum/LFSDET:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoError - name: NoError
@ -575,7 +565,7 @@ enum/MONO:
- name: Mono - name: Mono
description: Mono mode description: Mono mode
value: 1 value: 1
enum/MUTEDETR: enum/MUTEDET:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoMute - name: NoMute
@ -611,7 +601,7 @@ enum/OUTDRIV:
- name: Immediately - name: Immediately
description: Audio block output driven immediately after the setting of this bit description: Audio block output driven immediately after the setting of this bit
value: 1 value: 1
enum/OVRUDRR: enum/OVRUDR:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoError - name: NoError
@ -665,7 +655,7 @@ enum/SYNCEN:
- name: External - name: External
description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode
value: 2 value: 2
enum/WCKCFGR: enum/WCKCFG:
bit_size: 1 bit_size: 1
variants: variants:
- name: Correct - name: Correct

42
data/registers/sai_v4.yaml
View File

@ -165,7 +165,6 @@ fieldset/CR2:
description: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. description: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled.
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
enum_write: FFLUSH
- name: TRIS - name: TRIS
description: "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details." description: "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details."
bit_offset: 4 bit_offset: 4
@ -357,43 +356,43 @@ fieldset/SR:
description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register."
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum_read: OVRUDRR enum: OVRUDR
- name: MUTEDET - name: MUTEDET
description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register.
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
enum_read: MUTEDETR enum: MUTEDET
- name: WCKCFG - name: WCKCFG
description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register."
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
enum_read: WCKCFGR enum: WCKCFG
- name: FREQ - name: FREQ
description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register."
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
enum_read: FREQR enum: FREQ
- name: CNRDY - name: CNRDY
description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register.
bit_offset: 4 bit_offset: 4
bit_size: 1 bit_size: 1
enum_read: CNRDYR enum: CNRDY
- name: AFSDET - name: AFSDET
description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register.
bit_offset: 5 bit_offset: 5
bit_size: 1 bit_size: 1
enum_read: AFSDETR enum: AFSDET
- name: LFSDET - name: LFSDET
description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register
bit_offset: 6 bit_offset: 6
bit_size: 1 bit_size: 1
enum_read: LFSDETR enum: LFSDET
- name: FLVL - name: FLVL
description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:"
bit_offset: 16 bit_offset: 16
bit_size: 3 bit_size: 3
enum_read: FLVLR enum: FLVL
enum/AFSDETR: enum/AFSDET:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoError - name: NoError
@ -411,7 +410,7 @@ enum/CKSTR:
- name: RisingEdge - name: RisingEdge
description: Data strobing edge is rising edge of SCK description: Data strobing edge is rising edge of SCK
value: 1 value: 1
enum/CNRDYR: enum/CNRDY:
bit_size: 1 bit_size: 1
variants: variants:
- name: Ready - name: Ready
@ -462,16 +461,7 @@ enum/DS:
- name: Bit32 - name: Bit32
description: 32 bits description: 32 bits
value: 7 value: 7
enum/FFLUSH: enum/FLVL:
bit_size: 1
variants:
- name: NoFlush
description: No FIFO flush
value: 0
- name: Flush
description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared
value: 1
enum/FLVLR:
bit_size: 3 bit_size: 3
variants: variants:
- name: Empty - name: Empty
@ -492,7 +482,7 @@ enum/FLVLR:
- name: Full - name: Full
description: FIFO full description: FIFO full
value: 5 value: 5
enum/FREQR: enum/FREQ:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoRequest - name: NoRequest
@ -537,7 +527,7 @@ enum/FTH:
- name: Full - name: Full
description: FIFO full description: FIFO full
value: 4 value: 4
enum/LFSDETR: enum/LFSDET:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoError - name: NoError
@ -579,7 +569,7 @@ enum/MONO:
- name: Mono - name: Mono
description: Mono mode description: Mono mode
value: 1 value: 1
enum/MUTEDETR: enum/MUTEDET:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoMute - name: NoMute
@ -615,7 +605,7 @@ enum/OUTDRIV:
- name: Immediately - name: Immediately
description: Audio block output driven immediately after the setting of this bit description: Audio block output driven immediately after the setting of this bit
value: 1 value: 1
enum/OVRUDRR: enum/OVRUDR:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoError - name: NoError
@ -669,7 +659,7 @@ enum/SYNCEN:
- name: External - name: External
description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode
value: 2 value: 2
enum/WCKCFGR: enum/WCKCFG:
bit_size: 1 bit_size: 1
variants: variants:
- name: Correct - name: Correct

25
data/registers/spi_v2.yaml
View File

@ -270,7 +270,7 @@ fieldset/SR:
description: Underrun flag description: Underrun flag
bit_offset: 3 bit_offset: 3
bit_size: 1 bit_size: 1
enum_read: UDRR enum: UDR
- name: CRCERR - name: CRCERR
description: CRC error flag description: CRC error flag
bit_offset: 4 bit_offset: 4
@ -291,17 +291,17 @@ fieldset/SR:
description: frame format error description: frame format error
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
enum_read: FRER enum: FRE
- name: FRLVL - name: FRLVL
description: FIFO reception level description: FIFO reception level
bit_offset: 9 bit_offset: 9
bit_size: 2 bit_size: 2
enum_read: FRLVLR enum: FRLVL
- name: FTLVL - name: FTLVL
description: FIFO Transmission Level description: FIFO Transmission Level
bit_offset: 11 bit_offset: 11
bit_size: 2 bit_size: 2
enum_read: FTLVLR enum: FTLVL
fieldset/TXCRCR: fieldset/TXCRCR:
description: TX CRC register description: TX CRC register
fields: fields:
@ -471,7 +471,7 @@ enum/DS:
- name: SixteenBit - name: SixteenBit
description: 16-bit description: 16-bit
value: 15 value: 15
enum/FRER: enum/FRE:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoError - name: NoError
@ -489,7 +489,7 @@ enum/FRF:
- name: TI - name: TI
description: SPI TI mode description: SPI TI mode
value: 1 value: 1
enum/FRLVLR: enum/FRLVL:
bit_size: 2 bit_size: 2
variants: variants:
- name: Empty - name: Empty
@ -513,7 +513,7 @@ enum/FRXTH:
- name: Quarter - name: Quarter
description: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) description: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
value: 1 value: 1
enum/FTLVLR: enum/FTLVL:
bit_size: 2 bit_size: 2
variants: variants:
- name: Empty - name: Empty
@ -630,15 +630,6 @@ enum/ODD:
- name: Odd - name: Odd
description: Real divider value is (I2SDIV * 2) + 1 description: Real divider value is (I2SDIV * 2) + 1
value: 1 value: 1
enum/OVRR:
bit_size: 1
variants:
- name: NoOverrun
description: No overrun occurred
value: 0
- name: Overrun
description: Overrun occurred
value: 1
enum/PCMSYNC: enum/PCMSYNC:
bit_size: 1 bit_size: 1
variants: variants:
@ -657,7 +648,7 @@ enum/RXONLY:
- name: OutputDisabled - name: OutputDisabled
description: Output disabled (Receive-only mode) description: Output disabled (Receive-only mode)
value: 1 value: 1
enum/UDRR: enum/UDR:
bit_size: 1 bit_size: 1
variants: variants:
- name: NoUnderrun - name: NoUnderrun

21
data/registers/spi_v3.yaml
View File

@ -475,27 +475,6 @@ enum/CRC_:
- name: Enabled - name: Enabled
description: Full size (33/17 bit) CRC polynomial is used description: Full size (33/17 bit) CRC polynomial is used
value: 1 value: 1
enum/DATFMT:
bit_size: 1
variants:
- name: RightAligned
description: The data inside RXDR and TXDR are right aligned
value: 0
- name: LeftAligned
description: The data inside RXDR and TXDR are left aligned
value: 1
enum/DATLEN:
bit_size: 2
variants:
- name: Bits16
description: 16 bit data length
value: 0
- name: Bits24
description: 24 bit data length
value: 1
- name: Bits32
description: 32 bit data length
value: 2
enum/FTHLV: enum/FTHLV:
bit_size: 4 bit_size: 4
variants: variants:

21
data/registers/spi_v4.yaml
View File

@ -468,27 +468,6 @@ enum/CRC_:
- name: Enabled - name: Enabled
description: Full size (33/17 bit) CRC polynomial is used description: Full size (33/17 bit) CRC polynomial is used
value: 1 value: 1
enum/DATFMT:
bit_size: 1
variants:
- name: RightAligned
description: The data inside RXDR and TXDR are right aligned
value: 0
- name: LeftAligned
description: The data inside RXDR and TXDR are left aligned
value: 1
enum/DATLEN:
bit_size: 2
variants:
- name: Bits16
description: 16 bit data length
value: 0
- name: Bits24
description: 24 bit data length
value: 1
- name: Bits32
description: 32 bit data length
value: 2
enum/FTHLV: enum/FTHLV:
bit_size: 4 bit_size: 4
variants: variants:

21
data/registers/spi_v5.yaml
View File

@ -486,27 +486,6 @@ enum/CRC_:
- name: Enabled - name: Enabled
description: Full size (33/17 bit) CRC polynomial is used description: Full size (33/17 bit) CRC polynomial is used
value: 1 value: 1
enum/DATFMT:
bit_size: 1
variants:
- name: RightAligned
description: The data inside RXDR and TXDR are right aligned
value: 0
- name: LeftAligned
description: The data inside RXDR and TXDR are left aligned
value: 1
enum/DATLEN:
bit_size: 2
variants:
- name: Bits16
description: 16 bit data length
value: 0
- name: Bits24
description: 24 bit data length
value: 1
- name: Bits32
description: 32 bit data length
value: 2
enum/FTHLV: enum/FTHLV:
bit_size: 4 bit_size: 4
variants: variants:

17
data/registers/syscfg_f0.yaml
View File

@ -167,8 +167,6 @@ fieldset/CFGR2:
description: SRAM parity flag description: SRAM parity flag
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
enum_read: SRAM_PEFR
enum_write: SRAM_PEFW
fieldset/EXTICR: fieldset/EXTICR:
description: external interrupt configuration register 1 description: external interrupt configuration register 1
fields: fields:
@ -341,21 +339,6 @@ enum/SRAM_PARITY_LOCK:
- name: Connected - name: Connected
description: SRAM parity error connected to TIM1/15/16/17 Break input description: SRAM parity error connected to TIM1/15/16/17 Break input
value: 1 value: 1
enum/SRAM_PEFR:
bit_size: 1
variants:
- name: NoParityError
description: No SRAM parity error detected
value: 0
- name: ParityErrorDetected
description: SRAM parity error detected
value: 1
enum/SRAM_PEFW:
bit_size: 1
variants:
- name: Clear
description: Clear SRAM parity error flag
value: 1
enum/TIM16_DMA_RMP: enum/TIM16_DMA_RMP:
bit_size: 1 bit_size: 1
variants: variants:

350
data/registers/syscfg_f3.yaml
View File

@ -209,8 +209,6 @@ fieldset/CFGR2:
description: SRAM parity flag description: SRAM parity flag
bit_offset: 8 bit_offset: 8
bit_size: 1 bit_size: 1
enum_read: SRAM_PEFR
enum_write: SRAM_PEFW
fieldset/CFGR3: fieldset/CFGR3:
description: configuration register 3 description: configuration register 3
fields: fields:
@ -562,27 +560,6 @@ enum/BYP_ADDR_PAR:
- name: Bypass - name: Bypass
description: The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated description: The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated
value: 1 value: 1
enum/CFGR1_ADC2_DMA_RMP:
bit_size: 1
variants:
- name: NotRemapped
description: ADC24 DMA requests mapped on DMA2 channels 1 and 2
value: 0
- name: Remapped
description: ADC24 DMA requests mapped on DMA2 channels 3 and 4
value: 1
enum/CFGR3_ADC2_DMA_RMP:
bit_size: 2
variants:
- name: MapDma2
description: ADC2 mapped on DMA2
value: 0
- name: MapDma1Ch2
description: ADC2 mapped on DMA1 channel 2
value: 2
- name: MapDma1Ch4
description: ADC2 mapped on DMA1 channel 4
value: 3
enum/DAC1_TRIG3_RMP: enum/DAC1_TRIG3_RMP:
bit_size: 1 bit_size: 1
variants: variants:
@ -640,318 +617,6 @@ enum/ENCODER_MODE:
- name: MapTim3Tim15 - name: MapTim3Tim15
description: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively description: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
value: 2 value: 2
enum/EXTI0:
bit_size: 4
variants:
- name: PA0
description: Select PA0 as the source input for the EXTI0 external interrupt
value: 0
- name: PB0
description: Select PB0 as the source input for the EXTI0 external interrupt
value: 1
- name: PC0
description: Select PC0 as the source input for the EXTI0 external interrupt
value: 2
- name: PD0
description: Select PD0 as the source input for the EXTI0 external interrupt
value: 3
- name: PE0
description: Select PE0 as the source input for the EXTI0 external interrupt
value: 4
- name: PF0
description: Select PF0 as the source input for the EXTI0 external interrupt
value: 5
enum/EXTI1:
bit_size: 4
variants:
- name: PA1
description: Select PA1 as the source input for the EXTI1 external interrupt
value: 0
- name: PB1
description: Select PB1 as the source input for the EXTI1 external interrupt
value: 1
- name: PC1
description: Select PC1 as the source input for the EXTI1 external interrupt
value: 2
- name: PD1
description: Select PD1 as the source input for the EXTI1 external interrupt
value: 3
- name: PE1
description: Select PE1 as the source input for the EXTI1 external interrupt
value: 4
- name: PF1
description: Select PF1 as the source input for the EXTI1 external interrupt
value: 5
enum/EXTI10:
bit_size: 4
variants:
- name: PA10
description: Select PA10 as the source input for the EXTI10 external interrupt
value: 0
- name: PB10
description: Select PB10 as the source input for the EXTI10 external interrupt
value: 1
- name: PC10
description: Select PC10 as the source input for the EXTI10 external interrupt
value: 2
- name: PD10
description: Select PD10 as the source input for the EXTI10 external interrupt
value: 3
- name: PE10
description: Select PE10 as the source input for the EXTI10 external interrupt
value: 4
- name: PF10
description: Select PF10 as the source input for the EXTI10 external interrupt
value: 5
enum/EXTI11:
bit_size: 4
variants:
- name: PA11
description: Select PA11 as the source input for the EXTI11 external interrupt
value: 0
- name: PB11
description: Select PB11 as the source input for the EXTI11 external interrupt
value: 1
- name: PC11
description: Select PC11 as the source input for the EXTI11 external interrupt
value: 2
- name: PD11
description: Select PD11 as the source input for the EXTI11 external interrupt
value: 3
- name: PE11
description: Select PE11 as the source input for the EXTI11 external interrupt
value: 4
enum/EXTI12:
bit_size: 4
variants:
- name: PA12
description: Select PA12 as the source input for the EXTI12 external interrupt
value: 0
- name: PB12
description: Select PB12 as the source input for the EXTI12 external interrupt
value: 1
- name: PC12
description: Select PC12 as the source input for the EXTI12 external interrupt
value: 2
- name: PD12
description: Select PD12 as the source input for the EXTI12 external interrupt
value: 3
- name: PE12
description: Select PE12 as the source input for the EXTI12 external interrupt
value: 4
enum/EXTI13:
bit_size: 4
variants:
- name: PA13
description: Select PA13 as the source input for the EXTI13 external interrupt
value: 0
- name: PB13
description: Select PB13 as the source input for the EXTI13 external interrupt
value: 1
- name: PC13
description: Select PC13 as the source input for the EXTI13 external interrupt
value: 2
- name: PD13
description: Select PD13 as the source input for the EXTI13 external interrupt
value: 3
- name: PE13
description: Select PE13 as the source input for the EXTI13 external interrupt
value: 4
enum/EXTI14:
bit_size: 4
variants:
- name: PA14
description: Select PA14 as the source input for the EXTI14 external interrupt
value: 0
- name: PB14
description: Select PB14 as the source input for the EXTI14 external interrupt
value: 1
- name: PC14
description: Select PC14 as the source input for the EXTI14 external interrupt
value: 2
- name: PD14
description: Select PD14 as the source input for the EXTI14 external interrupt
value: 3
- name: PE14
description: Select PE14 as the source input for the EXTI14 external interrupt
value: 4
enum/EXTI15:
bit_size: 4
variants:
- name: PA15
description: Select PA15 as the source input for the EXTI15 external interrupt
value: 0
- name: PB15
description: Select PB15 as the source input for the EXTI15 external interrupt
value: 1
- name: PC15
description: Select PC15 as the source input for the EXTI15 external interrupt
value: 2
- name: PD15
description: Select PD15 as the source input for the EXTI15 external interrupt
value: 3
- name: PE15
description: Select PE15 as the source input for the EXTI15 external interrupt
value: 4
enum/EXTI2:
bit_size: 4
variants:
- name: PA2
description: Select PA2 as the source input for the EXTI2 external interrupt
value: 0
- name: PB2
description: Select PB2 as the source input for the EXTI2 external interrupt
value: 1
- name: PC2
description: Select PC2 as the source input for the EXTI2 external interrupt
value: 2
- name: PD2
description: Select PD2 as the source input for the EXTI2 external interrupt
value: 3
- name: PE2
description: Select PE2 as the source input for the EXTI2 external interrupt
value: 4
- name: PF2
description: Select PF2 as the source input for the EXTI2 external interrupt
value: 5
enum/EXTI3:
bit_size: 4
variants:
- name: PA3
description: Select PA3 as the source input for the EXTI3 external interrupt
value: 0
- name: PB3
description: Select PB3 as the source input for the EXTI3 external interrupt
value: 1
- name: PC3
description: Select PC3 as the source input for the EXTI3 external interrupt
value: 2
- name: PD3
description: Select PD3 as the source input for the EXTI3 external interrupt
value: 3
- name: PE3
description: Select PE3 as the source input for the EXTI3 external interrupt
value: 4
enum/EXTI4:
bit_size: 4
variants:
- name: PA4
description: Select PA4 as the source input for the EXTI4 external interrupt
value: 0
- name: PB4
description: Select PB4 as the source input for the EXTI4 external interrupt
value: 1
- name: PC4
description: Select PC4 as the source input for the EXTI4 external interrupt
value: 2
- name: PD4
description: Select PD4 as the source input for the EXTI4 external interrupt
value: 3
- name: PE4
description: Select PE4 as the source input for the EXTI4 external interrupt
value: 4
- name: PF4
description: Select PF4 as the source input for the EXTI4 external interrupt
value: 5
enum/EXTI5:
bit_size: 4
variants:
- name: PA5
description: Select PA5 as the source input for the EXTI5 external interrupt
value: 0
- name: PB5
description: Select PB5 as the source input for the EXTI5 external interrupt
value: 1
- name: PC5
description: Select PC5 as the source input for the EXTI5 external interrupt
value: 2
- name: PD5
description: Select PD5 as the source input for the EXTI5 external interrupt
value: 3
- name: PE5
description: Select PE5 as the source input for the EXTI5 external interrupt
value: 4
- name: PF5
description: Select PF5 as the source input for the EXTI5 external interrupt
value: 5
enum/EXTI6:
bit_size: 4
variants:
- name: PA6
description: Select PA6 as the source input for the EXTI6 external interrupt
value: 0
- name: PB6
description: Select PB6 as the source input for the EXTI6 external interrupt
value: 1
- name: PC6
description: Select PC6 as the source input for the EXTI6 external interrupt
value: 2
- name: PD6
description: Select PD6 as the source input for the EXTI6 external interrupt
value: 3
- name: PE6
description: Select PE6 as the source input for the EXTI6 external interrupt
value: 4
- name: PF6
description: Select PF6 as the source input for the EXTI6 external interrupt
value: 5
enum/EXTI7:
bit_size: 4
variants:
- name: PA7
description: Select PA7 as the source input for the EXTI7 external interrupt
value: 0
- name: PB7
description: Select PB7 as the source input for the EXTI7 external interrupt
value: 1
- name: PC7
description: Select PC7 as the source input for the EXTI7 external interrupt
value: 2
- name: PD7
description: Select PD7 as the source input for the EXTI7 external interrupt
value: 3
- name: PE7
description: Select PE7 as the source input for the EXTI7 external interrupt
value: 4
enum/EXTI8:
bit_size: 4
variants:
- name: PA8
description: Select PA8 as the source input for the EXTI8 external interrupt
value: 0
- name: PB8
description: Select PB8 as the source input for the EXTI8 external interrupt
value: 1
- name: PC8
description: Select PC8 as the source input for the EXTI8 external interrupt
value: 2
- name: PD8
description: Select PD8 as the source input for the EXTI8 external interrupt
value: 3
- name: PE8
description: Select PE8 as the source input for the EXTI8 external interrupt
value: 4
enum/EXTI9:
bit_size: 4
variants:
- name: PA9
description: Select PA9 as the source input for the EXTI9 external interrupt
value: 0
- name: PB9
description: Select PB9 as the source input for the EXTI9 external interrupt
value: 1
- name: PC9
description: Select PC9 as the source input for the EXTI9 external interrupt
value: 2
- name: PD9
description: Select PD9 as the source input for the EXTI9 external interrupt
value: 3
- name: PE9
description: Select PE9 as the source input for the EXTI9 external interrupt
value: 4
- name: PF9
description: Select PF9 as the source input for the EXTI9 external interrupt
value: 5
enum/FPU_IE0: enum/FPU_IE0:
bit_size: 1 bit_size: 1
variants: variants:
@ -1168,21 +833,6 @@ enum/SRAM_PARITY_LOCK:
- name: Connected - name: Connected
description: SRAM parity error signal connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs description: SRAM parity error signal connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs
value: 1 value: 1
enum/SRAM_PEFR:
bit_size: 1
variants:
- name: NoParityError
description: No SRAM parity error detected
value: 0
- name: ParityErrorDetected
description: SRAM parity error detected
value: 1
enum/SRAM_PEFW:
bit_size: 1
variants:
- name: Clear
description: Clear SRAM parity error flag
value: 1
enum/TIM16_DMA_RMP: enum/TIM16_DMA_RMP:
bit_size: 1 bit_size: 1
variants: variants:

24
data/registers/wwdg_v1.yaml
View File

@ -30,7 +30,6 @@ fieldset/CFR:
description: Early wakeup interrupt description: Early wakeup interrupt
bit_offset: 9 bit_offset: 9
bit_size: 1 bit_size: 1
enum_write: EWIW
fieldset/CR: fieldset/CR:
description: Control register description: Control register
fields: fields:
@ -50,29 +49,6 @@ fieldset/SR:
description: Early wakeup interrupt flag description: Early wakeup interrupt flag
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum_read: EWIFR
enum_write: EWIFW
enum/EWIFR:
bit_size: 1
variants:
- name: Finished
description: The EWI Interrupt Service Routine has been serviced
value: 0
- name: Pending
description: The EWI Interrupt Service Routine has been triggered
value: 1
enum/EWIFW:
bit_size: 1
variants:
- name: Finished
description: The EWI Interrupt Service Routine has been serviced
value: 0
enum/EWIW:
bit_size: 1
variants:
- name: Enable
description: interrupt occurs whenever the counter reaches the value 0x40
value: 1
enum/WDGA: enum/WDGA:
bit_size: 1 bit_size: 1
variants: variants: