diff --git a/data/registers/adc_f1.yaml b/data/registers/adc_f1.yaml index ee9c98f..6edf6bf 100644 --- a/data/registers/adc_f1.yaml +++ b/data/registers/adc_f1.yaml @@ -171,12 +171,10 @@ fieldset/CR2: description: Start conversion of injected channels bit_offset: 21 bit_size: 1 - enum_write: JSWSTARTW - name: SWSTART description: Start conversion of regular channels bit_offset: 22 bit_size: 1 - enum_write: SWSTARTW - name: TSVREFE description: Temperature sensor and VREFINT enable bit_offset: 23 diff --git a/data/registers/adc_v1.yaml b/data/registers/adc_v1.yaml index 7f1bc9b..f008f04 100644 --- a/data/registers/adc_v1.yaml +++ b/data/registers/adc_v1.yaml @@ -154,32 +154,22 @@ fieldset/CR: description: ADC enable command bit_offset: 0 bit_size: 1 - enum_read: ADENR - enum_write: ADENW - name: ADDIS description: ADC disable command bit_offset: 1 bit_size: 1 - enum_read: ADDISR - enum_write: ADDISW - name: ADSTART description: ADC start conversion command bit_offset: 2 bit_size: 1 - enum_read: ADSTARTR - enum_write: ADSTARTW - name: ADSTP description: ADC stop conversion command bit_offset: 4 bit_size: 1 - enum_read: ADSTPR - enum_write: ADSTPW - name: ADCAL description: ADC calibration bit_offset: 31 bit_size: 1 - enum_read: ADCALR - enum_write: ADCALW fieldset/DR: description: data register fields: @@ -260,81 +250,6 @@ fieldset/TR: description: Analog watchdog higher threshold bit_offset: 16 bit_size: 12 -enum/ADCALR: - bit_size: 1 - variants: - - name: NotCalibrating - description: ADC calibration either not yet performed or completed - value: 0 - - name: Calibrating - description: ADC calibration in progress - value: 1 -enum/ADCALW: - bit_size: 1 - variants: - - name: StartCalibration - description: Start the ADC calibration sequence - value: 1 -enum/ADDISR: - bit_size: 1 - variants: - - name: NotDisabling - description: No disable command active - value: 0 - - name: Disabling - description: ADC disabling - value: 1 -enum/ADDISW: - bit_size: 1 - variants: - - name: Disable - description: Disable the ADC - value: 1 -enum/ADENR: - bit_size: 1 - variants: - - name: Disabled - description: ADC disabled - value: 0 - - name: Enabled - description: ADC enabled - value: 1 -enum/ADENW: - bit_size: 1 - variants: - - name: Enabled - description: Enable the ADC - value: 1 -enum/ADSTARTR: - bit_size: 1 - variants: - - name: NotActive - description: No conversion ongoing - value: 0 - - name: Active - description: ADC operating and may be converting - value: 1 -enum/ADSTARTW: - bit_size: 1 - variants: - - name: StartConversion - description: Start the ADC conversion (may be delayed for hardware triggers) - value: 1 -enum/ADSTPR: - bit_size: 1 - variants: - - name: NotStopping - description: No stop command active - value: 0 - - name: Stopping - description: ADC stopping conversion - value: 1 -enum/ADSTPW: - bit_size: 1 - variants: - - name: StopConversion - description: Stop the active conversion - value: 1 enum/ALIGN: bit_size: 1 variants: @@ -467,21 +382,3 @@ enum/SCANDIR: - name: Backward description: Backward scan (from CHSEL18 to CHSEL0) value: 1 -enum/TSEN: - bit_size: 1 - variants: - - name: Disabled - description: Temperature sensor disabled - value: 0 - - name: Enabled - description: Temperature sensor enabled - value: 1 -enum/VBATEN: - bit_size: 1 - variants: - - name: Disabled - description: V_BAT channel disabled - value: 0 - - name: Enabled - description: V_BAT channel enabled - value: 1 diff --git a/data/registers/adc_v2.yaml b/data/registers/adc_v2.yaml index 87c377e..c66afcb 100644 --- a/data/registers/adc_v2.yaml +++ b/data/registers/adc_v2.yaml @@ -184,7 +184,6 @@ fieldset/CR2: description: Start conversion of injected channels bit_offset: 22 bit_size: 1 - enum_write: JSWSTARTW - name: EXTSEL description: External event select for regular group bit_offset: 24 @@ -199,7 +198,6 @@ fieldset/CR2: description: Start conversion of regular channels bit_offset: 30 bit_size: 1 - enum_write: SWSTARTW fieldset/DR: description: regular data register fields: @@ -618,12 +616,6 @@ enum/JSTRT: - name: Started description: Injected channel conversion has started value: 1 -enum/JSWSTARTW: - bit_size: 1 - variants: - - name: Start - description: Starts conversion of injected channels - value: 1 enum/OVR: bit_size: 1 variants: @@ -729,9 +721,3 @@ enum/STRT: - name: Started description: Regular channel conversion has started value: 1 -enum/SWSTARTW: - bit_size: 1 - variants: - - name: Start - description: Starts conversion of regular channels - value: 1 diff --git a/data/registers/adc_v4.yaml b/data/registers/adc_v4.yaml index 8d133b8..2eb9cd7 100644 --- a/data/registers/adc_v4.yaml +++ b/data/registers/adc_v4.yaml @@ -289,12 +289,10 @@ fieldset/CR: description: enable bit_offset: 0 bit_size: 1 - enum_write: ADENW - name: ADDIS description: disable bit_offset: 1 bit_size: 1 - enum_write: ADDISW - name: ADSTART description: group regular conversion start bit_offset: 2 @@ -642,18 +640,6 @@ enum/ADCALDIF: - name: Differential description: Calibration for differential mode value: 1 -enum/ADDISW: - bit_size: 1 - variants: - - name: Disable - description: Disable conversion and go to power down mode - value: 0 -enum/ADENW: - bit_size: 1 - variants: - - name: Enable - description: Enable ADC - value: 1 enum/ADSTP: bit_size: 1 variants: diff --git a/data/registers/bkp_v1.yaml b/data/registers/bkp_v1.yaml index 4d12784..6f85991 100644 --- a/data/registers/bkp_v1.yaml +++ b/data/registers/bkp_v1.yaml @@ -81,12 +81,10 @@ fieldset/CSR: description: Clear Tamper event bit_offset: 0 bit_size: 1 - enum_write: CTEW - name: CTI description: Clear Tamper Interrupt bit_offset: 1 bit_size: 1 - enum_write: CTIW - name: TPIE description: Tamper Pin interrupt enable bit_offset: 2 @@ -135,18 +133,6 @@ enum/ASOS: - name: Second description: RTC Second pulse output selected value: 1 -enum/CTEW: - bit_size: 1 - variants: - - name: Reset - description: Reset the TEF Tamper event flag (and the Tamper detector) - value: 1 -enum/CTIW: - bit_size: 1 - variants: - - name: Clear - description: Clear the Tamper interrupt and the TIF Tamper interrupt flag - value: 1 enum/TPAL: bit_size: 1 variants: diff --git a/data/registers/can_bxcan.yaml b/data/registers/can_bxcan.yaml index 73fb865..c7f1ad4 100644 --- a/data/registers/can_bxcan.yaml +++ b/data/registers/can_bxcan.yaml @@ -449,19 +449,14 @@ fieldset/RFR: description: FULL0 bit_offset: 3 bit_size: 1 - enum_read: FULLR - enum_write: FULLW - name: FOVR description: FOVR0 bit_offset: 4 bit_size: 1 - enum_read: FOVRR - enum_write: FOVRW - name: RFOM description: RFOM0 bit_offset: 5 bit_size: 1 - enum_write: RFOMW fieldset/RIR: description: receive FIFO mailbox identifier register fields: @@ -662,36 +657,6 @@ enum/FOVIE: - name: Enabled description: Interrupt generated when FOVR bit is set value: 1 -enum/FOVRR: - bit_size: 1 - variants: - - name: NoOverrun - description: No FIFO x overrun - value: 0 - - name: Overrun - description: FIFO x overrun - value: 1 -enum/FOVRW: - bit_size: 1 - variants: - - name: Clear - description: Clear flag - value: 1 -enum/FULLR: - bit_size: 1 - variants: - - name: NotFull - description: FIFO x is not full - value: 0 - - name: Full - description: FIFO x is full - value: 1 -enum/FULLW: - bit_size: 1 - variants: - - name: Clear - description: Clear flag - value: 1 enum/LBKM: bit_size: 1 variants: @@ -737,12 +702,6 @@ enum/LECIE: - name: Enabled description: "ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection" value: 1 -enum/RFOMW: - bit_size: 1 - variants: - - name: Release - description: Set by software to release the output mailbox of the FIFO - value: 1 enum/RIR_IDE: bit_size: 1 variants: diff --git a/data/registers/crs_v1.yaml b/data/registers/crs_v1.yaml index 28581df..ab22b40 100644 --- a/data/registers/crs_v1.yaml +++ b/data/registers/crs_v1.yaml @@ -136,33 +136,6 @@ fieldset/ISR: description: Frequency error capture bit_offset: 16 bit_size: 16 -enum/SYNCDIV: - bit_size: 3 - variants: - - name: DIV1 - description: f(SYNCDIV) = f(SYNCSRC) - value: 0 - - name: DIV2 - description: f(SYNCDIV) = f(SYNCSRC)/2 - value: 1 - - name: DIV4 - description: f(SYNCDIV) = f(SYNCSRC)/4 - value: 2 - - name: DIV8 - description: f(SYNCDIV) = f(SYNCSRC)/8 - value: 3 - - name: DIV16 - description: f(SYNCDIV) = f(SYNCSRC)/16 - value: 4 - - name: DIV32 - description: f(SYNCDIV) = f(SYNCSRC)/32 - value: 5 - - name: DIV64 - description: f(SYNCDIV) = f(SYNCSRC)/64 - value: 6 - - name: DIV128 - description: f(SYNCDIV) = f(SYNCSRC)/128 - value: 7 enum/SYNCSRC: bit_size: 2 variants: diff --git a/data/registers/eth_v1a.yaml b/data/registers/eth_v1a.yaml index 7f19043..7977977 100644 --- a/data/registers/eth_v1a.yaml +++ b/data/registers/eth_v1a.yaml @@ -1462,12 +1462,6 @@ enum/DM: - name: FullDuplex description: MAC operates in full-duplex mode value: 1 -enum/DMABMR_SR: - bit_size: 1 - variants: - - name: Reset - description: Reset all MAC subsystem internal registers and logic. Cleared automatically - value: 1 enum/DMAOMR_SR: bit_size: 1 variants: @@ -1825,15 +1819,6 @@ enum/RDP: - name: RDP32 description: 32 beats per RxDMA transaction value: 32 -enum/RE: - bit_size: 1 - variants: - - name: Disabled - description: MAC receive state machine is disabled after the completion of the reception of the current frame - value: 0 - - name: Enabled - description: MAC receive state machine is enabled - value: 1 enum/RFAEM: bit_size: 1 variants: @@ -1963,15 +1948,6 @@ enum/ST: - name: Started description: Transmission is placed in Running state value: 1 -enum/TE: - bit_size: 1 - variants: - - name: Disabled - description: MAC transmit state machine is disabled after completion of the transmission of the current frame - value: 0 - - name: Enabled - description: MAC transmit state machine is enabled - value: 1 enum/TFCE: bit_size: 1 variants: diff --git a/data/registers/eth_v1b.yaml b/data/registers/eth_v1b.yaml index fec0571..3eda175 100644 --- a/data/registers/eth_v1b.yaml +++ b/data/registers/eth_v1b.yaml @@ -1507,12 +1507,6 @@ enum/DM: - name: FullDuplex description: MAC operates in full-duplex mode value: 1 -enum/DMABMR_SR: - bit_size: 1 - variants: - - name: Reset - description: Reset all MAC subsystem internal registers and logic. Cleared automatically - value: 1 enum/DMAOMR_SR: bit_size: 1 variants: @@ -1903,15 +1897,6 @@ enum/RDP: - name: RDP32 description: 32 beats per RxDMA transaction value: 32 -enum/RE: - bit_size: 1 - variants: - - name: Disabled - description: MAC receive state machine is disabled after the completion of the reception of the current frame - value: 0 - - name: Enabled - description: MAC receive state machine is enabled - value: 1 enum/RFAEM: bit_size: 1 variants: @@ -2041,15 +2026,6 @@ enum/ST: - name: Started description: Transmission is placed in Running state value: 1 -enum/TE: - bit_size: 1 - variants: - - name: Disabled - description: MAC transmit state machine is disabled after completion of the transmission of the current frame - value: 0 - - name: Enabled - description: MAC transmit state machine is enabled - value: 1 enum/TFCE: bit_size: 1 variants: diff --git a/data/registers/eth_v1c.yaml b/data/registers/eth_v1c.yaml index fec0571..3eda175 100644 --- a/data/registers/eth_v1c.yaml +++ b/data/registers/eth_v1c.yaml @@ -1507,12 +1507,6 @@ enum/DM: - name: FullDuplex description: MAC operates in full-duplex mode value: 1 -enum/DMABMR_SR: - bit_size: 1 - variants: - - name: Reset - description: Reset all MAC subsystem internal registers and logic. Cleared automatically - value: 1 enum/DMAOMR_SR: bit_size: 1 variants: @@ -1903,15 +1897,6 @@ enum/RDP: - name: RDP32 description: 32 beats per RxDMA transaction value: 32 -enum/RE: - bit_size: 1 - variants: - - name: Disabled - description: MAC receive state machine is disabled after the completion of the reception of the current frame - value: 0 - - name: Enabled - description: MAC receive state machine is enabled - value: 1 enum/RFAEM: bit_size: 1 variants: @@ -2041,15 +2026,6 @@ enum/ST: - name: Started description: Transmission is placed in Running state value: 1 -enum/TE: - bit_size: 1 - variants: - - name: Disabled - description: MAC transmit state machine is disabled after completion of the transmission of the current frame - value: 0 - - name: Enabled - description: MAC transmit state machine is enabled - value: 1 enum/TFCE: bit_size: 1 variants: diff --git a/data/registers/flash_l0.yaml b/data/registers/flash_l0.yaml index aa1b7d9..edb9c00 100644 --- a/data/registers/flash_l0.yaml +++ b/data/registers/flash_l0.yaml @@ -156,7 +156,6 @@ fieldset/PECR: description: Launch the option byte loading bit_offset: 18 bit_size: 1 - enum_write: OBL_LAUNCHW fieldset/PEKEYR: description: Program/erase key register fields: diff --git a/data/registers/fmc_v1x3.yaml b/data/registers/fmc_v1x3.yaml index 9ee5577..259d84b 100644 --- a/data/registers/fmc_v1x3.yaml +++ b/data/registers/fmc_v1x3.yaml @@ -399,7 +399,7 @@ fieldset/SDCMR: description: Command mode bit_offset: 0 bit_size: 3 - enum_write: MODE + enum: MODE - name: CTB2 description: Command target bank 2 bit_offset: 3 @@ -469,7 +469,6 @@ fieldset/SDRTR: description: Clear Refresh error flag bit_offset: 0 bit_size: 1 - enum_write: CRE - name: COUNT description: Refresh Timer Count bit_offset: 1 @@ -489,12 +488,12 @@ fieldset/SDSR: description: Status Mode for Bank 1 bit_offset: 1 bit_size: 2 - enum_read: MODES + enum: MODES - name: MODES2 description: Status Mode for Bank 2 bit_offset: 3 bit_size: 2 - enum_read: MODES + enum: MODES - name: BUSY description: Busy status bit_offset: 5 @@ -606,12 +605,6 @@ enum/CPSIZE: - name: Bytes1024 description: 1024 bytes CRAM page size value: 4 -enum/CRE: - bit_size: 1 - variants: - - name: Clear - description: Refresh Error Flag is cleared - value: 1 enum/ECCPS: bit_size: 3 variants: diff --git a/data/registers/fmc_v2x1.yaml b/data/registers/fmc_v2x1.yaml index 8bc56df..ad43c48 100644 --- a/data/registers/fmc_v2x1.yaml +++ b/data/registers/fmc_v2x1.yaml @@ -357,7 +357,7 @@ fieldset/SDCMR: description: Command mode bit_offset: 0 bit_size: 3 - enum_write: MODE + enum: MODE - name: CTB2 description: Command target bank 2 bit_offset: 3 @@ -427,7 +427,6 @@ fieldset/SDRTR: description: Clear Refresh error flag bit_offset: 0 bit_size: 1 - enum_write: CRE - name: COUNT description: Refresh Timer Count bit_offset: 1 @@ -447,12 +446,12 @@ fieldset/SDSR: description: Status Mode for Bank 1 bit_offset: 1 bit_size: 2 - enum_read: MODES + enum: MODES - name: MODES2 description: Status Mode for Bank 2 bit_offset: 3 bit_size: 2 - enum_read: MODES + enum: MODES - name: BUSY description: Busy status bit_offset: 5 @@ -564,12 +563,6 @@ enum/CPSIZE: - name: Bytes1024 description: 1024 bytes CRAM page size value: 4 -enum/CRE: - bit_size: 1 - variants: - - name: Clear - description: Refresh Error Flag is cleared - value: 1 enum/ECCPS: bit_size: 3 variants: diff --git a/data/registers/fmc_v3x1.yaml b/data/registers/fmc_v3x1.yaml index f662b9a..bdac456 100644 --- a/data/registers/fmc_v3x1.yaml +++ b/data/registers/fmc_v3x1.yaml @@ -360,7 +360,7 @@ fieldset/SDCMR: description: Command mode bit_offset: 0 bit_size: 3 - enum_write: MODE + enum: MODE - name: CTB2 description: Command target bank 2 bit_offset: 3 @@ -430,7 +430,6 @@ fieldset/SDRTR: description: Clear Refresh error flag bit_offset: 0 bit_size: 1 - enum_write: CRE - name: COUNT description: Refresh Timer Count bit_offset: 1 @@ -450,12 +449,12 @@ fieldset/SDSR: description: Status Mode for Bank 1 bit_offset: 1 bit_size: 2 - enum_read: MODES + enum: MODES - name: MODES2 description: Status Mode for Bank 2 bit_offset: 3 bit_size: 2 - enum_read: MODES + enum: MODES fieldset/SDTR: description: SDRAM Timing register fields: @@ -563,12 +562,6 @@ enum/CPSIZE: - name: Bytes1024 description: 1024 bytes CRAM page size value: 4 -enum/CRE: - bit_size: 1 - variants: - - name: Clear - description: Refresh Error Flag is cleared - value: 1 enum/ECCPS: bit_size: 3 variants: diff --git a/data/registers/gpio_v1.yaml b/data/registers/gpio_v1.yaml index 10a495e..37eabef 100644 --- a/data/registers/gpio_v1.yaml +++ b/data/registers/gpio_v1.yaml @@ -42,7 +42,6 @@ fieldset/BRR: array: len: 16 stride: 1 - enum_write: BRW fieldset/BSRR: description: Port bit set/reset register (GPIOn_BSRR) fields: diff --git a/data/registers/hrtim_v1.yaml b/data/registers/hrtim_v1.yaml index f242101..922b954 100644 --- a/data/registers/hrtim_v1.yaml +++ b/data/registers/hrtim_v1.yaml @@ -296,22 +296,18 @@ fieldset/MICR: array: len: 4 stride: 1 - enum_write: ICR - name: MREPC description: Repetition Interrupt flag clear bit_offset: 4 bit_size: 1 - enum_write: ICR - name: SYNCC description: Sync Input Interrupt flag clear bit_offset: 5 bit_size: 1 - enum_write: ICR - name: MUPDC description: Master update Interrupt flag clear bit_offset: 6 bit_size: 1 - enum_write: ICR fieldset/MISR: description: Master Timer Interrupt Status Register fields: @@ -322,22 +318,22 @@ fieldset/MISR: array: len: 4 stride: 1 - enum_read: EVENT + enum: EVENT - name: MREP description: Master Repetition Interrupt Flag bit_offset: 4 bit_size: 1 - enum_read: EVENT + enum: EVENT - name: SYNC description: Sync Input Interrupt Flag bit_offset: 5 bit_size: 1 - enum_read: EVENT + enum: EVENT - name: MUPD description: Master Update Interrupt Flag bit_offset: 6 bit_size: 1 - enum_read: EVENT + enum: EVENT fieldset/MPER: description: Master Timer Period Register fields: @@ -766,17 +762,14 @@ fieldset/TIMXICR: array: len: 4 stride: 1 - enum_write: ICR - name: REPC description: Repetition Interrupt flag Clear bit_offset: 4 bit_size: 1 - enum_write: ICR - name: UPDC description: Update Interrupt flag Clear bit_offset: 6 bit_size: 1 - enum_write: ICR - name: CPTC description: Capture X Interrupt flag Clear bit_offset: 7 @@ -784,7 +777,6 @@ fieldset/TIMXICR: array: len: 2 stride: 1 - enum_write: ICR - name: SETRC description: Output X Set flag Clear bit_offset: 9 @@ -793,7 +785,6 @@ fieldset/TIMXICR: offsets: - 0 - 2 - enum_write: ICR - name: RSTRC description: Output X Reset flag Clear bit_offset: 10 @@ -802,17 +793,14 @@ fieldset/TIMXICR: offsets: - 0 - 2 - enum_write: ICR - name: RSTC description: Reset Interrupt flag Clear bit_offset: 13 bit_size: 1 - enum_write: ICR - name: DLYPRTC description: Delayed Protection Flag Clear bit_offset: 14 bit_size: 1 - enum_write: ICR fieldset/TIMXISR: description: Timerx Interrupt Status Register fields: @@ -823,17 +811,17 @@ fieldset/TIMXISR: array: len: 4 stride: 1 - enum_read: EVENT + enum: EVENT - name: REP description: Repetition Interrupt Flag bit_offset: 4 bit_size: 1 - enum_read: EVENT + enum: EVENT - name: UPD description: Update Interrupt Flag bit_offset: 6 bit_size: 1 - enum_read: EVENT + enum: EVENT - name: CPT description: Capture X Interrupt Flag bit_offset: 7 @@ -841,7 +829,7 @@ fieldset/TIMXISR: array: len: 2 stride: 1 - enum_read: EVENT + enum: EVENT - name: SETR description: Output X Set Interrupt Flag bit_offset: 9 @@ -850,7 +838,7 @@ fieldset/TIMXISR: offsets: - 0 - 2 - enum_read: EVENT + enum: EVENT - name: RSTR description: Output X Reset Interrupt Flag bit_offset: 10 @@ -859,27 +847,27 @@ fieldset/TIMXISR: offsets: - 0 - 2 - enum_read: EVENT + enum: EVENT - name: RST description: Reset Interrupt Flag bit_offset: 13 bit_size: 1 - enum_read: EVENT + enum: EVENT - name: DLYPRT description: Delayed Protection Flag bit_offset: 14 bit_size: 1 - enum_read: TIMAISR_DLYPRT + enum: TIMAISR_DLYPRT - name: CPPSTAT description: Current Push Pull Status bit_offset: 16 bit_size: 1 - enum_read: CPPSTAT + enum: CPPSTAT - name: IPPSTAT description: Idle Push Pull Status bit_offset: 17 bit_size: 1 - enum_read: IPPSTAT + enum: IPPSTAT - name: OSTAT description: Output X State bit_offset: 18 @@ -887,7 +875,7 @@ fieldset/TIMXISR: array: len: 2 stride: 1 - enum_read: OUTPUTSTATE + enum: OUTPUTSTATE - name: OCPY description: Output X Copy bit_offset: 20 @@ -895,7 +883,7 @@ fieldset/TIMXISR: array: len: 2 stride: 1 - enum_read: OUTPUTSTATE + enum: OUTPUTSTATE fieldset/TIMXOUTR: description: Timerx Output Register fields: @@ -1356,12 +1344,6 @@ enum/FLTEN: - name: Active description: Fault input is active and can disable HRTIM outputs value: 1 -enum/ICR: - bit_size: 1 - variants: - - name: Clear - description: Clears associated flag in ISR register - value: 1 enum/IDLEM: bit_size: 1 variants: diff --git a/data/registers/ltdc_v1.yaml b/data/registers/ltdc_v1.yaml index 90638ff..c8c5026 100644 --- a/data/registers/ltdc_v1.yaml +++ b/data/registers/ltdc_v1.yaml @@ -488,15 +488,6 @@ fieldset/WVPCR: description: Window Vertical Stop Position bit_offset: 16 bit_size: 11 -enum/BF1: - bit_size: 3 - variants: - - name: Constant - description: BF1 = constant alpha - value: 4 - - name: Pixel - description: BF1 = pixel alpha * constant alpha - value: 6 enum/BF2: bit_size: 3 variants: diff --git a/data/registers/pwr_wl5.yaml b/data/registers/pwr_wl5.yaml index b4809d1..2c15757 100644 --- a/data/registers/pwr_wl5.yaml +++ b/data/registers/pwr_wl5.yaml @@ -279,7 +279,6 @@ fieldset/EXTSCR: description: Clear CPU1 Stop Standby flags bit_offset: 0 bit_size: 1 - enum_write: CCSSFW - name: C2CSSF description: lear CPU2 Stop Standby flags bit_offset: 1 @@ -347,17 +346,14 @@ fieldset/SCR: array: len: 3 stride: 1 - enum_write: CWUFW - name: CWPVDF description: Clear wakeup PVD interrupt flag bit_offset: 8 bit_size: 1 - enum_write: CWPVDFW - name: CWRFBUSYF description: Clear wakeup Radio BUSY flag bit_offset: 11 bit_size: 1 - enum_write: CWRFBUSYFW - name: CC2HF description: lear CPU2 Hold interrupt flag bit_offset: 14 @@ -486,12 +482,6 @@ enum/APC: - name: Enabled description: PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os value: 1 -enum/CCSSFW: - bit_size: 1 - variants: - - name: Clear - description: Setting this bit clears the C1STOPF and C1SBF bits - value: 1 enum/CDS: bit_size: 1 variants: @@ -519,24 +509,6 @@ enum/CSTOPF: - name: Stop description: System has been in Stop 2 mode value: 1 -enum/CWPVDFW: - bit_size: 1 - variants: - - name: Clear - description: Setting this bit clears the WPVDF flag in the PWR_SR1. This bit is always read as 0. - value: 1 -enum/CWRFBUSYFW: - bit_size: 1 - variants: - - name: Clear - description: Setting this bit clears the WRFBUSYF flag in the PWR_SR1. This bit is always read 0. - value: 1 -enum/CWUFW: - bit_size: 1 - variants: - - name: Clear - description: Setting this bit clears the WUF2 flag in the PWR_SR1 register. This bit is always read as 0. - value: 1 enum/DBP: bit_size: 1 variants: @@ -672,42 +644,6 @@ enum/NSS: - name: High description: Sub-GHz SPI NSS signal is at level high value: 1 -enum/PD: - bit_size: 1 - variants: - - name: Disabled - description: "Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" - value: 0 - - name: Enabled - description: "Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" - value: 1 -enum/PDCRA_PD: - bit_size: 1 - variants: - - name: Disabled - description: "Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" - value: 0 - - name: Enabled - description: "Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" - value: 1 -enum/PDCRB_PD: - bit_size: 1 - variants: - - name: Disabled - description: "Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" - value: 0 - - name: Enabled - description: "Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" - value: 1 -enum/PDCRC_PD: - bit_size: 1 - variants: - - name: Disabled - description: "Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" - value: 0 - - name: Enabled - description: "Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" - value: 1 enum/PLS: bit_size: 3 variants: @@ -735,42 +671,6 @@ enum/PLS: - name: External description: External input analog voltage PVD_IN (compared internally to VREFINT) value: 7 -enum/PU: - bit_size: 1 - variants: - - name: Disabled - description: "Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" - value: 0 - - name: Enabled - description: "Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set" - value: 1 -enum/PUCRA_PU: - bit_size: 1 - variants: - - name: Disabled - description: "Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" - value: 0 - - name: Enabled - description: "Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set" - value: 1 -enum/PUCRB_PU: - bit_size: 1 - variants: - - name: Disabled - description: "Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" - value: 0 - - name: Enabled - description: "Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set" - value: 1 -enum/PUCRC_PU: - bit_size: 1 - variants: - - name: Disabled - description: "Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)" - value: 0 - - name: Enabled - description: "Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set" - value: 1 enum/PVDE: bit_size: 1 variants: diff --git a/data/registers/rcc_f0.yaml b/data/registers/rcc_f0.yaml index f58741a..d2b860f 100644 --- a/data/registers/rcc_f0.yaml +++ b/data/registers/rcc_f0.yaml @@ -445,7 +445,7 @@ fieldset/CFGR: description: System Clock Switch Status bit_offset: 2 bit_size: 2 - enum_read: SWSR + enum: SWS - name: HPRE description: AHB prescaler bit_offset: 4 @@ -1058,7 +1058,7 @@ enum/SW: - name: HSI48 description: HSI48 selected as system clock (when available) value: 3 -enum/SWSR: +enum/SWS: bit_size: 2 variants: - name: HSI diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml index 57fd23e..a96555a 100644 --- a/data/registers/rcc_f1.yaml +++ b/data/registers/rcc_f1.yaml @@ -453,7 +453,7 @@ fieldset/CFGR: description: System Clock Switch Status bit_offset: 2 bit_size: 2 - enum_read: SWSR + enum: SWS - name: HPRE description: AHB prescaler bit_offset: 4 @@ -829,7 +829,7 @@ enum/SW: - name: PLL description: PLL selected as system clock value: 2 -enum/SWSR: +enum/SWS: bit_size: 2 variants: - name: HSI diff --git a/data/registers/rcc_f100.yaml b/data/registers/rcc_f100.yaml index 6caf3a9..a094e0b 100644 --- a/data/registers/rcc_f100.yaml +++ b/data/registers/rcc_f100.yaml @@ -421,7 +421,7 @@ fieldset/CFGR: description: System Clock Switch Status bit_offset: 2 bit_size: 2 - enum_read: SWSR + enum: SWS - name: HPRE description: AHB prescaler bit_offset: 4 @@ -851,7 +851,7 @@ enum/SW: - name: PLL description: PLL selected as system clock value: 2 -enum/SWSR: +enum/SWS: bit_size: 2 variants: - name: HSI diff --git a/data/registers/rcc_f1cl.yaml b/data/registers/rcc_f1cl.yaml index 2512e2d..e48898f 100644 --- a/data/registers/rcc_f1cl.yaml +++ b/data/registers/rcc_f1cl.yaml @@ -400,7 +400,7 @@ fieldset/CFGR: description: System Clock Switch Status bit_offset: 2 bit_size: 2 - enum_read: SWSR + enum: SWS - name: HPRE description: AHB prescaler bit_offset: 4 @@ -938,7 +938,7 @@ enum/SW: - name: PLL description: PLL selected as system clock value: 2 -enum/SWSR: +enum/SWS: bit_size: 2 variants: - name: HSI diff --git a/data/registers/rcc_f2.yaml b/data/registers/rcc_f2.yaml index 7517af8..2f35de9 100644 --- a/data/registers/rcc_f2.yaml +++ b/data/registers/rcc_f2.yaml @@ -895,7 +895,7 @@ fieldset/CFGR: description: System clock switch status bit_offset: 2 bit_size: 2 - enum_read: SWSR + enum: SWS - name: HPRE description: AHB prescaler bit_offset: 4 @@ -1338,7 +1338,7 @@ enum/SW: - name: PLL description: PLL selected as system clock value: 2 -enum/SWSR: +enum/SWS: bit_size: 2 variants: - name: HSI diff --git a/data/registers/rcc_f3.yaml b/data/registers/rcc_f3.yaml index 40724a8..008f091 100644 --- a/data/registers/rcc_f3.yaml +++ b/data/registers/rcc_f3.yaml @@ -581,7 +581,7 @@ fieldset/CFGR: description: System Clock Switch Status bit_offset: 2 bit_size: 2 - enum_read: SWSR + enum: SWS - name: HPRE description: AHB prescaler bit_offset: 4 @@ -1327,7 +1327,7 @@ enum/SW: - name: PLL description: PLL selected as system clock value: 2 -enum/SWSR: +enum/SWS: bit_size: 2 variants: - name: HSI diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index 0669cc2..b9f138a 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -1224,7 +1224,7 @@ fieldset/CFGR: description: System clock switch status bit_offset: 2 bit_size: 2 - enum_read: SWSR + enum: SWS - name: HPRE description: AHB prescaler bit_offset: 4 @@ -1844,15 +1844,6 @@ enum/I2S1SRC: - name: HSI_HSE description: "I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])" value: 3 -enum/I2SSRC: - bit_size: 1 - variants: - - name: PLLI2S - description: PLLI2S clock used as I2S clock source - value: 0 - - name: CKIN - description: External clock mapped on the I2S_CKIN pin used as I2S clock source - value: 1 enum/ISSRC: bit_size: 1 variants: @@ -2534,7 +2525,7 @@ enum/SW: - name: PLL description: PLL selected as system clock value: 2 -enum/SWSR: +enum/SWS: bit_size: 2 variants: - name: HSI diff --git a/data/registers/rcc_f410.yaml b/data/registers/rcc_f410.yaml index 638a180..b65a21e 100644 --- a/data/registers/rcc_f410.yaml +++ b/data/registers/rcc_f410.yaml @@ -505,7 +505,7 @@ fieldset/CFGR: description: System clock switch status bit_offset: 2 bit_size: 2 - enum_read: SWSR + enum: SWS - name: HPRE description: AHB prescaler bit_offset: 4 @@ -984,7 +984,7 @@ enum/SW: - name: PLL description: PLL selected as system clock value: 2 -enum/SWSR: +enum/SWS: bit_size: 2 variants: - name: HSI diff --git a/data/registers/rcc_f7.yaml b/data/registers/rcc_f7.yaml index 51a2ccc..fc6fe61 100644 --- a/data/registers/rcc_f7.yaml +++ b/data/registers/rcc_f7.yaml @@ -1216,7 +1216,7 @@ fieldset/CFGR: description: System clock switch status bit_offset: 2 bit_size: 2 - enum_read: SWSR + enum: SWS - name: HPRE description: AHB prescaler bit_offset: 4 @@ -2202,7 +2202,7 @@ enum/SW: - name: PLL description: PLL selected as system clock value: 2 -enum/SWSR: +enum/SWS: bit_size: 2 variants: - name: HSI diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index 1118881..fd9da11 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -2761,7 +2761,7 @@ fieldset/CFGR: description: System clock switch status bit_offset: 3 bit_size: 3 - enum_read: SWSR + enum: SWS - name: STOPWUCK description: System clock selection after a wake up from system Stop bit_offset: 6 @@ -4236,7 +4236,7 @@ enum/SWPSEL: - name: HSI_KER description: hsi_ker selected as peripheral clock value: 1 -enum/SWSR: +enum/SWS: bit_size: 3 variants: - name: HSI diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml index dd50ee9..ef8723b 100644 --- a/data/registers/rcc_h7ab.yaml +++ b/data/registers/rcc_h7ab.yaml @@ -1728,7 +1728,7 @@ fieldset/CFGR: description: System clock switch status bit_offset: 3 bit_size: 3 - enum_read: SWSR + enum: SWS - name: STOPWUCK description: System clock selection after a wake up from system Stop bit_offset: 6 @@ -3171,7 +3171,7 @@ enum/SWPSEL: - name: HSI_KER description: hsi_ker selected as peripheral clock value: 1 -enum/SWSR: +enum/SWS: bit_size: 3 variants: - name: HSI diff --git a/data/registers/rtc_v2f0.yaml b/data/registers/rtc_v2f0.yaml index d94e8fa..24dca5e 100644 --- a/data/registers/rtc_v2f0.yaml +++ b/data/registers/rtc_v2f0.yaml @@ -319,12 +319,12 @@ fieldset/ISR: array: len: 1 stride: 1 - enum_read: ALRWFR + enum: ALRWF - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 - enum_read: WUTWFR + enum: WUTWF - name: SHPF description: Shift operation pending bit_offset: 3 @@ -333,18 +333,16 @@ fieldset/ISR: description: Initialization status flag bit_offset: 4 bit_size: 1 - enum_read: INITSR + enum: INITS - name: RSF description: Registers synchronization flag bit_offset: 5 bit_size: 1 - enum_read: RSFR - enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 - enum_read: INITFR + enum: INITF - name: INIT description: Initialization mode bit_offset: 7 @@ -357,26 +355,18 @@ fieldset/ISR: array: len: 1 stride: 1 - enum_read: ALRFR - enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 bit_size: 1 - enum_read: WUTFR - enum_write: WUTFW - name: TSF description: Timestamp flag bit_offset: 11 bit_size: 1 - enum_read: TSFR - enum_write: TSFW - name: TSOVF description: Timestamp overflow flag bit_offset: 12 bit_size: 1 - enum_read: TSOVFR - enum_write: TSOVFW - name: TAMPF description: Tamper detection flag bit_offset: 13 @@ -384,13 +374,10 @@ fieldset/ISR: array: len: 3 stride: 1 - enum_read: TAMPFR - enum_write: TAMPFW - name: RECALPF description: Recalibration pending flag bit_offset: 16 bit_size: 1 - enum_read: RECALPFR fieldset/PRER: description: Prescaler register fields: @@ -608,18 +595,6 @@ fieldset/WUTR: description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ALRFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 -enum/ALRFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/ALRMR_MSK: bit_size: 1 variants: @@ -647,7 +622,7 @@ enum/ALRMR_WDSEL: - name: WeekDay description: "DU[3:0] represents the week day. DT[1:0] is don’t care" value: 1 -enum/ALRWFR: +enum/ALRWF: bit_size: 1 variants: - name: UpdateNotAllowed @@ -713,7 +688,7 @@ enum/INIT: - name: InitMode description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." value: 1 -enum/INITFR: +enum/INITF: bit_size: 1 variants: - name: NotAllowed @@ -722,7 +697,7 @@ enum/INITFR: - name: Allowed description: Calendar registers update is allowed value: 1 -enum/INITSR: +enum/INITS: bit_size: 1 variants: - name: NotInitalized @@ -770,12 +745,6 @@ enum/POL: - name: Low description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" value: 1 -enum/RECALPFR: - bit_size: 1 - variants: - - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" - value: 1 enum/REFCKON: bit_size: 1 variants: @@ -785,21 +754,6 @@ enum/REFCKON: - name: Enabled description: RTC_REFIN detection enabled value: 1 -enum/RSFR: - bit_size: 1 - variants: - - name: NotSynced - description: Calendar shadow registers not yet synchronized - value: 0 - - name: Synced - description: Calendar shadow registers synchronized - value: 1 -enum/RSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/TAMPFLT: bit_size: 2 variants: @@ -815,12 +769,6 @@ enum/TAMPFLT: - name: Samples8 description: Tamper event is activated after 8 consecutive samples at the active level value: 3 -enum/TAMPFR: - bit_size: 1 - variants: - - name: Tampered - description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input - value: 1 enum/TAMPFREQ: bit_size: 3 variants: @@ -848,12 +796,6 @@ enum/TAMPFREQ: - name: Div256 description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) value: 7 -enum/TAMPFW: - bit_size: 1 - variants: - - name: Clear - description: Flag cleared by software writing 0 - value: 0 enum/TAMPPRCH: bit_size: 2 variants: @@ -896,30 +838,6 @@ enum/TSEDGE: - name: FallingEdge description: RTC_TS input falling edge generates a time-stamp event value: 1 -enum/TSFR: - bit_size: 1 - variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 -enum/TSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/TSOVFR: - bit_size: 1 - variants: - - name: Overflow - description: This flag is set by hardware when a timestamp event occurs while TSF is already set - value: 1 -enum/TSOVFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/WUCKSEL: bit_size: 3 variants: @@ -941,19 +859,7 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTFR: - bit_size: 1 - variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 -enum/WUTFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/WUTWFR: +enum/WUTWF: bit_size: 1 variants: - name: UpdateNotAllowed diff --git a/data/registers/rtc_v2f2.yaml b/data/registers/rtc_v2f2.yaml index d4c88e6..7d637a2 100644 --- a/data/registers/rtc_v2f2.yaml +++ b/data/registers/rtc_v2f2.yaml @@ -269,28 +269,26 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRWFR + enum: ALRWF - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 - enum_read: WUTWFR + enum: WUTWF - name: INITS description: Initialization status flag bit_offset: 4 bit_size: 1 - enum_read: INITSR + enum: INITS - name: RSF description: Registers synchronization flag bit_offset: 5 bit_size: 1 - enum_read: RSFR - enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 - enum_read: INITFR + enum: INITF - name: INIT description: Initialization mode bit_offset: 7 @@ -303,26 +301,18 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRFR - enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 bit_size: 1 - enum_read: WUTFR - enum_write: WUTFW - name: TSF description: Timestamp flag bit_offset: 11 bit_size: 1 - enum_read: TSFR - enum_write: TSFW - name: TSOVF description: Timestamp overflow flag bit_offset: 12 bit_size: 1 - enum_read: TSOVFR - enum_write: TSOVFW - name: TAMPF description: Tamper detection flag bit_offset: 13 @@ -330,8 +320,6 @@ fieldset/ISR: array: len: 1 stride: 1 - enum_read: TAMPFR - enum_write: TAMPFW fieldset/PRER: description: Prescaler register fields: @@ -478,18 +466,6 @@ fieldset/WUTR: description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ALRFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 -enum/ALRFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/ALRMR_MSK: bit_size: 1 variants: @@ -517,7 +493,7 @@ enum/ALRMR_WDSEL: - name: WeekDay description: "DU[3:0] represents the week day. DT[1:0] is don’t care" value: 1 -enum/ALRWFR: +enum/ALRWF: bit_size: 1 variants: - name: UpdateNotAllowed @@ -535,36 +511,6 @@ enum/AMPM: - name: PM description: PM value: 1 -enum/CALP: - bit_size: 1 - variants: - - name: NoChange - description: No RTCCLK pulses are added - value: 0 - - name: IncreaseFreq - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - value: 1 -enum/CALW16: - bit_size: 1 - variants: - - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" - value: 1 -enum/CALW8: - bit_size: 1 - variants: - - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 -enum/FMT: - bit_size: 1 - variants: - - name: Twenty_Four_Hour - description: 24 hour/day format - value: 0 - - name: AM_PM - description: AM/PM hour format - value: 1 enum/INIT: bit_size: 1 variants: @@ -574,7 +520,7 @@ enum/INIT: - name: InitMode description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." value: 1 -enum/INITFR: +enum/INITF: bit_size: 1 variants: - name: NotAllowed @@ -583,7 +529,7 @@ enum/INITFR: - name: Allowed description: Calendar registers update is allowed value: 1 -enum/INITSR: +enum/INITS: bit_size: 1 variants: - name: NotInitalized @@ -625,33 +571,6 @@ enum/REFCKON: - name: Enabled description: RTC_REFIN detection enabled value: 1 -enum/RSFR: - bit_size: 1 - variants: - - name: NotSynced - description: Calendar shadow registers not yet synchronized - value: 0 - - name: Synced - description: Calendar shadow registers synchronized - value: 1 -enum/RSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/TAMPFR: - bit_size: 1 - variants: - - name: Tampered - description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input - value: 1 -enum/TAMPFW: - bit_size: 1 - variants: - - name: Clear - description: Flag cleared by software writing 0 - value: 0 enum/TAMPTRG: bit_size: 1 variants: @@ -670,30 +589,6 @@ enum/TSEDGE: - name: FallingEdge description: RTC_TS input falling edge generates a time-stamp event value: 1 -enum/TSFR: - bit_size: 1 - variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 -enum/TSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/TSOVFR: - bit_size: 1 - variants: - - name: Overflow - description: This flag is set by hardware when a timestamp event occurs while TSF is already set - value: 1 -enum/TSOVFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/WUCKSEL: bit_size: 3 variants: @@ -715,19 +610,7 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTFR: - bit_size: 1 - variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 -enum/WUTFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/WUTWFR: +enum/WUTWF: bit_size: 1 variants: - name: UpdateNotAllowed diff --git a/data/registers/rtc_v2f3.yaml b/data/registers/rtc_v2f3.yaml index 36a2c72..c74f90d 100644 --- a/data/registers/rtc_v2f3.yaml +++ b/data/registers/rtc_v2f3.yaml @@ -319,12 +319,12 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRWFR + enum: ALRWF - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 - enum_read: WUTWFR + enum: WUTWF - name: SHPF description: Shift operation pending bit_offset: 3 @@ -333,18 +333,16 @@ fieldset/ISR: description: Initialization status flag bit_offset: 4 bit_size: 1 - enum_read: INITSR + enum: INITS - name: RSF description: Registers synchronization flag bit_offset: 5 bit_size: 1 - enum_read: RSFR - enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 - enum_read: INITFR + enum: INITF - name: INIT description: Initialization mode bit_offset: 7 @@ -357,26 +355,18 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRFR - enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 bit_size: 1 - enum_read: WUTFR - enum_write: WUTFW - name: TSF description: Timestamp flag bit_offset: 11 bit_size: 1 - enum_read: TSFR - enum_write: TSFW - name: TSOVF description: Timestamp overflow flag bit_offset: 12 bit_size: 1 - enum_read: TSOVFR - enum_write: TSOVFW - name: TAMPF description: Tamper detection flag bit_offset: 13 @@ -384,13 +374,11 @@ fieldset/ISR: array: len: 3 stride: 1 - enum_read: TAMPFR - enum_write: TAMPFW - name: RECALPF description: Recalibration pending flag bit_offset: 16 bit_size: 1 - enum_read: RECALPFR + enum: RECALPF fieldset/PRER: description: Prescaler register fields: @@ -606,18 +594,6 @@ fieldset/WUTR: description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ALRFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 -enum/ALRFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/ALRMR_MSK: bit_size: 1 variants: @@ -645,7 +621,7 @@ enum/ALRMR_WDSEL: - name: WeekDay description: "DU[3:0] represents the week day. DT[1:0] is don’t care" value: 1 -enum/ALRWFR: +enum/ALRWF: bit_size: 1 variants: - name: UpdateNotAllowed @@ -711,7 +687,7 @@ enum/INIT: - name: InitMode description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." value: 1 -enum/INITFR: +enum/INITF: bit_size: 1 variants: - name: NotAllowed @@ -720,7 +696,7 @@ enum/INITFR: - name: Allowed description: Calendar registers update is allowed value: 1 -enum/INITSR: +enum/INITS: bit_size: 1 variants: - name: NotInitalized @@ -771,7 +747,7 @@ enum/POL: - name: Low description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" value: 1 -enum/RECALPFR: +enum/RECALPF: bit_size: 1 variants: - name: Pending @@ -786,21 +762,6 @@ enum/REFCKON: - name: Enabled description: RTC_REFIN detection enabled value: 1 -enum/RSFR: - bit_size: 1 - variants: - - name: NotSynced - description: Calendar shadow registers not yet synchronized - value: 0 - - name: Synced - description: Calendar shadow registers synchronized - value: 1 -enum/RSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/TAMPFLT: bit_size: 2 variants: @@ -816,12 +777,6 @@ enum/TAMPFLT: - name: Samples8 description: Tamper event is activated after 8 consecutive samples at the active level value: 3 -enum/TAMPFR: - bit_size: 1 - variants: - - name: Tampered - description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input - value: 1 enum/TAMPFREQ: bit_size: 3 variants: @@ -849,12 +804,6 @@ enum/TAMPFREQ: - name: Div256 description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) value: 7 -enum/TAMPFW: - bit_size: 1 - variants: - - name: Clear - description: Flag cleared by software writing 0 - value: 0 enum/TAMPPRCH: bit_size: 2 variants: @@ -897,30 +846,6 @@ enum/TSEDGE: - name: FallingEdge description: RTC_TS input falling edge generates a time-stamp event value: 1 -enum/TSFR: - bit_size: 1 - variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 -enum/TSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/TSOVFR: - bit_size: 1 - variants: - - name: Overflow - description: This flag is set by hardware when a timestamp event occurs while TSF is already set - value: 1 -enum/TSOVFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/WUCKSEL: bit_size: 3 variants: @@ -942,19 +867,7 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTFR: - bit_size: 1 - variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 -enum/WUTFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/WUTWFR: +enum/WUTWF: bit_size: 1 variants: - name: UpdateNotAllowed diff --git a/data/registers/rtc_v2f4.yaml b/data/registers/rtc_v2f4.yaml index 59a8346..4b7dfa7 100644 --- a/data/registers/rtc_v2f4.yaml +++ b/data/registers/rtc_v2f4.yaml @@ -338,12 +338,12 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRWFR + enum: ALRWF - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 - enum_read: WUTWFR + enum: WUTWF - name: SHPF description: Shift operation pending bit_offset: 3 @@ -352,18 +352,16 @@ fieldset/ISR: description: Initialization status flag bit_offset: 4 bit_size: 1 - enum_read: INITSR + enum: INITS - name: RSF description: Registers synchronization flag bit_offset: 5 bit_size: 1 - enum_read: RSFR - enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 - enum_read: INITFR + enum: INITF - name: INIT description: Initialization mode bit_offset: 7 @@ -376,26 +374,18 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRFR - enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 bit_size: 1 - enum_read: WUTFR - enum_write: WUTFW - name: TSF description: Timestamp flag bit_offset: 11 bit_size: 1 - enum_read: TSFR - enum_write: TSFW - name: TSOVF description: Timestamp overflow flag bit_offset: 12 bit_size: 1 - enum_read: TSOVFR - enum_write: TSOVFW - name: TAMPF description: Tamper detection flag bit_offset: 13 @@ -403,13 +393,11 @@ fieldset/ISR: array: len: 3 stride: 1 - enum_read: TAMPFR - enum_write: TAMPFW - name: RECALPF description: Recalibration pending flag bit_offset: 16 bit_size: 1 - enum_read: RECALPFR + enum: RECALPF fieldset/PRER: description: Prescaler register fields: @@ -607,18 +595,6 @@ fieldset/WUTR: description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ALRFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 -enum/ALRFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/ALRMR_MSK: bit_size: 1 variants: @@ -646,7 +622,7 @@ enum/ALRMR_WDSEL: - name: WeekDay description: "DU[3:0] represents the week day. DT[1:0] is don’t care" value: 1 -enum/ALRWFR: +enum/ALRWF: bit_size: 1 variants: - name: UpdateNotAllowed @@ -712,7 +688,7 @@ enum/INIT: - name: InitMode description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." value: 1 -enum/INITFR: +enum/INITF: bit_size: 1 variants: - name: NotAllowed @@ -721,7 +697,7 @@ enum/INITFR: - name: Allowed description: Calendar registers update is allowed value: 1 -enum/INITSR: +enum/INITS: bit_size: 1 variants: - name: NotInitalized @@ -754,7 +730,7 @@ enum/POL: - name: Low description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" value: 1 -enum/RECALPFR: +enum/RECALPF: bit_size: 1 variants: - name: Pending @@ -769,36 +745,6 @@ enum/REFCKON: - name: Enabled description: RTC_REFIN detection enabled value: 1 -enum/RSFR: - bit_size: 1 - variants: - - name: NotSynced - description: Calendar shadow registers not yet synchronized - value: 0 - - name: Synced - description: Calendar shadow registers synchronized - value: 1 -enum/RSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/SHPFR: - bit_size: 1 - variants: - - name: NoShiftPending - description: No shift operation is pending - value: 0 - - name: ShiftPending - description: A shift operation is pending - value: 1 -enum/SUB1HW: - bit_size: 1 - variants: - - name: Sub1 - description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode - value: 1 enum/TAMPFLT: bit_size: 2 variants: @@ -814,12 +760,6 @@ enum/TAMPFLT: - name: Samples8 description: Tamper event is activated after 8 consecutive samples at the active level value: 3 -enum/TAMPFR: - bit_size: 1 - variants: - - name: Tampered - description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input - value: 1 enum/TAMPFREQ: bit_size: 3 variants: @@ -847,12 +787,6 @@ enum/TAMPFREQ: - name: Div256 description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) value: 7 -enum/TAMPFW: - bit_size: 1 - variants: - - name: Clear - description: Flag cleared by software writing 0 - value: 0 enum/TAMPPRCH: bit_size: 2 variants: @@ -895,30 +829,6 @@ enum/TSEDGE: - name: FallingEdge description: RTC_TS input falling edge generates a time-stamp event value: 1 -enum/TSFR: - bit_size: 1 - variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 -enum/TSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/TSOVFR: - bit_size: 1 - variants: - - name: Overflow - description: This flag is set by hardware when a timestamp event occurs while TSF is already set - value: 1 -enum/TSOVFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/WUCKSEL: bit_size: 3 variants: @@ -940,19 +850,7 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTFR: - bit_size: 1 - variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 -enum/WUTFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/WUTWFR: +enum/WUTWF: bit_size: 1 variants: - name: UpdateNotAllowed diff --git a/data/registers/rtc_v2f7.yaml b/data/registers/rtc_v2f7.yaml index 3d9f690..9853772 100644 --- a/data/registers/rtc_v2f7.yaml +++ b/data/registers/rtc_v2f7.yaml @@ -327,12 +327,12 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRWFR + enum: ALRWF - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 - enum_read: WUTWFR + enum: WUTWF - name: SHPF description: Shift operation pending bit_offset: 3 @@ -341,18 +341,16 @@ fieldset/ISR: description: Initialization status flag bit_offset: 4 bit_size: 1 - enum_read: INITSR + enum: INITS - name: RSF description: Registers synchronization flag bit_offset: 5 bit_size: 1 - enum_read: RSFR - enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 - enum_read: INITFR + enum: INITF - name: INIT description: Initialization mode bit_offset: 7 @@ -365,26 +363,18 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRFR - enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 bit_size: 1 - enum_read: WUTFR - enum_write: WUTFW - name: TSF description: Timestamp flag bit_offset: 11 bit_size: 1 - enum_read: TSFR - enum_write: TSFW - name: TSOVF description: Timestamp overflow flag bit_offset: 12 bit_size: 1 - enum_read: TSOVFR - enum_write: TSOVFW - name: TAMPF description: Tamper detection flag bit_offset: 13 @@ -392,13 +382,11 @@ fieldset/ISR: array: len: 3 stride: 1 - enum_read: TAMPFR - enum_write: TAMPFW - name: RECALPF description: Recalibration pending flag bit_offset: 16 bit_size: 1 - enum_read: RECALPFR + enum: RECALPF - name: ITSF description: Internal time-stamp flag bit_offset: 17 @@ -622,18 +610,6 @@ fieldset/WUTR: description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ALRFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 -enum/ALRFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/ALRMR_MSK: bit_size: 1 variants: @@ -661,7 +637,7 @@ enum/ALRMR_WDSEL: - name: WeekDay description: "DU[3:0] represents the week day. DT[1:0] is don’t care" value: 1 -enum/ALRWFR: +enum/ALRWF: bit_size: 1 variants: - name: UpdateNotAllowed @@ -727,7 +703,7 @@ enum/INIT: - name: InitMode description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." value: 1 -enum/INITFR: +enum/INITF: bit_size: 1 variants: - name: NotAllowed @@ -736,7 +712,7 @@ enum/INITFR: - name: Allowed description: Calendar registers update is allowed value: 1 -enum/INITSR: +enum/INITS: bit_size: 1 variants: - name: NotInitalized @@ -769,7 +745,7 @@ enum/POL: - name: Low description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" value: 1 -enum/RECALPFR: +enum/RECALPF: bit_size: 1 variants: - name: Pending @@ -784,21 +760,6 @@ enum/REFCKON: - name: Enabled description: RTC_REFIN detection enabled value: 1 -enum/RSFR: - bit_size: 1 - variants: - - name: NotSynced - description: Calendar shadow registers not yet synchronized - value: 0 - - name: Synced - description: Calendar shadow registers synchronized - value: 1 -enum/RSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/TAMPFLT: bit_size: 2 variants: @@ -814,12 +775,6 @@ enum/TAMPFLT: - name: Samples8 description: Tamper event is activated after 8 consecutive samples at the active level value: 3 -enum/TAMPFR: - bit_size: 1 - variants: - - name: Tampered - description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input - value: 1 enum/TAMPFREQ: bit_size: 3 variants: @@ -847,12 +802,6 @@ enum/TAMPFREQ: - name: Div256 description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) value: 7 -enum/TAMPFW: - bit_size: 1 - variants: - - name: Clear - description: Flag cleared by software writing 0 - value: 0 enum/TAMPPRCH: bit_size: 2 variants: @@ -895,30 +844,6 @@ enum/TSEDGE: - name: FallingEdge description: RTC_TS input falling edge generates a time-stamp event value: 1 -enum/TSFR: - bit_size: 1 - variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 -enum/TSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/TSOVFR: - bit_size: 1 - variants: - - name: Overflow - description: This flag is set by hardware when a timestamp event occurs while TSF is already set - value: 1 -enum/TSOVFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/WUCKSEL: bit_size: 3 variants: @@ -940,19 +865,7 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTFR: - bit_size: 1 - variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 -enum/WUTFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/WUTWFR: +enum/WUTWF: bit_size: 1 variants: - name: UpdateNotAllowed diff --git a/data/registers/rtc_v2h7.yaml b/data/registers/rtc_v2h7.yaml index 5641381..5489e19 100644 --- a/data/registers/rtc_v2h7.yaml +++ b/data/registers/rtc_v2h7.yaml @@ -327,12 +327,12 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRWFR + enum: ALRWF - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 - enum_read: WUTWFR + enum: WUTWF - name: SHPF description: Shift operation pending bit_offset: 3 @@ -341,18 +341,16 @@ fieldset/ISR: description: Initialization status flag bit_offset: 4 bit_size: 1 - enum_read: INITSR + enum: INITS - name: RSF description: Registers synchronization flag bit_offset: 5 bit_size: 1 - enum_read: RSFR - enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 - enum_read: INITFR + enum: INITF - name: INIT description: Initialization mode bit_offset: 7 @@ -365,26 +363,18 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRFR - enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 bit_size: 1 - enum_read: WUTFR - enum_write: WUTFW - name: TSF description: Timestamp flag bit_offset: 11 bit_size: 1 - enum_read: TSFR - enum_write: TSFW - name: TSOVF description: Timestamp overflow flag bit_offset: 12 bit_size: 1 - enum_read: TSOVFR - enum_write: TSOVFW - name: TAMPF description: Tamper detection flag bit_offset: 13 @@ -392,13 +382,11 @@ fieldset/ISR: array: len: 3 stride: 1 - enum_read: TAMPFR - enum_write: TAMPFW - name: RECALPF description: Recalibration pending flag bit_offset: 16 bit_size: 1 - enum_read: RECALPFR + enum: RECALPF - name: ITSF description: Internal time-stamp flag bit_offset: 17 @@ -622,18 +610,6 @@ fieldset/WUTR: description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ALRFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 -enum/ALRFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/ALRMR_MSK: bit_size: 1 variants: @@ -661,7 +637,7 @@ enum/ALRMR_WDSEL: - name: WeekDay description: "DU[3:0] represents the week day. DT[1:0] is don’t care" value: 1 -enum/ALRWFR: +enum/ALRWF: bit_size: 1 variants: - name: UpdateNotAllowed @@ -727,7 +703,7 @@ enum/INIT: - name: InitMode description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." value: 1 -enum/INITFR: +enum/INITF: bit_size: 1 variants: - name: NotAllowed @@ -736,7 +712,7 @@ enum/INITFR: - name: Allowed description: Calendar registers update is allowed value: 1 -enum/INITSR: +enum/INITS: bit_size: 1 variants: - name: NotInitalized @@ -769,7 +745,7 @@ enum/POL: - name: Low description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" value: 1 -enum/RECALPFR: +enum/RECALPF: bit_size: 1 variants: - name: Pending @@ -784,21 +760,6 @@ enum/REFCKON: - name: Enabled description: RTC_REFIN detection enabled value: 1 -enum/RSFR: - bit_size: 1 - variants: - - name: NotSynced - description: Calendar shadow registers not yet synchronized - value: 0 - - name: Synced - description: Calendar shadow registers synchronized - value: 1 -enum/RSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/TAMPFLT: bit_size: 2 variants: @@ -814,12 +775,6 @@ enum/TAMPFLT: - name: Samples8 description: Tamper event is activated after 8 consecutive samples at the active level value: 3 -enum/TAMPFR: - bit_size: 1 - variants: - - name: Tampered - description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input - value: 1 enum/TAMPFREQ: bit_size: 3 variants: @@ -847,12 +802,6 @@ enum/TAMPFREQ: - name: Div256 description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) value: 7 -enum/TAMPFW: - bit_size: 1 - variants: - - name: Clear - description: Flag cleared by software writing 0 - value: 0 enum/TAMPPRCH: bit_size: 2 variants: @@ -895,30 +844,6 @@ enum/TSEDGE: - name: FallingEdge description: RTC_TS input falling edge generates a time-stamp event value: 1 -enum/TSFR: - bit_size: 1 - variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 -enum/TSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/TSOVFR: - bit_size: 1 - variants: - - name: Overflow - description: This flag is set by hardware when a timestamp event occurs while TSF is already set - value: 1 -enum/TSOVFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/WUCKSEL: bit_size: 3 variants: @@ -940,19 +865,7 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTFR: - bit_size: 1 - variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 -enum/WUTFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/WUTWFR: +enum/WUTWF: bit_size: 1 variants: - name: UpdateNotAllowed diff --git a/data/registers/rtc_v2l0.yaml b/data/registers/rtc_v2l0.yaml index 7b21208..a012125 100644 --- a/data/registers/rtc_v2l0.yaml +++ b/data/registers/rtc_v2l0.yaml @@ -323,12 +323,12 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRWFR + enum: ALRWF - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 - enum_read: WUTWFR + enum: WUTWF - name: SHPF description: Shift operation pending bit_offset: 3 @@ -337,18 +337,16 @@ fieldset/ISR: description: Initialization status flag bit_offset: 4 bit_size: 1 - enum_read: INITSR + enum: INITS - name: RSF description: Registers synchronization flag bit_offset: 5 bit_size: 1 - enum_read: RSFR - enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 - enum_read: INITFR + enum: INITF - name: INIT description: Initialization mode bit_offset: 7 @@ -361,26 +359,18 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRFR - enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 bit_size: 1 - enum_read: WUTFR - enum_write: WUTFW - name: TSF description: Timestamp flag bit_offset: 11 bit_size: 1 - enum_read: TSFR - enum_write: TSFW - name: TSOVF description: Timestamp overflow flag bit_offset: 12 bit_size: 1 - enum_read: TSOVFR - enum_write: TSOVFW - name: TAMPF description: Tamper detection flag bit_offset: 13 @@ -388,13 +378,11 @@ fieldset/ISR: array: len: 3 stride: 1 - enum_read: TAMPFR - enum_write: TAMPFW - name: RECALPF description: Recalibration pending flag bit_offset: 16 bit_size: 1 - enum_read: RECALPFR + enum: RECALPF fieldset/OR: description: Option register fields: @@ -614,18 +602,6 @@ fieldset/WUTR: description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ALRFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 -enum/ALRFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/ALRMR_MSK: bit_size: 1 variants: @@ -653,7 +629,7 @@ enum/ALRMR_WDSEL: - name: WeekDay description: "DU[3:0] represents the week day. DT[1:0] is don’t care" value: 1 -enum/ALRWFR: +enum/ALRWF: bit_size: 1 variants: - name: UpdateNotAllowed @@ -719,7 +695,7 @@ enum/INIT: - name: InitMode description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." value: 1 -enum/INITFR: +enum/INITF: bit_size: 1 variants: - name: NotAllowed @@ -728,7 +704,7 @@ enum/INITFR: - name: Allowed description: Calendar registers update is allowed value: 1 -enum/INITSR: +enum/INITS: bit_size: 1 variants: - name: NotInitalized @@ -761,7 +737,7 @@ enum/POL: - name: Low description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" value: 1 -enum/RECALPFR: +enum/RECALPF: bit_size: 1 variants: - name: Pending @@ -776,21 +752,6 @@ enum/REFCKON: - name: Enabled description: RTC_REFIN detection enabled value: 1 -enum/RSFR: - bit_size: 1 - variants: - - name: NotSynced - description: Calendar shadow registers not yet synchronized - value: 0 - - name: Synced - description: Calendar shadow registers synchronized - value: 1 -enum/RSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/TAMPFLT: bit_size: 2 variants: @@ -806,12 +767,6 @@ enum/TAMPFLT: - name: Samples8 description: Tamper event is activated after 8 consecutive samples at the active level value: 3 -enum/TAMPFR: - bit_size: 1 - variants: - - name: Tampered - description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input - value: 1 enum/TAMPFREQ: bit_size: 3 variants: @@ -839,12 +794,6 @@ enum/TAMPFREQ: - name: Div256 description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) value: 7 -enum/TAMPFW: - bit_size: 1 - variants: - - name: Clear - description: Flag cleared by software writing 0 - value: 0 enum/TAMPPRCH: bit_size: 2 variants: @@ -887,30 +836,6 @@ enum/TSEDGE: - name: FallingEdge description: RTC_TS input falling edge generates a time-stamp event value: 1 -enum/TSFR: - bit_size: 1 - variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 -enum/TSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/TSOVFR: - bit_size: 1 - variants: - - name: Overflow - description: This flag is set by hardware when a timestamp event occurs while TSF is already set - value: 1 -enum/TSOVFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/WUCKSEL: bit_size: 3 variants: @@ -932,19 +857,7 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTFR: - bit_size: 1 - variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 -enum/WUTFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/WUTWFR: +enum/WUTWF: bit_size: 1 variants: - name: UpdateNotAllowed diff --git a/data/registers/rtc_v2l1.yaml b/data/registers/rtc_v2l1.yaml index 9542064..65046df 100644 --- a/data/registers/rtc_v2l1.yaml +++ b/data/registers/rtc_v2l1.yaml @@ -338,12 +338,12 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRWFR + enum: ALRWF - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 - enum_read: WUTWFR + enum: WUTWF - name: SHPF description: Shift operation pending bit_offset: 3 @@ -352,18 +352,16 @@ fieldset/ISR: description: Initialization status flag bit_offset: 4 bit_size: 1 - enum_read: INITSR + enum: INITS - name: RSF description: Registers synchronization flag bit_offset: 5 bit_size: 1 - enum_read: RSFR - enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 - enum_read: INITFR + enum: INITF - name: INIT description: Initialization mode bit_offset: 7 @@ -376,26 +374,18 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRFR - enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 bit_size: 1 - enum_read: WUTFR - enum_write: WUTFW - name: TSF description: Timestamp flag bit_offset: 11 bit_size: 1 - enum_read: TSFR - enum_write: TSFW - name: TSOVF description: Timestamp overflow flag bit_offset: 12 bit_size: 1 - enum_read: TSOVFR - enum_write: TSOVFW - name: TAMPF description: Tamper detection flag bit_offset: 13 @@ -403,13 +393,11 @@ fieldset/ISR: array: len: 3 stride: 1 - enum_read: TAMPFR - enum_write: TAMPFW - name: RECALPF description: Recalibration pending flag bit_offset: 16 bit_size: 1 - enum_read: RECALPFR + enum: RECALPF fieldset/PRER: description: Prescaler register fields: @@ -601,18 +589,6 @@ fieldset/WUTR: description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ALRFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 -enum/ALRFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/ALRMR_MSK: bit_size: 1 variants: @@ -640,7 +616,7 @@ enum/ALRMR_WDSEL: - name: WeekDay description: "DU[3:0] represents the week day. DT[1:0] is don’t care" value: 1 -enum/ALRWFR: +enum/ALRWF: bit_size: 1 variants: - name: UpdateNotAllowed @@ -706,7 +682,7 @@ enum/INIT: - name: InitMode description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." value: 1 -enum/INITFR: +enum/INITF: bit_size: 1 variants: - name: NotAllowed @@ -715,7 +691,7 @@ enum/INITFR: - name: Allowed description: Calendar registers update is allowed value: 1 -enum/INITSR: +enum/INITS: bit_size: 1 variants: - name: NotInitalized @@ -748,7 +724,7 @@ enum/POL: - name: Low description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" value: 1 -enum/RECALPFR: +enum/RECALPF: bit_size: 1 variants: - name: Pending @@ -763,21 +739,6 @@ enum/REFCKON: - name: Enabled description: RTC_REFIN detection enabled value: 1 -enum/RSFR: - bit_size: 1 - variants: - - name: NotSynced - description: Calendar shadow registers not yet synchronized - value: 0 - - name: Synced - description: Calendar shadow registers synchronized - value: 1 -enum/RSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/TAMPFLT: bit_size: 2 variants: @@ -793,12 +754,6 @@ enum/TAMPFLT: - name: Samples8 description: Tamper event is activated after 8 consecutive samples at the active level value: 3 -enum/TAMPFR: - bit_size: 1 - variants: - - name: Tampered - description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input - value: 1 enum/TAMPFREQ: bit_size: 3 variants: @@ -826,12 +781,6 @@ enum/TAMPFREQ: - name: Div256 description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) value: 7 -enum/TAMPFW: - bit_size: 1 - variants: - - name: Clear - description: Flag cleared by software writing 0 - value: 0 enum/TAMPPRCH: bit_size: 2 variants: @@ -874,30 +823,6 @@ enum/TSEDGE: - name: FallingEdge description: RTC_TS input falling edge generates a time-stamp event value: 1 -enum/TSFR: - bit_size: 1 - variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 -enum/TSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/TSOVFR: - bit_size: 1 - variants: - - name: Overflow - description: This flag is set by hardware when a timestamp event occurs while TSF is already set - value: 1 -enum/TSOVFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/WUCKSEL: bit_size: 3 variants: @@ -919,19 +844,7 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTFR: - bit_size: 1 - variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 -enum/WUTFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/WUTWFR: +enum/WUTWF: bit_size: 1 variants: - name: UpdateNotAllowed diff --git a/data/registers/rtc_v2l4.yaml b/data/registers/rtc_v2l4.yaml index 393e13e..4caa837 100644 --- a/data/registers/rtc_v2l4.yaml +++ b/data/registers/rtc_v2l4.yaml @@ -327,12 +327,12 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRWFR + enum: ALRWF - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 - enum_read: WUTWFR + enum: WUTWF - name: SHPF description: Shift operation pending bit_offset: 3 @@ -341,18 +341,16 @@ fieldset/ISR: description: Initialization status flag bit_offset: 4 bit_size: 1 - enum_read: INITSR + enum: INITS - name: RSF description: Registers synchronization flag bit_offset: 5 bit_size: 1 - enum_read: RSFR - enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 - enum_read: INITFR + enum: INITF - name: INIT description: Initialization mode bit_offset: 7 @@ -365,26 +363,18 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRFR - enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 bit_size: 1 - enum_read: WUTFR - enum_write: WUTFW - name: TSF description: Timestamp flag bit_offset: 11 bit_size: 1 - enum_read: TSFR - enum_write: TSFW - name: TSOVF description: Timestamp overflow flag bit_offset: 12 bit_size: 1 - enum_read: TSOVFR - enum_write: TSOVFW - name: TAMPF description: Tamper detection flag bit_offset: 13 @@ -392,13 +382,11 @@ fieldset/ISR: array: len: 3 stride: 1 - enum_read: TAMPFR - enum_write: TAMPFW - name: RECALPF description: Recalibration pending flag bit_offset: 16 bit_size: 1 - enum_read: RECALPFR + enum: RECALPF fieldset/OR: description: Option register fields: @@ -618,18 +606,6 @@ fieldset/WUTR: description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ALRFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 -enum/ALRFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/ALRMR_MSK: bit_size: 1 variants: @@ -657,7 +633,7 @@ enum/ALRMR_WDSEL: - name: WeekDay description: "DU[3:0] represents the week day. DT[1:0] is don’t care" value: 1 -enum/ALRWFR: +enum/ALRWF: bit_size: 1 variants: - name: UpdateNotAllowed @@ -723,7 +699,7 @@ enum/INIT: - name: InitMode description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." value: 1 -enum/INITFR: +enum/INITF: bit_size: 1 variants: - name: NotAllowed @@ -732,7 +708,7 @@ enum/INITFR: - name: Allowed description: Calendar registers update is allowed value: 1 -enum/INITSR: +enum/INITS: bit_size: 1 variants: - name: NotInitalized @@ -765,7 +741,7 @@ enum/POL: - name: Low description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" value: 1 -enum/RECALPFR: +enum/RECALPF: bit_size: 1 variants: - name: Pending @@ -780,21 +756,6 @@ enum/REFCKON: - name: Enabled description: RTC_REFIN detection enabled value: 1 -enum/RSFR: - bit_size: 1 - variants: - - name: NotSynced - description: Calendar shadow registers not yet synchronized - value: 0 - - name: Synced - description: Calendar shadow registers synchronized - value: 1 -enum/RSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/TAMPFLT: bit_size: 2 variants: @@ -810,12 +771,6 @@ enum/TAMPFLT: - name: Samples8 description: Tamper event is activated after 8 consecutive samples at the active level value: 3 -enum/TAMPFR: - bit_size: 1 - variants: - - name: Tampered - description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input - value: 1 enum/TAMPFREQ: bit_size: 3 variants: @@ -843,12 +798,6 @@ enum/TAMPFREQ: - name: Div256 description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) value: 7 -enum/TAMPFW: - bit_size: 1 - variants: - - name: Clear - description: Flag cleared by software writing 0 - value: 0 enum/TAMPPRCH: bit_size: 2 variants: @@ -891,30 +840,6 @@ enum/TSEDGE: - name: FallingEdge description: RTC_TS input falling edge generates a time-stamp event value: 1 -enum/TSFR: - bit_size: 1 - variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 -enum/TSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/TSOVFR: - bit_size: 1 - variants: - - name: Overflow - description: This flag is set by hardware when a timestamp event occurs while TSF is already set - value: 1 -enum/TSOVFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/WUCKSEL: bit_size: 3 variants: @@ -936,19 +861,7 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTFR: - bit_size: 1 - variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 -enum/WUTFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/WUTWFR: +enum/WUTWF: bit_size: 1 variants: - name: UpdateNotAllowed diff --git a/data/registers/rtc_v2wb.yaml b/data/registers/rtc_v2wb.yaml index 4a49b0b..27991b1 100644 --- a/data/registers/rtc_v2wb.yaml +++ b/data/registers/rtc_v2wb.yaml @@ -327,12 +327,12 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRWFR + enum: ALRWF - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 - enum_read: WUTWFR + enum: WUTWF - name: SHPF description: Shift operation pending bit_offset: 3 @@ -341,18 +341,16 @@ fieldset/ISR: description: Initialization status flag bit_offset: 4 bit_size: 1 - enum_read: INITSR + enum: INITS - name: RSF description: Registers synchronization flag bit_offset: 5 bit_size: 1 - enum_read: RSFR - enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 - enum_read: INITFR + enum: INITF - name: INIT description: Initialization mode bit_offset: 7 @@ -365,26 +363,18 @@ fieldset/ISR: array: len: 2 stride: 1 - enum_read: ALRFR - enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 bit_size: 1 - enum_read: WUTFR - enum_write: WUTFW - name: TSF description: Timestamp flag bit_offset: 11 bit_size: 1 - enum_read: TSFR - enum_write: TSFW - name: TSOVF description: Timestamp overflow flag bit_offset: 12 bit_size: 1 - enum_read: TSOVFR - enum_write: TSOVFW - name: TAMPF description: Tamper detection flag bit_offset: 13 @@ -392,13 +382,11 @@ fieldset/ISR: array: len: 3 stride: 1 - enum_read: TAMPFR - enum_write: TAMPFW - name: RECALPF description: Recalibration pending flag bit_offset: 16 bit_size: 1 - enum_read: RECALPFR + enum: RECALPF - name: ITSF description: Internal time-stamp flag bit_offset: 17 @@ -622,18 +610,6 @@ fieldset/WUTR: description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ALRFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 -enum/ALRFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/ALRMR_MSK: bit_size: 1 variants: @@ -661,7 +637,7 @@ enum/ALRMR_WDSEL: - name: WeekDay description: "DU[3:0] represents the week day. DT[1:0] is don’t care" value: 1 -enum/ALRWFR: +enum/ALRWF: bit_size: 1 variants: - name: UpdateNotAllowed @@ -727,7 +703,7 @@ enum/INIT: - name: InitMode description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." value: 1 -enum/INITFR: +enum/INITF: bit_size: 1 variants: - name: NotAllowed @@ -736,7 +712,7 @@ enum/INITFR: - name: Allowed description: Calendar registers update is allowed value: 1 -enum/INITSR: +enum/INITS: bit_size: 1 variants: - name: NotInitalized @@ -769,7 +745,7 @@ enum/POL: - name: Low description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" value: 1 -enum/RECALPFR: +enum/RECALPF: bit_size: 1 variants: - name: Pending @@ -784,21 +760,6 @@ enum/REFCKON: - name: Enabled description: RTC_REFIN detection enabled value: 1 -enum/RSFR: - bit_size: 1 - variants: - - name: NotSynced - description: Calendar shadow registers not yet synchronized - value: 0 - - name: Synced - description: Calendar shadow registers synchronized - value: 1 -enum/RSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/TAMPFLT: bit_size: 2 variants: @@ -814,12 +775,6 @@ enum/TAMPFLT: - name: Samples8 description: Tamper event is activated after 8 consecutive samples at the active level value: 3 -enum/TAMPFR: - bit_size: 1 - variants: - - name: Tampered - description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input - value: 1 enum/TAMPFREQ: bit_size: 3 variants: @@ -847,12 +802,6 @@ enum/TAMPFREQ: - name: Div256 description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) value: 7 -enum/TAMPFW: - bit_size: 1 - variants: - - name: Clear - description: Flag cleared by software writing 0 - value: 0 enum/TAMPPRCH: bit_size: 2 variants: @@ -895,30 +844,6 @@ enum/TSEDGE: - name: FallingEdge description: RTC_TS input falling edge generates a time-stamp event value: 1 -enum/TSFR: - bit_size: 1 - variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 -enum/TSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/TSOVFR: - bit_size: 1 - variants: - - name: Overflow - description: This flag is set by hardware when a timestamp event occurs while TSF is already set - value: 1 -enum/TSOVFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 enum/WUCKSEL: bit_size: 3 variants: @@ -940,19 +865,7 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTFR: - bit_size: 1 - variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 -enum/WUTFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/WUTWFR: +enum/WUTWF: bit_size: 1 variants: - name: UpdateNotAllowed diff --git a/data/registers/rtc_v3.yaml b/data/registers/rtc_v3.yaml index 39fb0f4..a5a6128 100644 --- a/data/registers/rtc_v3.yaml +++ b/data/registers/rtc_v3.yaml @@ -367,7 +367,7 @@ fieldset/ICSR: description: Wakeup timer write flag bit_offset: 2 bit_size: 1 - enum_read: WUTWFR + enum: WUTWF - name: SHPF description: Shift operation pending bit_offset: 3 @@ -376,18 +376,16 @@ fieldset/ICSR: description: Initialization status flag bit_offset: 4 bit_size: 1 - enum_read: INITSR + enum: INITS - name: RSF description: Registers synchronization flag bit_offset: 5 bit_size: 1 - enum_read: RSFR - enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 - enum_read: INITFR + enum: INITF - name: INIT description: Initialization mode bit_offset: 7 @@ -407,7 +405,7 @@ fieldset/ICSR: description: Recalibration pending Flag bit_offset: 16 bit_size: 1 - enum_read: RECALPFR + enum: RECALPF fieldset/MISR: description: Masked interrupt status register fields: @@ -810,7 +808,7 @@ enum/INIT: - name: InitMode description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." value: 1 -enum/INITFR: +enum/INITF: bit_size: 1 variants: - name: NotAllowed @@ -819,7 +817,7 @@ enum/INITFR: - name: Allowed description: Calendar registers update is allowed value: 1 -enum/INITSR: +enum/INITS: bit_size: 1 variants: - name: NotInitalized @@ -885,7 +883,7 @@ enum/POL: - name: Low description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" value: 1 -enum/RECALPFR: +enum/RECALPF: bit_size: 1 variants: - name: Pending @@ -900,45 +898,12 @@ enum/REFCKON: - name: Enabled description: RTC_REFIN detection enabled value: 1 -enum/RSFR: - bit_size: 1 - variants: - - name: NotSynced - description: Calendar shadow registers not yet synchronized - value: 0 - - name: Synced - description: Calendar shadow registers synchronized - value: 1 -enum/RSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/SHPFR: - bit_size: 1 - variants: - - name: NoShiftPending - description: No shift operation is pending - value: 0 - - name: ShiftPending - description: A shift operation is pending - value: 1 enum/SSRUF: bit_size: 1 variants: - name: Underflow description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 value: 1 -enum/SSRUIE: - bit_size: 1 - variants: - - name: Disabled - description: SSR underflow interrupt disabled - value: 0 - - name: Enabled - description: SSR underflow interrupt enabled - value: 1 enum/SSRUMF: bit_size: 1 variants: @@ -1029,7 +994,7 @@ enum/WUTMF: - name: Zero description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 value: 1 -enum/WUTWFR: +enum/WUTWF: bit_size: 1 variants: - name: UpdateNotAllowed diff --git a/data/registers/rtc_v3u5.yaml b/data/registers/rtc_v3u5.yaml index 8d97151..339cb2e 100644 --- a/data/registers/rtc_v3u5.yaml +++ b/data/registers/rtc_v3u5.yaml @@ -387,7 +387,7 @@ fieldset/ICSR: description: Wakeup timer write flag bit_offset: 2 bit_size: 1 - enum_read: WUTWFR + enum: WUTWF - name: SHPF description: Shift operation pending bit_offset: 3 @@ -396,18 +396,16 @@ fieldset/ICSR: description: Initialization status flag bit_offset: 4 bit_size: 1 - enum_read: INITSR + enum: INITS - name: RSF description: Registers synchronization flag bit_offset: 5 bit_size: 1 - enum_read: RSFR - enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 - enum_read: INITFR + enum: INITF - name: INIT description: Initialization mode bit_offset: 7 @@ -427,7 +425,7 @@ fieldset/ICSR: description: Recalibration pending Flag bit_offset: 16 bit_size: 1 - enum_read: RECALPFR + enum: RECALPF fieldset/MISR: description: Masked interrupt status register fields: @@ -923,7 +921,7 @@ enum/INIT: - name: InitMode description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." value: 1 -enum/INITFR: +enum/INITF: bit_size: 1 variants: - name: NotAllowed @@ -932,7 +930,7 @@ enum/INITFR: - name: Allowed description: Calendar registers update is allowed value: 1 -enum/INITSR: +enum/INITS: bit_size: 1 variants: - name: NotInitalized @@ -998,7 +996,7 @@ enum/POL: - name: Low description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" value: 1 -enum/RECALPFR: +enum/RECALPF: bit_size: 1 variants: - name: Pending @@ -1013,45 +1011,12 @@ enum/REFCKON: - name: Enabled description: RTC_REFIN detection enabled value: 1 -enum/RSFR: - bit_size: 1 - variants: - - name: NotSynced - description: Calendar shadow registers not yet synchronized - value: 0 - - name: Synced - description: Calendar shadow registers synchronized - value: 1 -enum/RSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/SHPFR: - bit_size: 1 - variants: - - name: NoShiftPending - description: No shift operation is pending - value: 0 - - name: ShiftPending - description: A shift operation is pending - value: 1 enum/SSRUF: bit_size: 1 variants: - name: Underflow description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 value: 1 -enum/SSRUIE: - bit_size: 1 - variants: - - name: Disabled - description: SSR underflow interrupt disabled - value: 0 - - name: Enabled - description: SSR underflow interrupt enabled - value: 1 enum/SSRUMF: bit_size: 1 variants: @@ -1142,7 +1107,7 @@ enum/WUTMF: - name: Zero description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 value: 1 -enum/WUTWFR: +enum/WUTWF: bit_size: 1 variants: - name: UpdateNotAllowed diff --git a/data/registers/sai_v1.yaml b/data/registers/sai_v1.yaml index 73ced5b..7e58c5e 100644 --- a/data/registers/sai_v1.yaml +++ b/data/registers/sai_v1.yaml @@ -264,43 +264,43 @@ fieldset/SR: description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." bit_offset: 0 bit_size: 1 - enum_read: OVRUDRR + enum: OVRUDR - name: MUTEDET description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. bit_offset: 1 bit_size: 1 - enum_read: MUTEDETR + enum: MUTEDET - name: WCKCFG description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." bit_offset: 2 bit_size: 1 - enum_read: WCKCFGR + enum: WCKCFG - name: FREQ description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." bit_offset: 3 bit_size: 1 - enum_read: FREQR + enum: FREQ - name: CNRDY description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. bit_offset: 4 bit_size: 1 - enum_read: CNRDYR + enum: CNRDY - name: AFSDET description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. bit_offset: 5 bit_size: 1 - enum_read: AFSDETR + enum: AFSDET - name: LFSDET description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register bit_offset: 6 bit_size: 1 - enum_read: LFSDETR + enum: LFSDET - name: FLVL description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" bit_offset: 16 bit_size: 3 - enum_read: FLVLR -enum/AFSDETR: + enum: FLVL +enum/AFSDET: bit_size: 1 variants: - name: NoError @@ -318,7 +318,7 @@ enum/CKSTR: - name: RisingEdge description: Data strobing edge is rising edge of SCK value: 1 -enum/CNRDYR: +enum/CNRDY: bit_size: 1 variants: - name: Ready @@ -378,7 +378,7 @@ enum/FFLUSH: - name: Flush description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared value: 1 -enum/FLVLR: +enum/FLVL: bit_size: 3 variants: - name: Empty @@ -399,7 +399,7 @@ enum/FLVLR: - name: Full description: FIFO full value: 5 -enum/FREQR: +enum/FREQ: bit_size: 1 variants: - name: NoRequest @@ -444,7 +444,7 @@ enum/FTH: - name: Full description: FIFO full value: 4 -enum/LFSDETR: +enum/LFSDET: bit_size: 1 variants: - name: NoError @@ -486,7 +486,7 @@ enum/MONO: - name: Mono description: Mono mode value: 1 -enum/MUTEDETR: +enum/MUTEDET: bit_size: 1 variants: - name: NoMute @@ -522,7 +522,7 @@ enum/OUTDRIV: - name: Immediately description: Audio block output driven immediately after the setting of this bit value: 1 -enum/OVRUDRR: +enum/OVRUDR: bit_size: 1 variants: - name: NoError @@ -576,7 +576,7 @@ enum/SYNCEN: - name: External description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode value: 2 -enum/WCKCFGR: +enum/WCKCFG: bit_size: 1 variants: - name: Correct diff --git a/data/registers/sai_v2.yaml b/data/registers/sai_v2.yaml index fa2bd78..f16c640 100644 --- a/data/registers/sai_v2.yaml +++ b/data/registers/sai_v2.yaml @@ -279,43 +279,43 @@ fieldset/SR: description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." bit_offset: 0 bit_size: 1 - enum_read: OVRUDRR + enum: OVRUDR - name: MUTEDET description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. bit_offset: 1 bit_size: 1 - enum_read: MUTEDETR + enum: MUTEDET - name: WCKCFG description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." bit_offset: 2 bit_size: 1 - enum_read: WCKCFGR + enum: WCKCFG - name: FREQ description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." bit_offset: 3 bit_size: 1 - enum_read: FREQR + enum: FREQ - name: CNRDY description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. bit_offset: 4 bit_size: 1 - enum_read: CNRDYR + enum: CNRDY - name: AFSDET description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. bit_offset: 5 bit_size: 1 - enum_read: AFSDETR + enum: AFSDET - name: LFSDET description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register bit_offset: 6 bit_size: 1 - enum_read: LFSDETR + enum: LFSDET - name: FLVL description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" bit_offset: 16 bit_size: 3 - enum_read: FLVLR -enum/AFSDETR: + enum: FLVL +enum/AFSDET: bit_size: 1 variants: - name: NoError @@ -333,7 +333,7 @@ enum/CKSTR: - name: RisingEdge description: Data strobing edge is rising edge of SCK value: 1 -enum/CNRDYR: +enum/CNRDY: bit_size: 1 variants: - name: Ready @@ -393,7 +393,7 @@ enum/FFLUSH: - name: Flush description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared value: 1 -enum/FLVLR: +enum/FLVL: bit_size: 3 variants: - name: Empty @@ -414,7 +414,7 @@ enum/FLVLR: - name: Full description: FIFO full value: 5 -enum/FREQR: +enum/FREQ: bit_size: 1 variants: - name: NoRequest @@ -459,7 +459,7 @@ enum/FTH: - name: Full description: FIFO full value: 4 -enum/LFSDETR: +enum/LFSDET: bit_size: 1 variants: - name: NoError @@ -501,7 +501,7 @@ enum/MONO: - name: Mono description: Mono mode value: 1 -enum/MUTEDETR: +enum/MUTEDET: bit_size: 1 variants: - name: NoMute @@ -537,7 +537,7 @@ enum/OUTDRIV: - name: Immediately description: Audio block output driven immediately after the setting of this bit value: 1 -enum/OVRUDRR: +enum/OVRUDR: bit_size: 1 variants: - name: NoError @@ -591,7 +591,7 @@ enum/SYNCEN: - name: External description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode value: 2 -enum/WCKCFGR: +enum/WCKCFG: bit_size: 1 variants: - name: Correct diff --git a/data/registers/sai_v3.yaml b/data/registers/sai_v3.yaml index cba0707..d17db2f 100644 --- a/data/registers/sai_v3.yaml +++ b/data/registers/sai_v3.yaml @@ -161,7 +161,6 @@ fieldset/CR2: description: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. bit_offset: 3 bit_size: 1 - enum_write: FFLUSH - name: TRIS description: "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details." bit_offset: 4 @@ -353,43 +352,43 @@ fieldset/SR: description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." bit_offset: 0 bit_size: 1 - enum_read: OVRUDRR + enum: OVRUDR - name: MUTEDET description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. bit_offset: 1 bit_size: 1 - enum_read: MUTEDETR + enum: MUTEDET - name: WCKCFG description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." bit_offset: 2 bit_size: 1 - enum_read: WCKCFGR + enum: WCKCFG - name: FREQ description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." bit_offset: 3 bit_size: 1 - enum_read: FREQR + enum: FREQ - name: CNRDY description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. bit_offset: 4 bit_size: 1 - enum_read: CNRDYR + enum: CNRDY - name: AFSDET description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. bit_offset: 5 bit_size: 1 - enum_read: AFSDETR + enum: AFSDET - name: LFSDET description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register bit_offset: 6 bit_size: 1 - enum_read: LFSDETR + enum: LFSDET - name: FLVL description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" bit_offset: 16 bit_size: 3 - enum_read: FLVLR -enum/AFSDETR: + enum: FLVL +enum/AFSDET: bit_size: 1 variants: - name: NoError @@ -407,7 +406,7 @@ enum/CKSTR: - name: RisingEdge description: Data strobing edge is rising edge of SCK value: 1 -enum/CNRDYR: +enum/CNRDY: bit_size: 1 variants: - name: Ready @@ -458,16 +457,7 @@ enum/DS: - name: Bit32 description: 32 bits value: 7 -enum/FFLUSH: - bit_size: 1 - variants: - - name: NoFlush - description: No FIFO flush - value: 0 - - name: Flush - description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared - value: 1 -enum/FLVLR: +enum/FLVL: bit_size: 3 variants: - name: Empty @@ -488,7 +478,7 @@ enum/FLVLR: - name: Full description: FIFO full value: 5 -enum/FREQR: +enum/FREQ: bit_size: 1 variants: - name: NoRequest @@ -533,7 +523,7 @@ enum/FTH: - name: Full description: FIFO full value: 4 -enum/LFSDETR: +enum/LFSDET: bit_size: 1 variants: - name: NoError @@ -575,7 +565,7 @@ enum/MONO: - name: Mono description: Mono mode value: 1 -enum/MUTEDETR: +enum/MUTEDET: bit_size: 1 variants: - name: NoMute @@ -611,7 +601,7 @@ enum/OUTDRIV: - name: Immediately description: Audio block output driven immediately after the setting of this bit value: 1 -enum/OVRUDRR: +enum/OVRUDR: bit_size: 1 variants: - name: NoError @@ -665,7 +655,7 @@ enum/SYNCEN: - name: External description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode value: 2 -enum/WCKCFGR: +enum/WCKCFG: bit_size: 1 variants: - name: Correct diff --git a/data/registers/sai_v4.yaml b/data/registers/sai_v4.yaml index bc21bad..887eb1b 100644 --- a/data/registers/sai_v4.yaml +++ b/data/registers/sai_v4.yaml @@ -165,7 +165,6 @@ fieldset/CR2: description: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. bit_offset: 3 bit_size: 1 - enum_write: FFLUSH - name: TRIS description: "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details." bit_offset: 4 @@ -357,43 +356,43 @@ fieldset/SR: description: "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." bit_offset: 0 bit_size: 1 - enum_read: OVRUDRR + enum: OVRUDR - name: MUTEDET description: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. bit_offset: 1 bit_size: 1 - enum_read: MUTEDETR + enum: MUTEDET - name: WCKCFG description: "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." bit_offset: 2 bit_size: 1 - enum_read: WCKCFGR + enum: WCKCFG - name: FREQ description: "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." bit_offset: 3 bit_size: 1 - enum_read: FREQR + enum: FREQ - name: CNRDY description: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. bit_offset: 4 bit_size: 1 - enum_read: CNRDYR + enum: CNRDY - name: AFSDET description: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. bit_offset: 5 bit_size: 1 - enum_read: AFSDETR + enum: AFSDET - name: LFSDET description: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register bit_offset: 6 bit_size: 1 - enum_read: LFSDETR + enum: LFSDET - name: FLVL description: "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" bit_offset: 16 bit_size: 3 - enum_read: FLVLR -enum/AFSDETR: + enum: FLVL +enum/AFSDET: bit_size: 1 variants: - name: NoError @@ -411,7 +410,7 @@ enum/CKSTR: - name: RisingEdge description: Data strobing edge is rising edge of SCK value: 1 -enum/CNRDYR: +enum/CNRDY: bit_size: 1 variants: - name: Ready @@ -462,16 +461,7 @@ enum/DS: - name: Bit32 description: 32 bits value: 7 -enum/FFLUSH: - bit_size: 1 - variants: - - name: NoFlush - description: No FIFO flush - value: 0 - - name: Flush - description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared - value: 1 -enum/FLVLR: +enum/FLVL: bit_size: 3 variants: - name: Empty @@ -492,7 +482,7 @@ enum/FLVLR: - name: Full description: FIFO full value: 5 -enum/FREQR: +enum/FREQ: bit_size: 1 variants: - name: NoRequest @@ -537,7 +527,7 @@ enum/FTH: - name: Full description: FIFO full value: 4 -enum/LFSDETR: +enum/LFSDET: bit_size: 1 variants: - name: NoError @@ -579,7 +569,7 @@ enum/MONO: - name: Mono description: Mono mode value: 1 -enum/MUTEDETR: +enum/MUTEDET: bit_size: 1 variants: - name: NoMute @@ -615,7 +605,7 @@ enum/OUTDRIV: - name: Immediately description: Audio block output driven immediately after the setting of this bit value: 1 -enum/OVRUDRR: +enum/OVRUDR: bit_size: 1 variants: - name: NoError @@ -669,7 +659,7 @@ enum/SYNCEN: - name: External description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode value: 2 -enum/WCKCFGR: +enum/WCKCFG: bit_size: 1 variants: - name: Correct diff --git a/data/registers/spi_v2.yaml b/data/registers/spi_v2.yaml index 55cb420..b11a3f9 100644 --- a/data/registers/spi_v2.yaml +++ b/data/registers/spi_v2.yaml @@ -270,7 +270,7 @@ fieldset/SR: description: Underrun flag bit_offset: 3 bit_size: 1 - enum_read: UDRR + enum: UDR - name: CRCERR description: CRC error flag bit_offset: 4 @@ -291,17 +291,17 @@ fieldset/SR: description: frame format error bit_offset: 8 bit_size: 1 - enum_read: FRER + enum: FRE - name: FRLVL description: FIFO reception level bit_offset: 9 bit_size: 2 - enum_read: FRLVLR + enum: FRLVL - name: FTLVL description: FIFO Transmission Level bit_offset: 11 bit_size: 2 - enum_read: FTLVLR + enum: FTLVL fieldset/TXCRCR: description: TX CRC register fields: @@ -471,7 +471,7 @@ enum/DS: - name: SixteenBit description: 16-bit value: 15 -enum/FRER: +enum/FRE: bit_size: 1 variants: - name: NoError @@ -489,7 +489,7 @@ enum/FRF: - name: TI description: SPI TI mode value: 1 -enum/FRLVLR: +enum/FRLVL: bit_size: 2 variants: - name: Empty @@ -513,7 +513,7 @@ enum/FRXTH: - name: Quarter description: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) value: 1 -enum/FTLVLR: +enum/FTLVL: bit_size: 2 variants: - name: Empty @@ -630,15 +630,6 @@ enum/ODD: - name: Odd description: Real divider value is (I2SDIV * 2) + 1 value: 1 -enum/OVRR: - bit_size: 1 - variants: - - name: NoOverrun - description: No overrun occurred - value: 0 - - name: Overrun - description: Overrun occurred - value: 1 enum/PCMSYNC: bit_size: 1 variants: @@ -657,7 +648,7 @@ enum/RXONLY: - name: OutputDisabled description: Output disabled (Receive-only mode) value: 1 -enum/UDRR: +enum/UDR: bit_size: 1 variants: - name: NoUnderrun diff --git a/data/registers/spi_v3.yaml b/data/registers/spi_v3.yaml index 7a89cdb..a1336e1 100644 --- a/data/registers/spi_v3.yaml +++ b/data/registers/spi_v3.yaml @@ -475,27 +475,6 @@ enum/CRC_: - name: Enabled description: Full size (33/17 bit) CRC polynomial is used value: 1 -enum/DATFMT: - bit_size: 1 - variants: - - name: RightAligned - description: The data inside RXDR and TXDR are right aligned - value: 0 - - name: LeftAligned - description: The data inside RXDR and TXDR are left aligned - value: 1 -enum/DATLEN: - bit_size: 2 - variants: - - name: Bits16 - description: 16 bit data length - value: 0 - - name: Bits24 - description: 24 bit data length - value: 1 - - name: Bits32 - description: 32 bit data length - value: 2 enum/FTHLV: bit_size: 4 variants: diff --git a/data/registers/spi_v4.yaml b/data/registers/spi_v4.yaml index bac2a9c..89ef354 100644 --- a/data/registers/spi_v4.yaml +++ b/data/registers/spi_v4.yaml @@ -468,27 +468,6 @@ enum/CRC_: - name: Enabled description: Full size (33/17 bit) CRC polynomial is used value: 1 -enum/DATFMT: - bit_size: 1 - variants: - - name: RightAligned - description: The data inside RXDR and TXDR are right aligned - value: 0 - - name: LeftAligned - description: The data inside RXDR and TXDR are left aligned - value: 1 -enum/DATLEN: - bit_size: 2 - variants: - - name: Bits16 - description: 16 bit data length - value: 0 - - name: Bits24 - description: 24 bit data length - value: 1 - - name: Bits32 - description: 32 bit data length - value: 2 enum/FTHLV: bit_size: 4 variants: diff --git a/data/registers/spi_v5.yaml b/data/registers/spi_v5.yaml index b7f7092..d5961e6 100644 --- a/data/registers/spi_v5.yaml +++ b/data/registers/spi_v5.yaml @@ -486,27 +486,6 @@ enum/CRC_: - name: Enabled description: Full size (33/17 bit) CRC polynomial is used value: 1 -enum/DATFMT: - bit_size: 1 - variants: - - name: RightAligned - description: The data inside RXDR and TXDR are right aligned - value: 0 - - name: LeftAligned - description: The data inside RXDR and TXDR are left aligned - value: 1 -enum/DATLEN: - bit_size: 2 - variants: - - name: Bits16 - description: 16 bit data length - value: 0 - - name: Bits24 - description: 24 bit data length - value: 1 - - name: Bits32 - description: 32 bit data length - value: 2 enum/FTHLV: bit_size: 4 variants: diff --git a/data/registers/syscfg_f0.yaml b/data/registers/syscfg_f0.yaml index ec2b981..91caf2e 100644 --- a/data/registers/syscfg_f0.yaml +++ b/data/registers/syscfg_f0.yaml @@ -167,8 +167,6 @@ fieldset/CFGR2: description: SRAM parity flag bit_offset: 8 bit_size: 1 - enum_read: SRAM_PEFR - enum_write: SRAM_PEFW fieldset/EXTICR: description: external interrupt configuration register 1 fields: @@ -341,21 +339,6 @@ enum/SRAM_PARITY_LOCK: - name: Connected description: SRAM parity error connected to TIM1/15/16/17 Break input value: 1 -enum/SRAM_PEFR: - bit_size: 1 - variants: - - name: NoParityError - description: No SRAM parity error detected - value: 0 - - name: ParityErrorDetected - description: SRAM parity error detected - value: 1 -enum/SRAM_PEFW: - bit_size: 1 - variants: - - name: Clear - description: Clear SRAM parity error flag - value: 1 enum/TIM16_DMA_RMP: bit_size: 1 variants: diff --git a/data/registers/syscfg_f3.yaml b/data/registers/syscfg_f3.yaml index 94dc85f..a683666 100644 --- a/data/registers/syscfg_f3.yaml +++ b/data/registers/syscfg_f3.yaml @@ -209,8 +209,6 @@ fieldset/CFGR2: description: SRAM parity flag bit_offset: 8 bit_size: 1 - enum_read: SRAM_PEFR - enum_write: SRAM_PEFW fieldset/CFGR3: description: configuration register 3 fields: @@ -562,27 +560,6 @@ enum/BYP_ADDR_PAR: - name: Bypass description: The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated value: 1 -enum/CFGR1_ADC2_DMA_RMP: - bit_size: 1 - variants: - - name: NotRemapped - description: ADC24 DMA requests mapped on DMA2 channels 1 and 2 - value: 0 - - name: Remapped - description: ADC24 DMA requests mapped on DMA2 channels 3 and 4 - value: 1 -enum/CFGR3_ADC2_DMA_RMP: - bit_size: 2 - variants: - - name: MapDma2 - description: ADC2 mapped on DMA2 - value: 0 - - name: MapDma1Ch2 - description: ADC2 mapped on DMA1 channel 2 - value: 2 - - name: MapDma1Ch4 - description: ADC2 mapped on DMA1 channel 4 - value: 3 enum/DAC1_TRIG3_RMP: bit_size: 1 variants: @@ -640,318 +617,6 @@ enum/ENCODER_MODE: - name: MapTim3Tim15 description: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively value: 2 -enum/EXTI0: - bit_size: 4 - variants: - - name: PA0 - description: Select PA0 as the source input for the EXTI0 external interrupt - value: 0 - - name: PB0 - description: Select PB0 as the source input for the EXTI0 external interrupt - value: 1 - - name: PC0 - description: Select PC0 as the source input for the EXTI0 external interrupt - value: 2 - - name: PD0 - description: Select PD0 as the source input for the EXTI0 external interrupt - value: 3 - - name: PE0 - description: Select PE0 as the source input for the EXTI0 external interrupt - value: 4 - - name: PF0 - description: Select PF0 as the source input for the EXTI0 external interrupt - value: 5 -enum/EXTI1: - bit_size: 4 - variants: - - name: PA1 - description: Select PA1 as the source input for the EXTI1 external interrupt - value: 0 - - name: PB1 - description: Select PB1 as the source input for the EXTI1 external interrupt - value: 1 - - name: PC1 - description: Select PC1 as the source input for the EXTI1 external interrupt - value: 2 - - name: PD1 - description: Select PD1 as the source input for the EXTI1 external interrupt - value: 3 - - name: PE1 - description: Select PE1 as the source input for the EXTI1 external interrupt - value: 4 - - name: PF1 - description: Select PF1 as the source input for the EXTI1 external interrupt - value: 5 -enum/EXTI10: - bit_size: 4 - variants: - - name: PA10 - description: Select PA10 as the source input for the EXTI10 external interrupt - value: 0 - - name: PB10 - description: Select PB10 as the source input for the EXTI10 external interrupt - value: 1 - - name: PC10 - description: Select PC10 as the source input for the EXTI10 external interrupt - value: 2 - - name: PD10 - description: Select PD10 as the source input for the EXTI10 external interrupt - value: 3 - - name: PE10 - description: Select PE10 as the source input for the EXTI10 external interrupt - value: 4 - - name: PF10 - description: Select PF10 as the source input for the EXTI10 external interrupt - value: 5 -enum/EXTI11: - bit_size: 4 - variants: - - name: PA11 - description: Select PA11 as the source input for the EXTI11 external interrupt - value: 0 - - name: PB11 - description: Select PB11 as the source input for the EXTI11 external interrupt - value: 1 - - name: PC11 - description: Select PC11 as the source input for the EXTI11 external interrupt - value: 2 - - name: PD11 - description: Select PD11 as the source input for the EXTI11 external interrupt - value: 3 - - name: PE11 - description: Select PE11 as the source input for the EXTI11 external interrupt - value: 4 -enum/EXTI12: - bit_size: 4 - variants: - - name: PA12 - description: Select PA12 as the source input for the EXTI12 external interrupt - value: 0 - - name: PB12 - description: Select PB12 as the source input for the EXTI12 external interrupt - value: 1 - - name: PC12 - description: Select PC12 as the source input for the EXTI12 external interrupt - value: 2 - - name: PD12 - description: Select PD12 as the source input for the EXTI12 external interrupt - value: 3 - - name: PE12 - description: Select PE12 as the source input for the EXTI12 external interrupt - value: 4 -enum/EXTI13: - bit_size: 4 - variants: - - name: PA13 - description: Select PA13 as the source input for the EXTI13 external interrupt - value: 0 - - name: PB13 - description: Select PB13 as the source input for the EXTI13 external interrupt - value: 1 - - name: PC13 - description: Select PC13 as the source input for the EXTI13 external interrupt - value: 2 - - name: PD13 - description: Select PD13 as the source input for the EXTI13 external interrupt - value: 3 - - name: PE13 - description: Select PE13 as the source input for the EXTI13 external interrupt - value: 4 -enum/EXTI14: - bit_size: 4 - variants: - - name: PA14 - description: Select PA14 as the source input for the EXTI14 external interrupt - value: 0 - - name: PB14 - description: Select PB14 as the source input for the EXTI14 external interrupt - value: 1 - - name: PC14 - description: Select PC14 as the source input for the EXTI14 external interrupt - value: 2 - - name: PD14 - description: Select PD14 as the source input for the EXTI14 external interrupt - value: 3 - - name: PE14 - description: Select PE14 as the source input for the EXTI14 external interrupt - value: 4 -enum/EXTI15: - bit_size: 4 - variants: - - name: PA15 - description: Select PA15 as the source input for the EXTI15 external interrupt - value: 0 - - name: PB15 - description: Select PB15 as the source input for the EXTI15 external interrupt - value: 1 - - name: PC15 - description: Select PC15 as the source input for the EXTI15 external interrupt - value: 2 - - name: PD15 - description: Select PD15 as the source input for the EXTI15 external interrupt - value: 3 - - name: PE15 - description: Select PE15 as the source input for the EXTI15 external interrupt - value: 4 -enum/EXTI2: - bit_size: 4 - variants: - - name: PA2 - description: Select PA2 as the source input for the EXTI2 external interrupt - value: 0 - - name: PB2 - description: Select PB2 as the source input for the EXTI2 external interrupt - value: 1 - - name: PC2 - description: Select PC2 as the source input for the EXTI2 external interrupt - value: 2 - - name: PD2 - description: Select PD2 as the source input for the EXTI2 external interrupt - value: 3 - - name: PE2 - description: Select PE2 as the source input for the EXTI2 external interrupt - value: 4 - - name: PF2 - description: Select PF2 as the source input for the EXTI2 external interrupt - value: 5 -enum/EXTI3: - bit_size: 4 - variants: - - name: PA3 - description: Select PA3 as the source input for the EXTI3 external interrupt - value: 0 - - name: PB3 - description: Select PB3 as the source input for the EXTI3 external interrupt - value: 1 - - name: PC3 - description: Select PC3 as the source input for the EXTI3 external interrupt - value: 2 - - name: PD3 - description: Select PD3 as the source input for the EXTI3 external interrupt - value: 3 - - name: PE3 - description: Select PE3 as the source input for the EXTI3 external interrupt - value: 4 -enum/EXTI4: - bit_size: 4 - variants: - - name: PA4 - description: Select PA4 as the source input for the EXTI4 external interrupt - value: 0 - - name: PB4 - description: Select PB4 as the source input for the EXTI4 external interrupt - value: 1 - - name: PC4 - description: Select PC4 as the source input for the EXTI4 external interrupt - value: 2 - - name: PD4 - description: Select PD4 as the source input for the EXTI4 external interrupt - value: 3 - - name: PE4 - description: Select PE4 as the source input for the EXTI4 external interrupt - value: 4 - - name: PF4 - description: Select PF4 as the source input for the EXTI4 external interrupt - value: 5 -enum/EXTI5: - bit_size: 4 - variants: - - name: PA5 - description: Select PA5 as the source input for the EXTI5 external interrupt - value: 0 - - name: PB5 - description: Select PB5 as the source input for the EXTI5 external interrupt - value: 1 - - name: PC5 - description: Select PC5 as the source input for the EXTI5 external interrupt - value: 2 - - name: PD5 - description: Select PD5 as the source input for the EXTI5 external interrupt - value: 3 - - name: PE5 - description: Select PE5 as the source input for the EXTI5 external interrupt - value: 4 - - name: PF5 - description: Select PF5 as the source input for the EXTI5 external interrupt - value: 5 -enum/EXTI6: - bit_size: 4 - variants: - - name: PA6 - description: Select PA6 as the source input for the EXTI6 external interrupt - value: 0 - - name: PB6 - description: Select PB6 as the source input for the EXTI6 external interrupt - value: 1 - - name: PC6 - description: Select PC6 as the source input for the EXTI6 external interrupt - value: 2 - - name: PD6 - description: Select PD6 as the source input for the EXTI6 external interrupt - value: 3 - - name: PE6 - description: Select PE6 as the source input for the EXTI6 external interrupt - value: 4 - - name: PF6 - description: Select PF6 as the source input for the EXTI6 external interrupt - value: 5 -enum/EXTI7: - bit_size: 4 - variants: - - name: PA7 - description: Select PA7 as the source input for the EXTI7 external interrupt - value: 0 - - name: PB7 - description: Select PB7 as the source input for the EXTI7 external interrupt - value: 1 - - name: PC7 - description: Select PC7 as the source input for the EXTI7 external interrupt - value: 2 - - name: PD7 - description: Select PD7 as the source input for the EXTI7 external interrupt - value: 3 - - name: PE7 - description: Select PE7 as the source input for the EXTI7 external interrupt - value: 4 -enum/EXTI8: - bit_size: 4 - variants: - - name: PA8 - description: Select PA8 as the source input for the EXTI8 external interrupt - value: 0 - - name: PB8 - description: Select PB8 as the source input for the EXTI8 external interrupt - value: 1 - - name: PC8 - description: Select PC8 as the source input for the EXTI8 external interrupt - value: 2 - - name: PD8 - description: Select PD8 as the source input for the EXTI8 external interrupt - value: 3 - - name: PE8 - description: Select PE8 as the source input for the EXTI8 external interrupt - value: 4 -enum/EXTI9: - bit_size: 4 - variants: - - name: PA9 - description: Select PA9 as the source input for the EXTI9 external interrupt - value: 0 - - name: PB9 - description: Select PB9 as the source input for the EXTI9 external interrupt - value: 1 - - name: PC9 - description: Select PC9 as the source input for the EXTI9 external interrupt - value: 2 - - name: PD9 - description: Select PD9 as the source input for the EXTI9 external interrupt - value: 3 - - name: PE9 - description: Select PE9 as the source input for the EXTI9 external interrupt - value: 4 - - name: PF9 - description: Select PF9 as the source input for the EXTI9 external interrupt - value: 5 enum/FPU_IE0: bit_size: 1 variants: @@ -1168,21 +833,6 @@ enum/SRAM_PARITY_LOCK: - name: Connected description: SRAM parity error signal connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs value: 1 -enum/SRAM_PEFR: - bit_size: 1 - variants: - - name: NoParityError - description: No SRAM parity error detected - value: 0 - - name: ParityErrorDetected - description: SRAM parity error detected - value: 1 -enum/SRAM_PEFW: - bit_size: 1 - variants: - - name: Clear - description: Clear SRAM parity error flag - value: 1 enum/TIM16_DMA_RMP: bit_size: 1 variants: diff --git a/data/registers/wwdg_v1.yaml b/data/registers/wwdg_v1.yaml index 9b55c3b..b1d77c2 100644 --- a/data/registers/wwdg_v1.yaml +++ b/data/registers/wwdg_v1.yaml @@ -30,7 +30,6 @@ fieldset/CFR: description: Early wakeup interrupt bit_offset: 9 bit_size: 1 - enum_write: EWIW fieldset/CR: description: Control register fields: @@ -50,29 +49,6 @@ fieldset/SR: description: Early wakeup interrupt flag bit_offset: 0 bit_size: 1 - enum_read: EWIFR - enum_write: EWIFW -enum/EWIFR: - bit_size: 1 - variants: - - name: Finished - description: The EWI Interrupt Service Routine has been serviced - value: 0 - - name: Pending - description: The EWI Interrupt Service Routine has been triggered - value: 1 -enum/EWIFW: - bit_size: 1 - variants: - - name: Finished - description: The EWI Interrupt Service Routine has been serviced - value: 0 -enum/EWIW: - bit_size: 1 - variants: - - name: Enable - description: interrupt occurs whenever the counter reaches the value 0x40 - value: 1 enum/WDGA: bit_size: 1 variants: