862 lines
21 KiB
YAML
862 lines
21 KiB
YAML
---
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block/RTC:
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description: Real-time clock
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items:
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- name: TR
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description: Time register
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byte_offset: 0
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fieldset: TR
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- name: DR
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description: Date register
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byte_offset: 4
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fieldset: DR
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- name: CR
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description: Control register
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byte_offset: 8
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fieldset: CR
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- name: ISR
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description: Initialization and status register
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byte_offset: 12
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fieldset: ISR
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- name: PRER
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description: Prescaler register
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byte_offset: 16
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fieldset: PRER
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- name: WUTR
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description: Wakeup timer register
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byte_offset: 20
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fieldset: WUTR
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- name: CALIBR
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description: Calibration register
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byte_offset: 24
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fieldset: CALIBR
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- name: ALRMR
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description: Alarm register
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array:
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len: 2
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stride: 4
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byte_offset: 28
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fieldset: ALRMR
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- name: WPR
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description: Write protection register
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byte_offset: 36
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access: Write
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fieldset: WPR
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- name: SSR
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description: Sub second register
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byte_offset: 40
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access: Read
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fieldset: SSR
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- name: SHIFTR
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description: Shift control register
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byte_offset: 44
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access: Write
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fieldset: SHIFTR
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- name: TSTR
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description: Timestamp time register
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byte_offset: 48
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access: Read
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fieldset: TSTR
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- name: TSDR
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description: Timestamp date register
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byte_offset: 52
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access: Read
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fieldset: TSDR
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- name: TSSSR
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description: Timestamp sub second register
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byte_offset: 56
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access: Read
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fieldset: TSSSR
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- name: CALR
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description: Calibration register
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byte_offset: 60
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fieldset: CALR
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- name: TAFCR
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description: Tamper and alternate function configuration register
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byte_offset: 64
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fieldset: TAFCR
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- name: ALRMSSR
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description: Alarm sub second register
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array:
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len: 2
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stride: 4
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byte_offset: 68
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fieldset: ALRMSSR
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- name: BKPR
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description: Backup register
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array:
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len: 20
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stride: 4
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byte_offset: 80
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fieldset: BKPR
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fieldset/ALRMR:
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description: Alarm register
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fields:
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- name: SU
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description: Second units in BCD format
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bit_offset: 0
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bit_size: 4
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- name: ST
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description: Second tens in BCD format
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bit_offset: 4
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bit_size: 3
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- name: MSK1
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description: Alarm seconds mask
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bit_offset: 7
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bit_size: 1
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enum: ALRMR_MSK
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- name: MNU
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description: Minute units in BCD format
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bit_offset: 8
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bit_size: 4
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- name: MNT
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description: Minute tens in BCD format
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bit_offset: 12
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bit_size: 3
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- name: MSK2
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description: Alarm minutes mask
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bit_offset: 15
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bit_size: 1
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enum: ALRMR_MSK
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- name: HU
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description: Hour units in BCD format
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bit_offset: 16
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bit_size: 4
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- name: HT
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description: Hour tens in BCD format
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bit_offset: 20
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bit_size: 2
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- name: PM
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description: AM/PM notation
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bit_offset: 22
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bit_size: 1
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enum: ALRMR_PM
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- name: MSK3
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description: Alarm hours mask
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bit_offset: 23
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bit_size: 1
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enum: ALRMR_MSK
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- name: DU
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description: Date units or day in BCD format
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bit_offset: 24
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bit_size: 4
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- name: DT
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description: Date tens in BCD format
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bit_offset: 28
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bit_size: 2
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- name: WDSEL
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description: Week day selection
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bit_offset: 30
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bit_size: 1
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enum: ALRMR_WDSEL
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- name: MSK4
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description: Alarm date mask
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bit_offset: 31
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bit_size: 1
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enum: ALRMR_MSK
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fieldset/ALRMSSR:
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description: Alarm sub second register
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fields:
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- name: SS
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description: Sub seconds value
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bit_offset: 0
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bit_size: 15
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- name: MASKSS
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description: Mask the most-significant bits starting at this bit
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bit_offset: 24
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bit_size: 4
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fieldset/BKPR:
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description: Backup register
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fields:
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- name: BKP
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description: BKP
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bit_offset: 0
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bit_size: 32
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fieldset/CALIBR:
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description: Calibration register
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fields:
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- name: DC
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description: Digital calibration
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bit_offset: 0
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bit_size: 5
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- name: DCS
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description: Digital calibration sign
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bit_offset: 7
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bit_size: 1
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fieldset/CALR:
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description: Calibration register
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fields:
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- name: CALM
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description: Calibration minus
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bit_offset: 0
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bit_size: 9
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- name: CALW16
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description: Use a 16-second calibration cycle period
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bit_offset: 13
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bit_size: 1
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enum: CALW16
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- name: CALW8
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description: Use an 8-second calibration cycle period
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bit_offset: 14
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bit_size: 1
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enum: CALW8
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- name: CALP
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description: Increase frequency of RTC by 488.5 ppm
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bit_offset: 15
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bit_size: 1
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enum: CALP
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fieldset/CR:
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description: Control register
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fields:
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- name: WUCKSEL
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description: Wakeup clock selection
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bit_offset: 0
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bit_size: 3
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enum: WUCKSEL
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- name: TSEDGE
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description: Timestamp event active edge
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bit_offset: 3
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bit_size: 1
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enum: TSEDGE
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- name: REFCKON
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description: Reference clock detection enable (50 or 60 Hz)
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bit_offset: 4
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bit_size: 1
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enum: REFCKON
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- name: BYPSHAD
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description: Bypass the shadow registers
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bit_offset: 5
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bit_size: 1
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- name: FMT
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description: Hour format
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bit_offset: 6
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bit_size: 1
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enum: FMT
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- name: DCE
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description: Coarse digital calibration enable
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bit_offset: 7
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bit_size: 1
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- name: ALRE
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description: Alarm enable
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bit_offset: 8
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bit_size: 1
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array:
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len: 2
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stride: 1
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- name: WUTE
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description: Wakeup timer enable
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bit_offset: 10
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bit_size: 1
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- name: TSE
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description: Timestamp enable
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bit_offset: 11
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bit_size: 1
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- name: ALRIE
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description: Alarm interrupt enable
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bit_offset: 12
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bit_size: 1
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array:
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len: 2
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stride: 1
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- name: WUTIE
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description: Wakeup timer interrupt enable
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bit_offset: 14
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bit_size: 1
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- name: TSIE
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description: Timestamp interrupt enable
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bit_offset: 15
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bit_size: 1
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- name: ADD1H
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description: Add 1 hour (summer time change)
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bit_offset: 16
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bit_size: 1
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- name: SUB1H
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description: Subtract 1 hour (winter time change)
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bit_offset: 17
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bit_size: 1
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- name: BKP
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description: Backup
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bit_offset: 18
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bit_size: 1
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- name: COSEL
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description: Calibration output selection
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bit_offset: 19
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bit_size: 1
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enum: COSEL
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- name: POL
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description: Output polarity
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bit_offset: 20
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bit_size: 1
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enum: POL
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- name: OSEL
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description: Output selection
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bit_offset: 21
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bit_size: 2
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enum: OSEL
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- name: COE
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description: Calibration output enable
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bit_offset: 23
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bit_size: 1
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fieldset/DR:
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description: Date register
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fields:
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- name: DU
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description: Date units in BCD format
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bit_offset: 0
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bit_size: 4
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- name: DT
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description: Date tens in BCD format
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bit_offset: 4
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bit_size: 2
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- name: MU
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description: Month units in BCD format
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bit_offset: 8
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bit_size: 4
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- name: MT
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description: Month tens in BCD format
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bit_offset: 12
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bit_size: 1
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- name: WDU
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description: Week day units
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bit_offset: 13
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bit_size: 3
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- name: YU
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description: Year units in BCD format
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bit_offset: 16
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bit_size: 4
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- name: YT
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description: Year tens in BCD format
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bit_offset: 20
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bit_size: 4
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fieldset/ISR:
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description: Initialization and status register
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fields:
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- name: ALRWF
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description: Alarm write flag
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bit_offset: 0
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bit_size: 1
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array:
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len: 2
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stride: 1
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enum: ALRWF
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- name: WUTWF
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description: Wakeup timer write flag
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bit_offset: 2
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bit_size: 1
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enum: WUTWF
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- name: SHPF
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description: Shift operation pending
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bit_offset: 3
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bit_size: 1
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- name: INITS
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description: Initialization status flag
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bit_offset: 4
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bit_size: 1
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enum: INITS
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- name: RSF
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description: Registers synchronization flag
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bit_offset: 5
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bit_size: 1
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- name: INITF
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description: Initialization flag
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bit_offset: 6
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bit_size: 1
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enum: INITF
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- name: INIT
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description: Initialization mode
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bit_offset: 7
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bit_size: 1
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enum: INIT
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- name: ALRF
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description: Alarm flag
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bit_offset: 8
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bit_size: 1
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array:
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len: 2
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stride: 1
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- name: WUTF
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description: Wakeup timer flag
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bit_offset: 10
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bit_size: 1
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- name: TSF
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description: Timestamp flag
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bit_offset: 11
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bit_size: 1
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- name: TSOVF
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description: Timestamp overflow flag
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bit_offset: 12
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bit_size: 1
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- name: TAMPF
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description: Tamper detection flag
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bit_offset: 13
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bit_size: 1
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array:
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len: 3
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stride: 1
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- name: RECALPF
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description: Recalibration pending flag
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bit_offset: 16
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bit_size: 1
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enum: RECALPF
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fieldset/PRER:
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description: Prescaler register
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fields:
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- name: PREDIV_S
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description: Synchronous prescaler factor
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bit_offset: 0
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bit_size: 15
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- name: PREDIV_A
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description: Asynchronous prescaler factor
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bit_offset: 16
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bit_size: 7
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fieldset/SHIFTR:
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description: Shift control register
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fields:
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- name: SUBFS
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description: Subtract a fraction of a second
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bit_offset: 0
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bit_size: 15
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- name: ADD1S
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description: Add one second
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bit_offset: 31
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bit_size: 1
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fieldset/SSR:
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description: Sub second register
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fields:
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- name: SS
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description: Sub second value
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bit_offset: 0
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bit_size: 16
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fieldset/TAFCR:
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description: Tamper and alternate function configuration register
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fields:
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- name: TAMPE
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description: Tamper detection enable
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bit_offset: 0
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bit_size: 1
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array:
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offsets:
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- 0
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- 3
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- name: TAMPTRG
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description: Active level for tamper
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bit_offset: 1
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bit_size: 1
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array:
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offsets:
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- 0
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- 3
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enum: TAMPTRG
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- name: TAMPIE
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description: Tamper interrupt enable
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bit_offset: 2
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bit_size: 1
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- name: TAMPTS
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description: Activate timestamp on tamper detection event
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bit_offset: 7
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bit_size: 1
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- name: TAMPFREQ
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description: Tamper sampling frequency
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bit_offset: 8
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bit_size: 3
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enum: TAMPFREQ
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- name: TAMPFLT
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description: Tamper filter count
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bit_offset: 11
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bit_size: 2
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enum: TAMPFLT
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- name: TAMPPRCH
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description: Tamper precharge duration
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bit_offset: 13
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bit_size: 2
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enum: TAMPPRCH
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- name: TAMPPUDIS
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description: Tamper pull-up disable
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bit_offset: 15
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bit_size: 1
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enum: TAMPPUDIS
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- name: TAMP1INSEL
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description: Tamper 1 mapping
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bit_offset: 16
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bit_size: 1
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- name: TSINSEL
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description: Timestamp mapping
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bit_offset: 17
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bit_size: 1
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- name: ALARMOUTTYPE
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description: AFO_ALARM output type
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bit_offset: 18
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bit_size: 1
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fieldset/TR:
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description: Time register
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fields:
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- name: SU
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description: Second units in BCD format
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bit_offset: 0
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bit_size: 4
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- name: ST
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description: Second tens in BCD format
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bit_offset: 4
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bit_size: 3
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- name: MNU
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description: Minute units in BCD format
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bit_offset: 8
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bit_size: 4
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- name: MNT
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description: Minute tens in BCD format
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bit_offset: 12
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bit_size: 3
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- name: HU
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description: Hour units in BCD format
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bit_offset: 16
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bit_size: 4
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- name: HT
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description: Hour tens in BCD format
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bit_offset: 20
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bit_size: 2
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- name: PM
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description: AM/PM notation
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bit_offset: 22
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bit_size: 1
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enum: AMPM
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fieldset/TSDR:
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description: Timestamp date register
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fields:
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- name: DU
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description: Date units in BCD format
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bit_offset: 0
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bit_size: 4
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- name: DT
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description: Date tens in BCD format
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bit_offset: 4
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bit_size: 2
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- name: MU
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description: Month units in BCD format
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bit_offset: 8
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bit_size: 4
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- name: MT
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description: Month tens in BCD format
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bit_offset: 12
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bit_size: 1
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- name: WDU
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description: Week day units
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bit_offset: 13
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bit_size: 3
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fieldset/TSSSR:
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description: Timestamp sub second register
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fields:
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- name: SS
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description: Sub second value
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bit_offset: 0
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bit_size: 16
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fieldset/TSTR:
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description: Timestamp time register
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fields:
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- name: SU
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description: Second units in BCD format
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bit_offset: 0
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bit_size: 4
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- name: ST
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description: Second tens in BCD format
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bit_offset: 4
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bit_size: 3
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- name: MNU
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description: Minute units in BCD format
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bit_offset: 8
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bit_size: 4
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- name: MNT
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description: Minute tens in BCD format
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bit_offset: 12
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bit_size: 3
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- name: HU
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description: Hour units in BCD format
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bit_offset: 16
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bit_size: 4
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- name: HT
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description: Hour tens in BCD format
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bit_offset: 20
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bit_size: 2
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- name: PM
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description: AM/PM notation
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bit_offset: 22
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bit_size: 1
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enum: AMPM
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fieldset/WPR:
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description: Write protection register
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fields:
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- name: KEY
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description: Write protection key
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bit_offset: 0
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bit_size: 8
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fieldset/WUTR:
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description: Wakeup timer register
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fields:
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- name: WUT
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description: Wakeup auto-reload value bits
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bit_offset: 0
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bit_size: 16
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enum/ALRMR_MSK:
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bit_size: 1
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variants:
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- name: Mask
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description: Alarm set if the date/day match
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value: 0
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- name: NotMask
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description: Date/day don’t care in Alarm comparison
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value: 1
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enum/ALRMR_PM:
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bit_size: 1
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variants:
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- name: AM
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description: AM or 24-hour format
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value: 0
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- name: PM
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||
description: PM
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value: 1
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enum/ALRMR_WDSEL:
|
||
bit_size: 1
|
||
variants:
|
||
- name: DateUnits
|
||
description: "DU[3:0] represents the date units"
|
||
value: 0
|
||
- name: WeekDay
|
||
description: "DU[3:0] represents the week day. DT[1:0] is don’t care"
|
||
value: 1
|
||
enum/ALRWF:
|
||
bit_size: 1
|
||
variants:
|
||
- name: UpdateNotAllowed
|
||
description: Alarm update not allowed
|
||
value: 0
|
||
- name: UpdateAllowed
|
||
description: Alarm update allowed
|
||
value: 1
|
||
enum/AMPM:
|
||
bit_size: 1
|
||
variants:
|
||
- name: AM
|
||
description: AM or 24-hour format
|
||
value: 0
|
||
- name: PM
|
||
description: PM
|
||
value: 1
|
||
enum/CALP:
|
||
bit_size: 1
|
||
variants:
|
||
- name: NoChange
|
||
description: No RTCCLK pulses are added
|
||
value: 0
|
||
- name: IncreaseFreq
|
||
description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)
|
||
value: 1
|
||
enum/CALW16:
|
||
bit_size: 1
|
||
variants:
|
||
- name: Sixteen_Second
|
||
description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1"
|
||
value: 1
|
||
enum/CALW8:
|
||
bit_size: 1
|
||
variants:
|
||
- name: Eight_Second
|
||
description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected"
|
||
value: 1
|
||
enum/COSEL:
|
||
bit_size: 1
|
||
variants:
|
||
- name: CalFreq_512Hz
|
||
description: Calibration output is 512 Hz (with default prescaler setting)
|
||
value: 0
|
||
- name: CalFreq_1Hz
|
||
description: Calibration output is 1 Hz (with default prescaler setting)
|
||
value: 1
|
||
enum/FMT:
|
||
bit_size: 1
|
||
variants:
|
||
- name: Twenty_Four_Hour
|
||
description: 24 hour/day format
|
||
value: 0
|
||
- name: AM_PM
|
||
description: AM/PM hour format
|
||
value: 1
|
||
enum/INIT:
|
||
bit_size: 1
|
||
variants:
|
||
- name: FreeRunningMode
|
||
description: Free running mode
|
||
value: 0
|
||
- name: InitMode
|
||
description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."
|
||
value: 1
|
||
enum/INITF:
|
||
bit_size: 1
|
||
variants:
|
||
- name: NotAllowed
|
||
description: Calendar registers update is not allowed
|
||
value: 0
|
||
- name: Allowed
|
||
description: Calendar registers update is allowed
|
||
value: 1
|
||
enum/INITS:
|
||
bit_size: 1
|
||
variants:
|
||
- name: NotInitalized
|
||
description: Calendar has not been initialized
|
||
value: 0
|
||
- name: Initalized
|
||
description: Calendar has been initialized
|
||
value: 1
|
||
enum/OSEL:
|
||
bit_size: 2
|
||
variants:
|
||
- name: Disabled
|
||
description: Output disabled
|
||
value: 0
|
||
- name: AlarmA
|
||
description: Alarm A output enabled
|
||
value: 1
|
||
- name: AlarmB
|
||
description: Alarm B output enabled
|
||
value: 2
|
||
- name: Wakeup
|
||
description: Wakeup output enabled
|
||
value: 3
|
||
enum/POL:
|
||
bit_size: 1
|
||
variants:
|
||
- name: High
|
||
description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
|
||
value: 0
|
||
- name: Low
|
||
description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"
|
||
value: 1
|
||
enum/RECALPF:
|
||
bit_size: 1
|
||
variants:
|
||
- name: Pending
|
||
description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0"
|
||
value: 1
|
||
enum/REFCKON:
|
||
bit_size: 1
|
||
variants:
|
||
- name: Disabled
|
||
description: RTC_REFIN detection disabled
|
||
value: 0
|
||
- name: Enabled
|
||
description: RTC_REFIN detection enabled
|
||
value: 1
|
||
enum/TAMPFLT:
|
||
bit_size: 2
|
||
variants:
|
||
- name: Immediate
|
||
description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input)
|
||
value: 0
|
||
- name: Samples2
|
||
description: Tamper event is activated after 2 consecutive samples at the active level
|
||
value: 1
|
||
- name: Samples4
|
||
description: Tamper event is activated after 4 consecutive samples at the active level
|
||
value: 2
|
||
- name: Samples8
|
||
description: Tamper event is activated after 8 consecutive samples at the active level
|
||
value: 3
|
||
enum/TAMPFREQ:
|
||
bit_size: 3
|
||
variants:
|
||
- name: Div32768
|
||
description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)
|
||
value: 0
|
||
- name: Div16384
|
||
description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)
|
||
value: 1
|
||
- name: Div8192
|
||
description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)
|
||
value: 2
|
||
- name: Div4096
|
||
description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)
|
||
value: 3
|
||
- name: Div2048
|
||
description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)
|
||
value: 4
|
||
- name: Div1024
|
||
description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)
|
||
value: 5
|
||
- name: Div512
|
||
description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)
|
||
value: 6
|
||
- name: Div256
|
||
description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
|
||
value: 7
|
||
enum/TAMPPRCH:
|
||
bit_size: 2
|
||
variants:
|
||
- name: Cycles1
|
||
description: 1 RTCCLK cycle
|
||
value: 0
|
||
- name: Cycles2
|
||
description: 2 RTCCLK cycles
|
||
value: 1
|
||
- name: Cycles4
|
||
description: 4 RTCCLK cycles
|
||
value: 2
|
||
- name: Cycles8
|
||
description: 8 RTCCLK cycles
|
||
value: 3
|
||
enum/TAMPPUDIS:
|
||
bit_size: 1
|
||
variants:
|
||
- name: Enabled
|
||
description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up)
|
||
value: 0
|
||
- name: Disabled
|
||
description: Disable precharge of RTC_TAMPx pins
|
||
value: 1
|
||
enum/TAMPTRG:
|
||
bit_size: 1
|
||
variants:
|
||
- name: RisingEdge
|
||
description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event."
|
||
value: 0
|
||
- name: FallingEdge
|
||
description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event"
|
||
value: 1
|
||
enum/TSEDGE:
|
||
bit_size: 1
|
||
variants:
|
||
- name: RisingEdge
|
||
description: RTC_TS input rising edge generates a time-stamp event
|
||
value: 0
|
||
- name: FallingEdge
|
||
description: RTC_TS input falling edge generates a time-stamp event
|
||
value: 1
|
||
enum/WUCKSEL:
|
||
bit_size: 3
|
||
variants:
|
||
- name: Div16
|
||
description: RTC/16 clock is selected
|
||
value: 0
|
||
- name: Div8
|
||
description: RTC/8 clock is selected
|
||
value: 1
|
||
- name: Div4
|
||
description: RTC/4 clock is selected
|
||
value: 2
|
||
- name: Div2
|
||
description: RTC/2 clock is selected
|
||
value: 3
|
||
- name: ClockSpare
|
||
description: ck_spre (usually 1 Hz) clock is selected
|
||
value: 4
|
||
- name: ClockSpareWithOffset
|
||
description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
|
||
value: 6
|
||
enum/WUTWF:
|
||
bit_size: 1
|
||
variants:
|
||
- name: UpdateNotAllowed
|
||
description: Wakeup timer configuration update not allowed
|
||
value: 0
|
||
- name: UpdateAllowed
|
||
description: Wakeup timer configuration update allowed
|
||
value: 1
|