381 lines
16 KiB
C
Executable File
381 lines
16 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t day : 8; // 0 Timestamp Day
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uint32_t mon : 8; // 8 Timestamp Month
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uint32_t year : 4; // 16 Timestamp Year
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uint32_t substep : 4; // 20 Sub-step of Core release
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uint32_t step : 4; // 24 Step of Core release
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uint32_t rel : 4; // 28 Core release
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} reg_sec_fdcan1_ram_fdcan_crel_t;
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typedef struct {
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uint32_t etv : 32; // 0 Endiannes Test Value
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} reg_sec_fdcan1_ram_fdcan_endn_t;
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typedef struct {
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uint32_t dsjw : 4; // 0 Synchronization Jump Width
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uint32_t dtseg2 : 4; // 4 Data time segment after sample point
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uint32_t dtseg1 : 5; // 8 Data time segment after sample point
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uint32_t reserve0 : 3; // 13 Reserve
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uint32_t dbrp : 5; // 16 Data BIt Rate Prescaler
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uint32_t reserve1 : 2; // 21 Reserve
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uint32_t tdc : 1; // 23 Transceiver Delay Compensation
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uint32_t reserve2 : 8; // 24 Reserve
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} reg_sec_fdcan1_ram_fdcan_dbtp_t;
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typedef struct {
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uint32_t reserve0 : 4; // 0 Reserve
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uint32_t lbck : 1; // 4 Loop Back mode
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uint32_t tx : 2; // 5 Loop Back mode
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uint32_t rx : 1; // 7 Control of Transmit Pin
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uint32_t reserve1 : 24; // 8 Reserve
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} reg_sec_fdcan1_ram_fdcan_test_t;
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typedef struct {
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uint32_t wdc : 8; // 0 Watchdog configuration
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uint32_t wdv : 8; // 8 Watchdog value
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_sec_fdcan1_ram_fdcan_rwd_t;
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typedef struct {
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uint32_t init : 1; // 0 Initialization
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uint32_t cce : 1; // 1 Configuration Change Enable
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uint32_t asm : 1; // 2 ASM Restricted Operation Mode
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uint32_t csa : 1; // 3 Clock Stop Acknowledge
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uint32_t csr : 1; // 4 Clock Stop Request
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uint32_t mon : 1; // 5 Bus Monitoring Mode
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uint32_t dar : 1; // 6 Disable Automatic Retransmission
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uint32_t test : 1; // 7 Test Mode Enable
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uint32_t fdoe : 1; // 8 FD Operation Enable
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uint32_t brse : 1; // 9 FDCAN Bit Rate Switching
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uint32_t reserve0 : 2; // 10 Reserve
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uint32_t pxhd : 1; // 12 Protocol Exception Handling Disable
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uint32_t efbi : 1; // 13 Edge Filtering during Bus Integration
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uint32_t txp : 1; // 14 TXP
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uint32_t niso : 1; // 15 Non ISO Operation
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uint32_t reserve1 : 16; // 16 Reserve
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} reg_sec_fdcan1_ram_fdcan_cccr_t;
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typedef struct {
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uint32_t ntseg2 : 7; // 0 Nominal Time segment after sample point
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uint32_t reserve0 : 1; // 7 Reserve
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uint32_t ntseg1 : 8; // 8 Nominal Time segment before sample point
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uint32_t nbrp : 9; // 16 Bit Rate Prescaler
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uint32_t nsjw : 7; // 25 Nominal (Re)Synchronization Jump Width
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} reg_sec_fdcan1_ram_fdcan_nbtp_t;
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typedef struct {
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uint32_t tss : 2; // 0 Timestamp Select
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uint32_t reserve0 : 14; // 2 Reserve
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uint32_t tcp : 4; // 16 Timestamp Counter Prescaler
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uint32_t reserve1 : 12; // 20 Reserve
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} reg_sec_fdcan1_ram_fdcan_tscc_t;
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typedef struct {
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uint32_t tsc : 16; // 0 Timestamp Counter
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_sec_fdcan1_ram_fdcan_tscv_t;
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typedef struct {
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uint32_t etoc : 1; // 0 Enable Timeout Counter
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uint32_t tos : 2; // 1 Timeout Select
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uint32_t reserve0 : 13; // 3 Reserve
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uint32_t top : 16; // 16 Timeout Period
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} reg_sec_fdcan1_ram_fdcan_tocc_t;
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typedef struct {
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uint32_t toc : 16; // 0 Timeout Counter
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_sec_fdcan1_ram_fdcan_tocv_t;
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typedef struct {
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uint32_t tec : 8; // 0 Transmit Error Counter
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uint32_t rec : 7; // 8 Receive Error Counter
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uint32_t rp : 1; // 15 Receive Error Passive
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uint32_t cel : 8; // 16 AN Error Logging
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uint32_t reserve0 : 8; // 24 Reserve
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} reg_sec_fdcan1_ram_fdcan_ecr_t;
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typedef struct {
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uint32_t lec : 3; // 0 Last Error Code
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uint32_t act : 2; // 3 Activity
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uint32_t ep : 1; // 5 Error Passive
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uint32_t ew : 1; // 6 Warning Status
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uint32_t bo : 1; // 7 Bus_Off Status
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uint32_t dlec : 3; // 8 Data Last Error Code
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uint32_t resi : 1; // 11 ESI flag of last received FDCAN Message
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uint32_t rbrs : 1; // 12 BRS flag of last received FDCAN Message
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uint32_t redl : 1; // 13 Received FDCAN Message
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uint32_t pxe : 1; // 14 Protocol Exception Event
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uint32_t reserve0 : 1; // 15 Reserve
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uint32_t tdcv : 7; // 16 Transmitter Delay Compensation Value
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uint32_t reserve1 : 9; // 23 Reserve
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} reg_sec_fdcan1_ram_fdcan_psr_t;
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typedef struct {
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uint32_t tdcf : 7; // 0 Transmitter Delay Compensation Filter Window Length
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uint32_t reserve0 : 1; // 7 Reserve
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uint32_t tdco : 7; // 8 Transmitter Delay Compensation Offset
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uint32_t reserve1 : 17; // 15 Reserve
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} reg_sec_fdcan1_ram_fdcan_tdcr_t;
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typedef struct {
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uint32_t rf0n : 1; // 0 RF0N
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uint32_t rf0f : 1; // 1 RF0F
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uint32_t rf0l : 1; // 2 RF0L
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uint32_t rf1n : 1; // 3 RF1N
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uint32_t rf1f : 1; // 4 RF1F
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uint32_t rf1l : 1; // 5 RF1L
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uint32_t hpm : 1; // 6 HPM
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uint32_t tc : 1; // 7 TC
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uint32_t tcf : 1; // 8 TCF
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uint32_t tfe : 1; // 9 TFE
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uint32_t tefn : 1; // 10 TEFN
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uint32_t teff : 1; // 11 TEFF
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uint32_t tefl : 1; // 12 TEFL
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uint32_t tsw : 1; // 13 TSW
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uint32_t mraf : 1; // 14 MRAF
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uint32_t too : 1; // 15 TOO
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uint32_t elo : 1; // 16 ELO
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uint32_t ep : 1; // 17 EP
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uint32_t ew : 1; // 18 EW
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uint32_t bo : 1; // 19 BO
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uint32_t wdi : 1; // 20 WDI
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uint32_t pea : 1; // 21 PEA
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uint32_t ped : 1; // 22 PED
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uint32_t ara : 1; // 23 ARA
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uint32_t reserve0 : 8; // 24 Reserve
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} reg_sec_fdcan1_ram_fdcan_ir_t;
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typedef struct {
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uint32_t rf0ne : 1; // 0 Rx FIFO 0 New Message Enable
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uint32_t rf0fe : 1; // 1 Rx FIFO 0 Full Enable
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uint32_t rf0le : 1; // 2 Rx FIFO 0 Message Lost Enable
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uint32_t rf1ne : 1; // 3 Rx FIFO 1 New Message Enable
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uint32_t rf1fe : 1; // 4 Rx FIFO 1 Watermark Reached Enable
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uint32_t rf1le : 1; // 5 Rx FIFO 1 Message Lost Enable
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uint32_t hpme : 1; // 6 High Priority Message Enable
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uint32_t tce : 1; // 7 Transmission Completed Enable
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uint32_t tcfe : 1; // 8 Transmission Cancellation Finished Enable
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uint32_t tefe : 1; // 9 Tx FIFO Empty Enable
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uint32_t tefne : 1; // 10 Tx Event FIFO New Entry Enable
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uint32_t teffe : 1; // 11 Tx Event FIFO Full Enable
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uint32_t tefle : 1; // 12 Tx Event FIFO Element Lost Enable
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uint32_t tswe : 1; // 13 TSWE
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uint32_t mrafe : 1; // 14 Message RAM Access Failure Enable
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uint32_t tooe : 1; // 15 Timeout Occurred Enable
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uint32_t eloe : 1; // 16 Error Logging Overflow Enable
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uint32_t epe : 1; // 17 Error Passive Enable
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uint32_t ewe : 1; // 18 Warning Status Enable
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uint32_t boe : 1; // 19 Bus_Off Status Enable
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uint32_t wdie : 1; // 20 Watchdog Interrupt Enable
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uint32_t peae : 1; // 21 Protocol Error in Arbitration Phase Enable
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uint32_t pede : 1; // 22 Protocol Error in Data Phase Enable
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uint32_t arae : 1; // 23 Access to Reserved Address Enable
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uint32_t reserve0 : 8; // 24 Reserve
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} reg_sec_fdcan1_ram_fdcan_ie_t;
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typedef struct {
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uint32_t rxfifo0 : 1; // 0 RxFIFO0
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uint32_t rxfifo1 : 1; // 1 RxFIFO1
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uint32_t smsg : 1; // 2 SMSG
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uint32_t tferr : 1; // 3 TFERR
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uint32_t misc : 1; // 4 MISC
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uint32_t berr : 1; // 5 BERR
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uint32_t perr : 1; // 6 PERR
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uint32_t reserve0 : 25; // 7 Reserve
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} reg_sec_fdcan1_ram_fdcan_ils_t;
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typedef struct {
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uint32_t eint0 : 1; // 0 Enable Interrupt Line 0
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uint32_t eint1 : 1; // 1 Enable Interrupt Line 1
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uint32_t reserve0 : 30; // 2 Reserve
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} reg_sec_fdcan1_ram_fdcan_ile_t;
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typedef struct {
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uint32_t rrfe : 1; // 0 Reject Remote Frames Extended
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uint32_t rrfs : 1; // 1 Reject Remote Frames Standard
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uint32_t anfe : 2; // 2 Accept Non-matching Frames Extended
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uint32_t anfs : 2; // 4 Accept Non-matching Frames Standard
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uint32_t reserve0 : 2; // 6 Reserve
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uint32_t f1om : 1; // 8 F1OM
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uint32_t f0om : 1; // 9 F0OM
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uint32_t reserve1 : 6; // 10 Reserve
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uint32_t lss : 5; // 16 LSS
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uint32_t reserve2 : 3; // 21 Reserve
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uint32_t lse : 4; // 24 LSE
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uint32_t reserve3 : 4; // 28 Reserve
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} reg_sec_fdcan1_ram_fdcan_rxgfc_t;
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typedef struct {
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uint32_t eidm : 29; // 0 Extended ID Mask
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uint32_t reserve0 : 3; // 29 Reserve
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} reg_sec_fdcan1_ram_fdcan_xidam_t;
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typedef struct {
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uint32_t bidx : 3; // 0 Buffer Index
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uint32_t reserve0 : 3; // 3 Reserve
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uint32_t msi : 2; // 6 Message Storage Indicator
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uint32_t fidx : 5; // 8 Filter Index
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uint32_t reserve1 : 2; // 13 Reserve
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uint32_t flst : 1; // 15 Filter List
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uint32_t reserve2 : 16; // 16 Reserve
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} reg_sec_fdcan1_ram_fdcan_hpms_t;
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typedef struct {
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uint32_t f0fl : 4; // 0 Rx FIFO 0 Fill Level
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uint32_t reserve0 : 4; // 4 Reserve
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uint32_t f0gi : 2; // 8 Rx FIFO 0 Get Index
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uint32_t reserve1 : 6; // 10 Reserve
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uint32_t f0pi : 2; // 16 Rx FIFO 0 Put Index
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uint32_t reserve2 : 6; // 18 Reserve
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uint32_t f0f : 1; // 24 Rx FIFO 0 Full
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uint32_t rf0l : 1; // 25 Rx FIFO 0 Message Lost
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uint32_t reserve3 : 6; // 26 Reserve
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} reg_sec_fdcan1_ram_fdcan_rxf0s_t;
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typedef struct {
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uint32_t f0ai : 3; // 0 Rx FIFO 0 Acknowledge Index
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uint32_t reserve0 : 29; // 3 Reserve
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} reg_sec_fdcan1_ram_fdcan_rxf0a_t;
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typedef struct {
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uint32_t f1fl : 4; // 0 Rx FIFO 1 Fill Level
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uint32_t reserve0 : 4; // 4 Reserve
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uint32_t f1gi : 2; // 8 Rx FIFO 1 Get Index
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uint32_t reserve1 : 6; // 10 Reserve
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uint32_t f1pi : 2; // 16 Rx FIFO 1 Put Index
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uint32_t reserve2 : 6; // 18 Reserve
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uint32_t f1f : 1; // 24 Rx FIFO 1 Full
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uint32_t rf1l : 1; // 25 Rx FIFO 1 Message Lost
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uint32_t reserve3 : 6; // 26 Reserve
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} reg_sec_fdcan1_ram_fdcan_rxf1s_t;
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typedef struct {
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uint32_t f1ai : 3; // 0 Rx FIFO 1 Acknowledge Index
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uint32_t reserve0 : 29; // 3 Reserve
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} reg_sec_fdcan1_ram_fdcan_rxf1a_t;
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typedef struct {
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uint32_t reserve0 : 24; // 0 Reserve
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uint32_t tfqm : 1; // 24 Tx FIFO/Queue Mode
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uint32_t reserve1 : 7; // 25 Reserve
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} reg_sec_fdcan1_ram_fdcan_txbc_t;
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typedef struct {
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uint32_t tffl : 3; // 0 Tx FIFO Free Level
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uint32_t reserve0 : 5; // 3 Reserve
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uint32_t tfgi : 2; // 8 TFGI
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uint32_t reserve1 : 6; // 10 Reserve
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uint32_t tfqpi : 2; // 16 Tx FIFO/Queue Put Index
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uint32_t reserve2 : 3; // 18 Reserve
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uint32_t tfqf : 1; // 21 Tx FIFO/Queue Full
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uint32_t reserve3 : 10; // 22 Reserve
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} reg_sec_fdcan1_ram_fdcan_txfqs_t;
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typedef struct {
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uint32_t trp : 3; // 0 Transmission Request Pending
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uint32_t reserve0 : 29; // 3 Reserve
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} reg_sec_fdcan1_ram_fdcan_txbrp_t;
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typedef struct {
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uint32_t ar : 3; // 0 Add Request
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uint32_t reserve0 : 29; // 3 Reserve
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} reg_sec_fdcan1_ram_fdcan_txbar_t;
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typedef struct {
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uint32_t cr : 3; // 0 Cancellation Request
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uint32_t reserve0 : 29; // 3 Reserve
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} reg_sec_fdcan1_ram_fdcan_txbcr_t;
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typedef struct {
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uint32_t to : 3; // 0 Transmission Occurred.
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uint32_t reserve0 : 29; // 3 Reserve
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} reg_sec_fdcan1_ram_fdcan_txbto_t;
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typedef struct {
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uint32_t cf : 3; // 0 Cancellation Finished
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uint32_t reserve0 : 29; // 3 Reserve
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} reg_sec_fdcan1_ram_fdcan_txbcf_t;
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typedef struct {
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uint32_t tie : 3; // 0 Transmission Interrupt Enable
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uint32_t reserve0 : 29; // 3 Reserve
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} reg_sec_fdcan1_ram_fdcan_txbtie_t;
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typedef struct {
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uint32_t cfie : 3; // 0 Cancellation Finished Interrupt Enable
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uint32_t reserve0 : 29; // 3 Reserve
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} reg_sec_fdcan1_ram_fdcan_txbcie_t;
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typedef struct {
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uint32_t effl : 3; // 0 Event FIFO Fill Level
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uint32_t reserve0 : 5; // 3 Reserve
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uint32_t efgi : 2; // 8 Event FIFO Get Index.
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uint32_t reserve1 : 6; // 10 Reserve
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uint32_t efpi : 2; // 16 Event FIFO Put Index
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uint32_t reserve2 : 6; // 18 Reserve
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uint32_t eff : 1; // 24 Event FIFO Full.
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uint32_t tefl : 1; // 25 Tx Event FIFO Element Lost.
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uint32_t reserve3 : 6; // 26 Reserve
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} reg_sec_fdcan1_ram_fdcan_txefs_t;
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typedef struct {
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uint32_t efai : 2; // 0 Event FIFO Acknowledge Index
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uint32_t reserve0 : 30; // 2 Reserve
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} reg_sec_fdcan1_ram_fdcan_txefa_t;
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typedef struct {
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uint32_t pdiv : 4; // 0 PDIV
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uint32_t reserve0 : 28; // 4 Reserve
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} reg_sec_fdcan1_ram_fdcan_ckdiv_t;
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typedef struct {
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volatile reg_sec_fdcan1_ram_fdcan_crel_t fdcan_crel;
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volatile reg_sec_fdcan1_ram_fdcan_endn_t fdcan_endn;
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volatile uint32_t reserve0[1];
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volatile reg_sec_fdcan1_ram_fdcan_dbtp_t fdcan_dbtp;
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volatile reg_sec_fdcan1_ram_fdcan_test_t fdcan_test;
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volatile reg_sec_fdcan1_ram_fdcan_rwd_t fdcan_rwd;
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volatile reg_sec_fdcan1_ram_fdcan_cccr_t fdcan_cccr;
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volatile reg_sec_fdcan1_ram_fdcan_nbtp_t fdcan_nbtp;
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volatile reg_sec_fdcan1_ram_fdcan_tscc_t fdcan_tscc;
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volatile reg_sec_fdcan1_ram_fdcan_tscv_t fdcan_tscv;
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volatile reg_sec_fdcan1_ram_fdcan_tocc_t fdcan_tocc;
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volatile reg_sec_fdcan1_ram_fdcan_tocv_t fdcan_tocv;
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volatile uint32_t reserve1[4];
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volatile reg_sec_fdcan1_ram_fdcan_ecr_t fdcan_ecr;
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volatile reg_sec_fdcan1_ram_fdcan_psr_t fdcan_psr;
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volatile reg_sec_fdcan1_ram_fdcan_tdcr_t fdcan_tdcr;
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volatile uint32_t reserve2[1];
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volatile reg_sec_fdcan1_ram_fdcan_ir_t fdcan_ir;
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volatile reg_sec_fdcan1_ram_fdcan_ie_t fdcan_ie;
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volatile reg_sec_fdcan1_ram_fdcan_ils_t fdcan_ils;
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volatile reg_sec_fdcan1_ram_fdcan_ile_t fdcan_ile;
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volatile uint32_t reserve3[8];
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volatile reg_sec_fdcan1_ram_fdcan_rxgfc_t fdcan_rxgfc;
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volatile reg_sec_fdcan1_ram_fdcan_xidam_t fdcan_xidam;
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volatile reg_sec_fdcan1_ram_fdcan_hpms_t fdcan_hpms;
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volatile uint32_t reserve4[1];
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volatile reg_sec_fdcan1_ram_fdcan_rxf0s_t fdcan_rxf0s;
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volatile reg_sec_fdcan1_ram_fdcan_rxf0a_t fdcan_rxf0a;
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volatile reg_sec_fdcan1_ram_fdcan_rxf1s_t fdcan_rxf1s;
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volatile reg_sec_fdcan1_ram_fdcan_rxf1a_t fdcan_rxf1a;
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volatile uint32_t reserve5[8];
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volatile reg_sec_fdcan1_ram_fdcan_txbc_t fdcan_txbc;
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volatile reg_sec_fdcan1_ram_fdcan_txfqs_t fdcan_txfqs;
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volatile reg_sec_fdcan1_ram_fdcan_txbrp_t fdcan_txbrp;
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volatile reg_sec_fdcan1_ram_fdcan_txbar_t fdcan_txbar;
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volatile reg_sec_fdcan1_ram_fdcan_txbcr_t fdcan_txbcr;
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volatile reg_sec_fdcan1_ram_fdcan_txbto_t fdcan_txbto;
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volatile reg_sec_fdcan1_ram_fdcan_txbcf_t fdcan_txbcf;
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volatile reg_sec_fdcan1_ram_fdcan_txbtie_t fdcan_txbtie;
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volatile reg_sec_fdcan1_ram_fdcan_txbcie_t fdcan_txbcie;
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volatile reg_sec_fdcan1_ram_fdcan_txefs_t fdcan_txefs;
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volatile reg_sec_fdcan1_ram_fdcan_txefa_t fdcan_txefa;
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volatile uint32_t reserve6[5];
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volatile reg_sec_fdcan1_ram_fdcan_ckdiv_t fdcan_ckdiv;
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} reg_sec_fdcan1_ram_t;
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