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Mason 2023-11-14 16:25:09 -05:00
commit dbefded049
Signed by untrusted user who does not match committer: guangzong
GPG Key ID: 095389BACAE97D19
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12
.cargo/config Normal file
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# .cargo/config
[build]
# Always compile for the instruction set of the STM32F1
target = "thumbv8m.main-none-eabihf"
# use the Tlink.x scrip from the cortex-m-rt crate
rustflags = [ "-C", "link-arg=-Tlink.x"]
[net]
retry = 3 # network retries
git-fetch-with-cli = true

2
.gitignore vendored Normal file
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/target
.DS_Store

195
Cargo.lock generated Normal file
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# This file is automatically @generated by Cargo.
# It is not intended for manual editing.
version = 3
[[package]]
name = "bare-metal"
version = "0.2.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "5deb64efa5bd81e31fcd1938615a6d98c82eafcbcd787162b6f63b91d6bac5b3"
dependencies = [
"rustc_version",
]
[[package]]
name = "bitfield"
version = "0.13.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "46afbd2983a5d5a7bd740ccb198caf5b82f45c40c09c0eed36052d91cb92e719"
[[package]]
name = "cc"
version = "1.0.84"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "0f8e7c90afad890484a21653d08b6e209ae34770fb5ee298f9c699fcc1e5c856"
dependencies = [
"libc",
]
[[package]]
name = "cmake"
version = "0.1.50"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "a31c789563b815f77f4250caee12365734369f942439b7defd71e18a48197130"
dependencies = [
"cc",
]
[[package]]
name = "cortex-m"
version = "0.7.7"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "8ec610d8f49840a5b376c69663b6369e71f4b34484b9b2eb29fb918d92516cb9"
dependencies = [
"bare-metal",
"bitfield",
"embedded-hal",
"volatile-register",
]
[[package]]
name = "cortex-m-rt"
version = "0.6.15"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "454f278bf469e2de0a4d22ea019d169d8944f86957c8207a39e3f66c32be2fc6"
dependencies = [
"cortex-m-rt-macros",
"r0",
]
[[package]]
name = "cortex-m-rt-macros"
version = "0.6.15"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "c8e3aa52243e26f5922fa522b0814019e0c98fc567e2756d715dce7ad7a81f49"
dependencies = [
"proc-macro2",
"quote",
"syn",
]
[[package]]
name = "embedded-hal"
version = "0.2.7"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "35949884794ad573cf46071e41c9b60efb0cb311e3ca01f7af807af1debc66ff"
dependencies = [
"nb 0.1.3",
"void",
]
[[package]]
name = "libc"
version = "0.2.150"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "89d92a4743f9a61002fae18374ed11e7973f530cb3a3255fb354818118b2203c"
[[package]]
name = "nb"
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source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "801d31da0513b6ec5214e9bf433a77966320625a37860f910be265be6e18d06f"
dependencies = [
"nb 1.1.0",
]
[[package]]
name = "nb"
version = "1.1.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
name = "proc-macro2"
version = "1.0.69"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "134c189feb4956b20f6f547d2cf727d4c0fe06722b20a0eec87ed445a97f92da"
dependencies = [
"unicode-ident",
]
[[package]]
name = "quote"
version = "1.0.33"
source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
"proc-macro2",
]
[[package]]
name = "r0"
version = "0.2.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f"
[[package]]
name = "rustc_version"
version = "0.2.3"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "138e3e0acb6c9fb258b19b67cb8abd63c00679d2851805ea151465464fe9030a"
dependencies = [
"semver",
]
[[package]]
name = "semver"
version = "0.9.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "1d7eb9ef2c18661902cc47e535f9bc51b78acd254da71d375c2f6720d9a40403"
dependencies = [
"semver-parser",
]
[[package]]
name = "semver-parser"
version = "0.7.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3"
[[package]]
name = "syn"
version = "1.0.109"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "72b64191b275b66ffe2469e8af2c1cfe3bafa67b529ead792a6d0160888b4237"
dependencies = [
"proc-macro2",
"quote",
"unicode-ident",
]
[[package]]
name = "u5"
version = "0.1.0"
dependencies = [
"cmake",
"cortex-m",
"cortex-m-rt",
]
[[package]]
name = "unicode-ident"
version = "1.0.12"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0fee4b"
[[package]]
name = "vcell"
version = "0.1.3"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "77439c1b53d2303b20d9459b1ade71a83c716e3f9c34f3228c00e6f185d6c002"
[[package]]
name = "void"
version = "1.0.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d"
[[package]]
name = "volatile-register"
version = "0.2.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "de437e2a6208b014ab52972a27e59b33fa2920d3e00fe05026167a1c509d19cc"
dependencies = [
"vcell",
]

18
Cargo.toml Normal file
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[package]
name = "u5"
version = "0.1.0"
edition = "2021"
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
[net]
retry = 3 # network retries
git-fetch-with-cli = true
[dependencies]
cortex-m = "0.7.3"
cortex-m-rt = "0.6.13"
# CARGO_NET_GIT_FETCH_WITH_CLI=true
[build-dependencies]
cmake = "0.1"

6
Makefile Normal file
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.PHONY: all
all: clean
cargo build
clean:
cargo clean

15
build.rs Normal file
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// build.rs
use cmake::Config;
fn main() {
// Tell Cargo to tell rustc to link the C++ library.
println!("cargo:rustc-link-lib=static=stm32u5");
// Use cmake to build the C++ project
let dst = Config::new("stm32u5").build();
// Tell Cargo where to find the compiled library
println!("cargo:rustc-link-search=native={}", dst.display());
// get the out dir of dependcy `cortex-m`
}

1
src/lib.rs Normal file
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#![no_std]

147
stm32u5/.clang-tidy Executable file
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# Generated from CLion Inspection settings
---
Checks: '-*,
bugprone-argument-comment,
bugprone-assert-side-effect,
bugprone-bad-signal-to-kill-thread,
bugprone-branch-clone,
bugprone-copy-constructor-init,
bugprone-dangling-handle,
bugprone-dynamic-static-initializers,
bugprone-fold-init-type,
bugprone-forward-declaration-namespace,
bugprone-forwarding-reference-overload,
bugprone-inaccurate-erase,
bugprone-incorrect-roundings,
bugprone-integer-division,
bugprone-lambda-function-name,
bugprone-macro-parentheses,
bugprone-macro-repeated-side-effects,
bugprone-misplaced-operator-in-strlen-in-alloc,
bugprone-misplaced-pointer-arithmetic-in-alloc,
bugprone-misplaced-widening-cast,
bugprone-move-forwarding-reference,
bugprone-multiple-statement-macro,
bugprone-no-escape,
bugprone-not-null-terminated-result,
bugprone-parent-virtual-call,
bugprone-posix-return,
bugprone-reserved-identifier,
bugprone-sizeof-container,
bugprone-sizeof-expression,
bugprone-spuriously-wake-up-functions,
bugprone-string-constructor,
bugprone-string-integer-assignment,
bugprone-string-literal-with-embedded-nul,
bugprone-suspicious-enum-usage,
bugprone-suspicious-include,
bugprone-suspicious-memory-comparison,
bugprone-suspicious-memset-usage,
bugprone-suspicious-missing-comma,
bugprone-suspicious-semicolon,
bugprone-suspicious-string-compare,
bugprone-swapped-arguments,
bugprone-terminating-continue,
bugprone-throw-keyword-missing,
bugprone-too-small-loop-variable,
bugprone-undefined-memory-manipulation,
bugprone-undelegated-constructor,
bugprone-unhandled-self-assignment,
bugprone-unused-raii,
bugprone-unused-return-value,
bugprone-use-after-move,
bugprone-virtual-near-miss,
cert-dcl21-cpp,
cert-dcl58-cpp,
cert-err34-c,
cert-err52-cpp,
cert-err60-cpp,
cert-flp30-c,
cert-msc50-cpp,
cert-msc51-cpp,
cert-str34-c,
cppcoreguidelines-interfaces-global-init,
cppcoreguidelines-narrowing-conversions,
cppcoreguidelines-pro-type-member-init,
cppcoreguidelines-pro-type-static-cast-downcast,
cppcoreguidelines-slicing,
google-default-arguments,
google-explicit-constructor,
google-runtime-operator,
hicpp-exception-baseclass,
hicpp-multiway-paths-covered,
misc-misplaced-const,
misc-new-delete-overloads,
misc-no-recursion,
misc-non-copyable-objects,
misc-throw-by-value-catch-by-reference,
misc-unconventional-assign-operator,
misc-uniqueptr-reset-release,
modernize-avoid-bind,
modernize-concat-nested-namespaces,
modernize-deprecated-headers,
modernize-deprecated-ios-base-aliases,
modernize-loop-convert,
modernize-make-shared,
modernize-make-unique,
modernize-pass-by-value,
modernize-raw-string-literal,
modernize-redundant-void-arg,
modernize-replace-auto-ptr,
modernize-replace-disallow-copy-and-assign-macro,
modernize-replace-random-shuffle,
modernize-return-braced-init-list,
modernize-shrink-to-fit,
modernize-unary-static-assert,
modernize-use-auto,
modernize-use-bool-literals,
modernize-use-emplace,
modernize-use-equals-default,
modernize-use-equals-delete,
modernize-use-nodiscard,
modernize-use-noexcept,
modernize-use-nullptr,
modernize-use-override,
modernize-use-transparent-functors,
modernize-use-uncaught-exceptions,
mpi-buffer-deref,
mpi-type-mismatch,
openmp-use-default-none,
performance-faster-string-find,
performance-for-range-copy,
performance-implicit-conversion-in-loop,
performance-inefficient-algorithm,
performance-inefficient-string-concatenation,
performance-inefficient-vector-operation,
performance-move-const-arg,
performance-move-constructor-init,
performance-no-automatic-move,
performance-noexcept-move-constructor,
performance-trivially-destructible,
performance-type-promotion-in-math-fn,
performance-unnecessary-copy-initialization,
performance-unnecessary-value-param,
portability-simd-intrinsics,
readability-avoid-const-params-in-decls,
readability-const-return-type,
readability-container-size-empty,
readability-convert-member-functions-to-static,
readability-delete-null-pointer,
readability-deleted-default,
readability-inconsistent-declaration-parameter-name,
readability-make-member-function-const,
readability-misleading-indentation,
readability-misplaced-array-index,
readability-non-const-parameter,
readability-redundant-control-flow,
readability-redundant-declaration,
readability-redundant-function-ptr-dereference,
readability-redundant-smartptr-get,
readability-redundant-string-cstr,
readability-redundant-string-init,
readability-simplify-subscript-expr,
readability-static-accessed-through-instance,
readability-static-definition-in-anonymous-namespace,
readability-string-compare,
readability-uniqueptr-delete-release,
readability-use-anyofallof'

36
stm32u5/.drone.yml Executable file
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---
kind: pipeline
type: exec
name: default
platform:
os: linux
arch: amd64
steps:
- name: greeting
commands:
- echo hello world
- pwd
- # create variable base on project name
- export PROJECT_NAME=$(git config --local remote.origin.url | tr '/' '\n' | tail -1)
- export BRANCH_NAME=$(git rev-parse --abbrev-ref HEAD)
- export BINARY_BASE_PATH=/var/lib/drone-runner-exec/bins/$PROJECT_NAME
- export BINARY_FOLDER_PATH=/var/lib/drone-runner-exec/bins/$PROJECT_NAME/$BRANCH_NAME-$(date +%Y%m%d-%H%M%S)-$(git rev-parse --short HEAD)
- echo $USER
# generate documentation
- doxygen doxygen.cfg
- mv docs stm32u5
- cp -r stm32u5 /var/lib/drone-runner-exec/docs/
- mkdir build
- cd build
- cmake ..
- make
- make install
- # create binary foler base on project name build timer and commit id
- mkdir -p $BINARY_FOLDER_PATH
- cd ..
- cp -r publish/* $BINARY_FOLDER_PATH/
- zip -q -r $BINARY_FOLDER_PATH.zip publish/*
# - cp $BINARY_FOLDER_PATH.zip $BINARY_BASE_PATH/
# - $(date +%Y%m%d%H%M%S)-$(git rev-parse --short HEAD)

19
stm32u5/.gitignore vendored Executable file
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/cmake-build-debug/
/build/
.cproject
.mxproject
.project
compile_commands.json
DCMI Debug.launch
DCMI.ioc
/Debug/
.cache
.flee
.idea
.settings
cmake-build-debug-arm/
docs/
publish/
cmake-build-archgcc/
cmake-build-arm-gcc/
.vscode/

894
stm32u5/CMSIS/Include/cmsis_armcc.h Executable file
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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2019 IAR Systems
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __PROGRAM_START
#define __PROGRAM_START __iar_program_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP CSTACK$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT CSTACK$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __vector_table
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.3
* @date 24. June 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 13. March 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t vectors = 0x0U;
(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = 0x0U;
return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.1
* @date 12. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

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Contributor provides its Contributions) on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied, including, without limitation, any warranties or conditions
of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
PARTICULAR PURPOSE. You are solely responsible for determining the
appropriateness of using or redistributing the Work and assume any
risks associated with Your exercise of permissions under this License.
8. Limitation of Liability. In no event and under no legal theory,
whether in tort (including negligence), contract, or otherwise,
unless required by applicable law (such as deliberate and grossly
negligent acts) or agreed to in writing, shall any Contributor be
liable to You for damages, including any direct, indirect, special,
incidental, or consequential damages of any character arising as a
result of this License or out of the use or inability to use the
Work (including but not limited to damages for loss of goodwill,
work stoppage, computer failure or malfunction, or any and all
other commercial damages or losses), even if such Contributor
has been advised of the possibility of such damages.
9. Accepting Warranty or Additional Liability. While redistributing
the Work or Derivative Works thereof, You may choose to offer,
and charge a fee for, acceptance of support, warranty, indemnity,
or other liability obligations and/or rights consistent with this
License. However, in accepting such obligations, You may act only
on Your own behalf and on Your sole responsibility, not on behalf
of any other Contributor, and only if You agree to indemnify,
defend, and hold each Contributor harmless for any liability
incurred by, or claims asserted against, such Contributor by reason
of your accepting any such warranty or additional liability.
END OF TERMS AND CONDITIONS
APPENDIX: How to apply the Apache License to your work.
To apply the Apache License to your work, attach the following
boilerplate notice, with the fields enclosed by brackets "{}"
replaced with your own identifying information. (Don't include
the brackets!) The text should be enclosed in the appropriate
comment syntax for the file format. We also recommend that a
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Licensed under the Apache License, Version 2.0 (the "License");
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See the License for the specific language governing permissions and
limitations under the License.

55
stm32u5/CMakeLists.txt Normal file
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cmake_minimum_required(VERSION 3.24)
set(CMAKE_SYSTEM_NAME Generic)
set(CMAKE_SYSTEM_PROCESSOR ARM)
set(CMAKE_C_COMPILER_WORKS 1) # skip compiler test
set(CMAKE_CXX_COMPILER_WORKS 1)
project(STM32U5 C CXX ASM)
set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
add_definitions(-DFX_INCLUDE_USER_DEFINE_FILE) # this is for filex
include_directories(
${CMAKE_CURRENT_LIST_DIR}/includes
${CMAKE_CURRENT_LIST_DIR}/includes/u575xx
${CMAKE_CURRENT_LIST_DIR}/includes/lowlevel
${CMAKE_CURRENT_LIST_DIR}/CMSIS/Include
${CMAKE_CURRENT_LIST_DIR}/filex/common/inc
${CMAKE_CURRENT_LIST_DIR}/filex/common/
${CMAKE_CURRENT_LIST_DIR}/filex/ports/generic/inc
)
file(GLOB_RECURSE LIB_SOURCES
"${CMAKE_CURRENT_LIST_DIR}/src/*.c"
"${CMAKE_CURRENT_LIST_DIR}/src/*.cpp"
"${CMAKE_CURRENT_LIST_DIR}/filex/common/src/*.c"
"${CMAKE_CURRENT_LIST_DIR}/startup/startup_stm32u575zitxq.s"
)
message(STATUS "LIB_SOURCES: ${LIB_SOURCES}")
add_definitions(-DSTM32U575xx)
message(STATUS "CMAKE_CURRENT_LIST_DIR: ${CMAKE_CURRENT_LIST_DIR}")
#Uncomment for hardware floating point
# add_compile_definitions(ARM_MATH_CM4;ARM_MATH_MATRIX_CHECK;ARM_MATH_ROUNDING)
# add_compile_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)
# add_compile_options(-mcpu=cortex-m33 -mthumb -mthumb-interwork)
# add_compile_options(-ffunction-sections -fdata-sections -fno-common -fmessage-length=0)
# Enable assembler files preprocessing
# add_compile_options($<$<COMPILE_LANGUAGE:ASM>:-x$<SEMICOLON>assembler-with-cpp>)
add_library(${PROJECT_NAME} STATIC ${LIB_SOURCES})
# copy files to output directory
# file(COPY ${CMAKE_CURRENT_LIST_DIR}/link_script DESTINATION ${CMAKE_BINARY_DIR})
# file(COPY ${CMAKE_CURRENT_LIST_DIR}/includes DESTINATION ${CMAKE_BINARY_DIR})
# file(COPY ${CMAKE_CURRENT_LIST_DIR}/CMSIS DESTINATION ${CMAKE_BINARY_DIR})
# file(COPY ${CMAKE_CURRENT_LIST_DIR}/startup DESTINATION ${CMAKE_BINARY_DIR})
install(TARGETS ${PROJECT_NAME} DESTINATION .)
install(DIRECTORY ${CMAKE_CURRENT_LIST_DIR}/includes DESTINATION .)
install(DIRECTORY ${CMAKE_CURRENT_LIST_DIR}/CMSIS DESTINATION .)
install(DIRECTORY ${CMAKE_CURRENT_LIST_DIR}/startup DESTINATION .)
install(DIRECTORY ${CMAKE_CURRENT_LIST_DIR}/filex DESTINATION .)
install(DIRECTORY ${CMAKE_CURRENT_LIST_DIR}/link_script DESTINATION .)

14
stm32u5/Makefile Normal file
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# incldue sub makefile
.PHONY: connie lib clean
connie:
cmake -DCMAKE_BUILD_TYPE=Debug -S "${PWD}/examples/connie" -B "/tmp/u5/connie_build" -G "Ninja"
cmake --build "/tmp/u5/connie_build" --target all
clean:
rm -rf /tmp/u5/connie_build
lib:
cmake -DCMAKE_BUILD_TYPE=Debug -S "${PWD}" -B "/tmp/u5/lib_build" -G "Ninja"
cmake --build "/tmp/u5/lib_build" --target all
cp:
cp /tmp/u5/lib_build/libSTM32U5.a /home/zong/OneDrive/Code/stm32u5/examples/connie/libSTM32U5.a

54
stm32u5/Stm32U5LibConfig.cmake Normal file
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set(COMPILE_PREFIX "")
if (APPLE)
set(COMPILE_PREFIX /opt/homebrew/bin/)
endif ()
set(CMAKE_C_COMPILER ${COMPILE_PREFIX}arm-none-eabi-gcc)
set(CMAKE_CXX_COMPILER ${COMPILE_PREFIX}arm-none-eabi-g++)
set(CMAKE_ASM_COMPILER ${COMPILE_PREFIX}arm-none-eabi-gcc)
set(CMAKE_AR ${COMPILE_PREFIX}arm-none-eabi-ar)
set(CMAKE_OBJCOPY ${COMPILE_PREFIX}arm-none-eabi-objcopy)
set(CMAKE_OBJDUMP ${COMPILE_PREFIX}arm-none-eabi-objdump)
set(SIZE ${COMPILE_PREFIX}arm-none-eabi-size)
# add definition for filex
add_definitions(-DFX_INCLUDE_USER_DEFINE_FILE)
include_directories(
${CMAKE_CURRENT_LIST_DIR}/includes
${CMAKE_CURRENT_LIST_DIR}/includes/u575xx
${CMAKE_CURRENT_LIST_DIR}/includes/lowlevel
${CMAKE_CURRENT_LIST_DIR}/CMSIS/Include
${CMAKE_CURRENT_LIST_DIR}/filex/common/inc
${CMAKE_CURRENT_LIST_DIR}/filex/common/
${CMAKE_CURRENT_LIST_DIR}/filex/ports/generic/inc
)
file(GLOB_RECURSE LIB_SOURCES
"${CMAKE_CURRENT_LIST_DIR}/src/*.c"
"${CMAKE_CURRENT_LIST_DIR}/src/*.cpp"
"${CMAKE_CURRENT_LIST_DIR}/filex/common/src/*.c"
"${CMAKE_CURRENT_LIST_DIR}/startup/startup_stm32u575zitxq.s"
)
message(STATUS "CMAKE_CURRENT_LIST_DIR: ${CMAKE_CURRENT_LIST_DIR}")
#Uncomment for hardware floating point
# add_compile_definitions(ARM_MATH_CM4;ARM_MATH_MATRIX_CHECK;ARM_MATH_ROUNDING)
add_compile_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)
add_link_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)
add_compile_options(-mcpu=cortex-m33 -mthumb -mthumb-interwork)
add_compile_options(-ffunction-sections -fdata-sections -fno-common -fmessage-length=0)
# Enable assembler files preprocessing
add_compile_options($<$<COMPILE_LANGUAGE:ASM>:-x$<SEMICOLON>assembler-with-cpp>)
# add link script
set(LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/link_script/STM32U575ZITXQ_FLASH.ld)
# add link options
add_link_options(-Wall -Wl,-gc-sections,--print-memory-usage,-Map=${PROJECT_BINARY_DIR}/${PROJECT_NAME}.map)
add_link_options(-mcpu=cortex-m33 -mthumb -mthumb-interwork)
add_link_options(-T ${LINKER_SCRIPT})
add_definitions(-DSTM32U575xx)
# set(LIB_BIN ${CMAKE_CURRENT_LIST_DIR}/libSTM32U5.a)

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---
Language: Cpp
# BasedOnStyle: LLVM
AccessModifierOffset: -2
AlignAfterOpenBracket: Align
AlignArrayOfStructures: None
AlignConsecutiveMacros: None
AlignConsecutiveAssignments: None
AlignConsecutiveBitFields: None
AlignConsecutiveDeclarations: None
AlignEscapedNewlines: Right
AlignOperands: Align
AlignTrailingComments: true
AllowAllArgumentsOnNextLine: true
AllowAllParametersOfDeclarationOnNextLine: true
AllowShortEnumsOnASingleLine: true
AllowShortBlocksOnASingleLine: true
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: All
AllowShortLambdasOnASingleLine: All
AllowShortIfStatementsOnASingleLine: Always
AllowShortLoopsOnASingleLine: true
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: MultiLine
AttributeMacros:
- __capability
BinPackArguments: true
BinPackParameters: true
BraceWrapping:
AfterCaseLabel: false
AfterClass: false
AfterControlStatement: Never
AfterEnum: false
AfterFunction: false
AfterNamespace: false
AfterObjCDeclaration: false
AfterStruct: false
AfterUnion: false
AfterExternBlock: false
BeforeCatch: false
BeforeElse: false
BeforeLambdaBody: false
BeforeWhile: false
IndentBraces: false
SplitEmptyFunction: true
SplitEmptyRecord: true
SplitEmptyNamespace: true
BreakBeforeBinaryOperators: None
BreakBeforeConceptDeclarations: true
BreakBeforeBraces: Attach
BreakBeforeInheritanceComma: false
BreakInheritanceList: BeforeColon
BreakBeforeTernaryOperators: true
BreakConstructorInitializersBeforeComma: false
BreakConstructorInitializers: BeforeColon
BreakAfterJavaFieldAnnotations: false
BreakStringLiterals: true
ColumnLimit: 100
CommentPragmas: '^ IWYU pragma:'
QualifierAlignment: Leave
CompactNamespaces: false
ConstructorInitializerIndentWidth: 4
ContinuationIndentWidth: 4
Cpp11BracedListStyle: true
DeriveLineEnding: true
DerivePointerAlignment: false
DisableFormat: false
EmptyLineAfterAccessModifier: Never
EmptyLineBeforeAccessModifier: LogicalBlock
ExperimentalAutoDetectBinPacking: false
PackConstructorInitializers: BinPack
BasedOnStyle: ''
ConstructorInitializerAllOnOneLineOrOnePerLine: false
AllowAllConstructorInitializersOnNextLine: true
FixNamespaceComments: true
ForEachMacros:
- foreach
- Q_FOREACH
- BOOST_FOREACH
IfMacros:
- KJ_IF_MAYBE
IncludeBlocks: Preserve
IncludeCategories:
- Regex: '^"(llvm|llvm-c|clang|clang-c)/'
Priority: 2
SortPriority: 0
CaseSensitive: false
- Regex: '^(<|"(gtest|gmock|isl|json)/)'
Priority: 3
SortPriority: 0
CaseSensitive: false
- Regex: '.*'
Priority: 1
SortPriority: 0
CaseSensitive: false
IncludeIsMainRegex: '(Test)?$'
IncludeIsMainSourceRegex: ''
IndentAccessModifiers: false
IndentCaseLabels: false
IndentCaseBlocks: false
IndentGotoLabels: true
IndentPPDirectives: None
IndentExternBlock: AfterExternBlock
IndentRequires: false
IndentWidth: 4
IndentWrappedFunctionNames: false
InsertTrailingCommas: None
JavaScriptQuotes: Leave
JavaScriptWrapImports: true
KeepEmptyLinesAtTheStartOfBlocks: true
LambdaBodyIndentation: Signature
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
NamespaceIndentation: None
ObjCBinPackProtocolList: Auto
ObjCBlockIndentWidth: 2
ObjCBreakBeforeNestedBlockParam: true
ObjCSpaceAfterProperty: false
ObjCSpaceBeforeProtocolList: true
PenaltyBreakAssignment: 2
PenaltyBreakBeforeFirstCallParameter: 19
PenaltyBreakComment: 300
PenaltyBreakFirstLessLess: 120
PenaltyBreakOpenParenthesis: 0
PenaltyBreakString: 1000
PenaltyBreakTemplateDeclaration: 10
PenaltyExcessCharacter: 1000000
PenaltyReturnTypeOnItsOwnLine: 60
PenaltyIndentedWhitespace: 0
PointerAlignment: Right
PPIndentWidth: -1
ReferenceAlignment: Pointer
ReflowComments: true
RemoveBracesLLVM: false
SeparateDefinitionBlocks: Always
ShortNamespaceLines: 1
SortIncludes: CaseSensitive
SortJavaStaticImport: Before
SortUsingDeclarations: true
SpaceAfterCStyleCast: false
SpaceAfterLogicalNot: false
SpaceAfterTemplateKeyword: true
SpaceBeforeAssignmentOperators: true
SpaceBeforeCaseColon: false
SpaceBeforeCpp11BracedList: false
SpaceBeforeCtorInitializerColon: true
SpaceBeforeInheritanceColon: true
SpaceBeforeParens: ControlStatements
SpaceBeforeParensOptions:
AfterControlStatements: true
AfterForeachMacros: true
AfterFunctionDefinitionName: false
AfterFunctionDeclarationName: false
AfterIfMacros: true
AfterOverloadedOperator: false
BeforeNonEmptyParentheses: false
SpaceAroundPointerQualifiers: Default
SpaceBeforeRangeBasedForLoopColon: true
SpaceInEmptyBlock: false
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: Never
SpacesInConditionalStatement: false
SpacesInContainerLiterals: true
SpacesInCStyleCastParentheses: false
SpacesInLineCommentPrefix:
Minimum: 1
Maximum: -1
SpacesInParentheses: false
SpacesInSquareBrackets: false
SpaceBeforeSquareBrackets: false
BitFieldColonSpacing: Both
Standard: Latest
StatementAttributeLikeMacros:
- Q_EMIT
StatementMacros:
- Q_UNUSED
- QT_REQUIRE_VERSION
TabWidth: 4
UseCRLF: false
UseTab: Never
WhitespaceSensitiveMacros:
- STRINGIZE
- PP_STRINGIZE
- BOOST_PP_STRINGIZE
- NS_SWIFT_NAME
- CF_SWIFT_NAME
...

3
stm32u5/cmake/compile_options.cmake Normal file
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add_compile_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)
add_compile_options(-mcpu=cortex-m33 -mthumb -mthumb-interwork)
add_compile_options(-ffunction-sections -fdata-sections -fno-common -fmessage-length=0)

3
stm32u5/cmake/link_options.cmake Normal file
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@ -0,0 +1,3 @@
add_link_options(-Wall -Wl,-gc-sections,--print-memory-usage,-Map=${PROJECT_BINARY_DIR}/${PROJECT_NAME}.map)
add_link_options(-mcpu=cortex-m33 -mthumb -mthumb-interwork)
add_link_options(-T ${LINKER_SCRIPT})

12
stm32u5/cmake/set_compiler.cmake Normal file
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set(COMPILE_PREFIX "")
if (APPLE)
set(COMPILE_PREFIX /opt/homebrew/bin/)
endif ()
set(CMAKE_C_COMPILER ${COMPILE_PREFIX}arm-none-eabi-gcc)
set(CMAKE_CXX_COMPILER ${COMPILE_PREFIX}arm-none-eabi-g++)
set(CMAKE_ASM_COMPILER ${COMPILE_PREFIX}arm-none-eabi-gcc)
set(CMAKE_AR ${COMPILE_PREFIX}arm-none-eabi-ar)
set(CMAKE_OBJCOPY ${COMPILE_PREFIX}arm-none-eabi-objcopy)
set(CMAKE_OBJDUMP ${COMPILE_PREFIX}arm-none-eabi-objdump)
set(SIZE ${COMPILE_PREFIX}arm-none-eabi-size)

0
stm32u5/cmake_options.cmake Normal file
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41
stm32u5/examples/cam_board/5640/CMakeLists.txt Executable file
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cmake_minimum_required(VERSION 3.23)
set(CMAKE_C_COMPILER_WORKS 1)
set(CMAKE_CXX_COMPILER_WORKS 1)
project(ov5640 LANGUAGES C CXX ASM)
set(EXAMPLE_NAME "ov5640")
set(CMAKE_EXPORT_COMPILE_COMMANDS on) # for clangd
### set includes and library
set(Stm32U5Lib_DIR ../../../)
find_package(Stm32U5Lib REQUIRED)
include_directories(../)
file(GLOB_RECURSE SOURCES
main.cpp
../custom_prephrals.cpp
./fx_stm32_sd_driver.cpp
../../../startup/startup_stm32u575zitxq.s
)
#add_executable(${EXAMPLE_NAME}.elf ${SOURCES} ${LINKER_SCRIPT} ${LIB_BIN})
# if LIB_SOURCES is not empty, then add it to the target
if(NOT LIB_SOURCES)
message(STATUS "LIB_SOURCES is empty")
add_executable(${EXAMPLE_NAME}.elf ${SOURCES} ${LINKER_SCRIPT})
# add the library to the target
target_link_libraries(${EXAMPLE_NAME}.elf ${LIB_BIN})
else()
message(STATUS "LIB_SOURCES is not empty")
add_executable(${EXAMPLE_NAME}.elf ${SOURCES} ${LINKER_SCRIPT} ${LIB_SOURCES})
endif()
set(HEX_FILE ${EXAMPLE_NAME}.hex)
set(BIN_FILE ${EXAMPLE_NAME}.bin)
add_custom_command(TARGET ${EXAMPLE_NAME}.elf POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${HEX_FILE}
COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${BIN_FILE}
COMMENT "Building ${HEX_FILE}
Building ${BIN_FILE}")

270
stm32u5/examples/cam_board/5640/fx_stm32_sd_driver.cpp Executable file
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#include "fx_api.h"
#include "sdmmc.h"
#include <stdio.h>
#include "prepherials.h"
extern "C" {
UINT
_fx_partition_offset_calculate(void *partition_sector, UINT partition, ULONG *partition_start, ULONG *partition_size);
ULONG partition_start;
ULONG partition_size;
VOID fx_ggeta_driver(FX_MEDIA *media_ptr) {
hal_status_e ret;
switch (media_ptr->fx_media_driver_request) {
case FX_DRIVER_INIT: {
// sdcard will be init_old by the user sperately
media_ptr->fx_media_driver_status = FX_SUCCESS;
break;
}
case FX_DRIVER_UNINIT:
break;
case FX_DRIVER_READ:
ret = sdmmc2.sdmmc_read_multiple_block((uint32_t) media_ptr->fx_media_driver_buffer,
media_ptr->fx_media_driver_logical_sector +
media_ptr->fx_media_hidden_sectors,
media_ptr->fx_media_driver_sectors);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
case FX_DRIVER_WRITE:
ret = sdmmc2.sdmmc_write_multiple_block((uint32_t) media_ptr->fx_media_driver_buffer,
media_ptr->fx_media_driver_logical_sector +
media_ptr->fx_media_hidden_sectors,
media_ptr->fx_media_driver_sectors);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
case FX_DRIVER_BOOT_READ:
ret = sdmmc2.sdmmc_read_multiple_block((uint32_t) media_ptr->fx_media_driver_buffer, 0,
media_ptr->fx_media_driver_sectors);
_fx_partition_offset_calculate(media_ptr->fx_media_driver_buffer, 0, &partition_start, &partition_size);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else {
media_ptr->fx_media_driver_status = FX_IO_ERROR;
return;
}
ret = sdmmc2.sdmmc_read_multiple_block((uint32_t) media_ptr->fx_media_driver_buffer, partition_start,
media_ptr->fx_media_driver_sectors);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
case FX_DRIVER_BOOT_WRITE: {
// ret = sdmmc_write_multiple_block(sd1,
// (uint32_t) media_ptr->fx_media_driver_buffer,
// partition_start,
// 1);
ret = sdmmc2.sdmmc_write_single_block((uint32_t) media_ptr->fx_media_driver_buffer, partition_start);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
}
default:
media_ptr->fx_media_driver_status = FX_NOT_IMPLEMENTED;
break;
}
}
}
//void fx_stm32_sd_driver(FX_MEDIA *media_ptr) {
// UINT status;
// UINT unaligned_buffer;
// ULONG partition_start;
// ULONG partition_size;
//
//#if (FX_STM32_SD_INIT == 0)
// /* the SD was initialized by the application */
// is_initialized = 1;
//#endif
// /* before performing any operation, check the status of the SD IP */
// if (is_initialized == 1) {
// if (check_sd_status(FX_STM32_SD_INSTANCE) != 0) {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// return;
// }
// }
//
//#if (FX_STM32_SD_DMA_API == 1)
// /* the SD DMA requires a 4-byte aligned buffers */
// unaligned_buffer = (UINT)(media_ptr->fx_media_driver_buffer) & 0x3;
//#else
// /* if the DMA is not used there isn't any constraint on buffer alignment */
// unaligned_buffer = 0;
//#endif
// /* Process the driver request specified in the media control block. */
// switch (media_ptr->fx_media_driver_request) {
// case FX_DRIVER_INIT: {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
//
// FX_STM32_SD_PRE_INIT(media_ptr);
//
//#if (FX_STM32_SD_INIT == 1)
// /* Initialize the SD instance */
// if (is_initialized == 0)
// {
// status = fx_stm32_sd_init(FX_STM32_SD_INSTANCE);
//
// if (status == 0)
// {
// is_initialized = 1;
// }
// else
// {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// }
// }
//#endif
// /* call post init_old user macro */
// FX_STM32_SD_POST_INIT(media_ptr);
// break;
// }
//
// case FX_DRIVER_UNINIT: {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
//
//#if (FX_STM32_SD_INIT == 1)
// status = fx_stm32_sd_deinit(FX_STM32_SD_INSTANCE);
//
// if (status != 0)
// {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// }
// else
// {
// is_initialized = 0;
// }
//#endif
// /* call post deinit processing */
// FX_STM32_SD_POST_DEINIT(media_ptr);
//
// break;
// }
//
// case FX_DRIVER_READ: {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
//
// if (sd_read_data(media_ptr, media_ptr->fx_media_driver_logical_sector + media_ptr->fx_media_hidden_sectors,
// media_ptr->fx_media_driver_sectors, unaligned_buffer) == FX_SUCCESS) {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// }
//
// break;
// }
//
// case FX_DRIVER_WRITE: {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
//
// if (sd_write_data(media_ptr, media_ptr->fx_media_driver_logical_sector + media_ptr->fx_media_hidden_sectors,
// media_ptr->fx_media_driver_sectors, unaligned_buffer) == FX_SUCCESS) {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// }
//
// break;
// }
//
// case FX_DRIVER_FLUSH: {
// /* Return driver success. */
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// break;
// }
//
// case FX_DRIVER_ABORT: {
// /* Return driver success. */
// media_ptr->fx_media_driver_status = FX_SUCCESS;
//
// FX_STM32_SD_POST_ABORT(media_ptr);
// break;
// }
//
// case FX_DRIVER_BOOT_READ: {
// /* the boot sector is the sector zero */
// status = sd_read_data(media_ptr, 0, media_ptr->fx_media_driver_sectors, unaligned_buffer);
//
// if (status != FX_SUCCESS) {
// media_ptr->fx_media_driver_status = status;
// break;
// }
//
// /* Check if the sector 0 is the actual boot sector, otherwise calculate the offset into it.
// Please note that this should belong to higher level of MW to do this check and it is here
// as a temporary work solution */
//
// partition_start = 0;
//
// status = _fx_partition_offset_calculate(media_ptr->fx_media_driver_buffer, 0,
// &partition_start, &partition_size);
//
// /* Check partition read error. */
// if (status) {
// /* Unsuccessful driver request. */
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// break;
// }
//
// /* Now determine if there is a partition... */
// if (partition_start) {
//
// if (check_sd_status(FX_STM32_SD_INSTANCE) != 0) {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// break;
// }
//
// /* Yes, now lets read the actual boot record. */
// status = sd_read_data(media_ptr, partition_start, media_ptr->fx_media_driver_sectors, unaligned_buffer);
//
// if (status != FX_SUCCESS) {
// media_ptr->fx_media_driver_status = status;
// break;
// }
// }
//
// /* Successful driver request. */
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// break;
// }
//
// case FX_DRIVER_BOOT_WRITE: {
// status = sd_write_data(media_ptr, 0, media_ptr->fx_media_driver_sectors, unaligned_buffer);
//
// media_ptr->fx_media_driver_status = status;
//
// break;
// }
//
// default: {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// break;
// }
// }
//}
/**
* @brief Read data from uSD into destination buffer
* @param FX_MEDIA *media_ptr a pointer the main FileX structure
* @param ULONG start_sector first sector to start reading from
* @param UINT num_sectors number of sectors to be read
* @param UINT use_scratch_buffer to enable scratch buffer usage or not.
* @retval FX_SUCCESS on success FX_BUFFER_ERROR / FX_ACCESS_ERROR / FX_IO_ERROR otherwise
*/
//static UINT sd_read_data(FX_MEDIA *media_ptr, ULONG start_sector, UINT num_sectors, UINT use_scratch_buffer)
/**
* @brief write data buffer into the uSD
* @param FX_MEDIA *media_ptr a pointer the main FileX structure
* @param ULONG start_sector first sector to start writing from
* @param UINT num_sectors number of sectors to be written
* @param UINT use_scratch_buffer to enable scratch buffer usage or not.
* @retval FX_SUCCESS on success FX_BUFFER_ERROR / FX_ACCESS_ERROR / FX_IO_ERROR otherwise
*/
// static UINT sd_write_data(FX_MEDIA *media_ptr, ULONG start_sector, UINT num_sectors, UINT use_scratch_buffer);

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stm32u5/examples/cam_board/5640/main.cpp Executable file
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#include "bsp.h"
#include "ov5640.h"
#include "prepherials.h"
#include <string>
#include "dcmi.hpp"
#include "custom_prephrals.h"
#include "ov5640_configs.h"
uint32_t picture[PICTURE_BUFFER_SIZE];
#define OV5640_I2C_ADDR (0x78)
#include "fx_api.h"
extern "C" {
VOID fx_ggeta_driver(FX_MEDIA *media_ptr);
}
FX_MEDIA sdio_disk;
FX_FILE file;
UINT status;
UINT media_memory[1024];
hal_status_e ov5640_read_reg(uint16_t reg[2]) {
uint8_t reg_addr[2];
reg_addr[0] = (reg[0] >> 8) & 0xFF;
reg_addr[1] = reg[0] & 0xFF;
auto ret = cam_i2c.send(OV5640_I2C_ADDR, reg_addr, 2);
uint8_t data;
ret = cam_i2c.read(OV5640_I2C_ADDR, &data, 1);
reg[1] = (uint16_t) data;
return HAL_OK;
}
hal_status_e ov5640_read_id() {
uint8_t data[3];
data[0] = 0x30, data[1] = 0x0A;
uint16_t reg[2] = {0x300A, 0};
ov5640_read_reg(reg);
reg[0] = 0x300B;
ov5640_read_reg(reg);
return HAL_OK;
}
hal_status_e ov5640_write_reg(const uint16_t reg[][2], uint16_t len) {
for (int i = 0; i < len; i++) {
uint8_t data[3];
data[0] = (reg[i][0] >> 8) & 0xFF;
data[1] = reg[i][0] & 0xFF;
data[2] = reg[i][1] & 0xFF;
// wait for receive complete
cam_i2c.send(OV5640_I2C_ADDR, data, 3);
}
return HAL_OK;
}
int main() {
cam_board_init();
// delay.ms(20); // some delay for camera to be ready
// delay_ms(200, true);
// auto ret = sdmmc2.sdmmc_init();
// while (ret != HAL_OK)
// ret = sdmmc2.sdmmc_init();
// delay.ms(20); // some delay for camera to be ready
// status = fx_media_open(&sdio_disk, "STM32_SDIO", fx_ggeta_driver, 0, (VOID *) media_memory,
// sizeof(media_memory));
led1.set_high();
// sdmmc2.sdmmc_init();
// while(1);
ov5640_read_id();
// cam_pdwn.set_high();
// config camera
ov5640_write_reg(OV5640_Common, sizeof(OV5640_Common));
ov5640_write_reg(OV5640_PF_JPEG, sizeof(OV5640_PF_JPEG));
// setup for JPEG mode
uint16_t tmp_addr[1][2] = {{OV5640_TIMING_TC_REG21, 0xA8}};
IF_ERROR_STUCK(ov5640_read_reg(tmp_addr[0]));
tmp_addr[0][1] |= (uint8_t) (1 << 5);
IF_ERROR_STUCK(ov5640_write_reg(tmp_addr, 1));
tmp_addr[0][0] = OV5640_SYSREM_RESET02;
IF_ERROR_STUCK(ov5640_read_reg(tmp_addr[0]));
tmp_addr[0][1] &= ~((1 << 2) | (1 << 3) | (1 << 4));
IF_ERROR_STUCK(ov5640_write_reg(tmp_addr, 1));
tmp_addr[0][0] = OV5640_CLOCK_ENABLE02;
IF_ERROR_STUCK(ov5640_read_reg(tmp_addr[0]));
tmp_addr[0][1] |= (1 << 3) | (1 << 5);
IF_ERROR_STUCK(ov5640_write_reg(tmp_addr, 1));
// end of config camera
dcmi.init_5640(&dma10, picture, PICTURE_BUFFER_SIZE);
while (true) {
cam_pdwn.set_low();
led1.set_low();
if (dcmi.capture_block() == HAL_OK) {
delay.ms(500);
cam_pdwn.set_high();
led1.set_high();
delay.ms(500);
// save picture
dcmi_buffer buf = dcmi.dcmi_get_buf();
// uint32_t * buf = dcmi.dcmi_get_buf();
static int pic_cnt = 0;
std::string file_name = "picture" + std::to_string(pic_cnt) + ".jpg";
pic_cnt++;
status = fx_file_create(&sdio_disk, (char *) file_name.c_str());
if (status == FX_ALREADY_CREATED) {
// delete file and create empty file
status = fx_file_delete(&sdio_disk, (char *) file_name.c_str());
status = fx_file_create(&sdio_disk, (char *) file_name.c_str());
}
status = fx_file_open(&sdio_disk, &file, (char *) file_name.c_str(), FX_OPEN_FOR_WRITE);
status = fx_file_seek(&file, 0);
status = fx_file_write(&file, (uint8_t *) dcmi.dcmi_get_buf().data, dcmi.dcmi_get_buf().picture_length);
status = fx_file_close(&file);
}
};
}

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#include "ov5640_configs.h"
#include "ov5640.h"
#include "prepherials.h"
//#include "tim.h"
//#include "i2c.h"
//#include "dma.h"
//#include "uart.h"
#include "bsp.h"
#include "delay.h"
#include "global_variable.h"
#define OV5640_I2C_ADDR 0x78
__WARN_UNUSED_RESULT hal_status_e ov5640_read_reg(uint16_t reg[2]) {
// while (READ_BIT(i2c1_p->event, I2C_SEND_RECEIVE_COMPLETE) == 0);
uint8_t reg_addr[2];
reg_addr[0] = (reg[0] >> 8) & 0xFF;
reg_addr[1] = reg[0] & 0xFF;
i2c1.send_it_dep(OV5640_I2C_ADDR, reg_addr, 2, 10);
i2c1.read_block_dep(OV5640_I2C_ADDR, 1, 10);
uint8_t tmp_data;
i2c1.i2c_wait_for_transfer_complete(10);
i2c1.recv_queue_dep.pop(&tmp_data);
reg[1] = (uint16_t) tmp_data;
return HAL_OK;
}
__WARN_UNUSED_RESULT hal_status_e ov5640_write_reg(const uint16_t reg[][2], uint16_t len) {
for (int i = 0; i < len; i++) {
uint8_t data[3];
data[0] = (reg[i][0] >> 8) & 0xFF;
data[1] = reg[i][0] & 0xFF;
data[2] = reg[i][1] & 0xFF;
// wait for receive complete
i2c1.send_it_dep(OV5640_I2C_ADDR, data, 3, 10);
}
return HAL_OK;
}
void camera_sleep() {
pf.set_high(0);
}
void camera_wakeup() {
pf.set_low(0);
}
void camera_clock_init() {
pe.init(9, AF, 1); // PE9 ------> TIM1_CH1 for camera clock
// tim_set_gpio_ch1();
// timer_init_default(timer1);
tim1.init_default();
// timer_set_pwm(timer1, CH1, 4, 4);
tim1.set_pwm(CH1, 4, 4);
// timer_enable_output(timer1, CH1);
tim1.enable_output(CH1);
}
void camera_uart_int() {
// IF_ERROR_STUCK(uart_gpio_init(usart1_p, 0));
// IF_ERROR_STUCK(uart_init(usart1_p, 115200, 50, 20));
}
void camera_i2c_init() {
// IF_ERROR_STUCK(i2c_gpio_init(i2c1_p, 0));
// IF_ERROR_STUCK(i2c_init(i2c1_p, 20, 20));
}
void camera_sleep_init() {
// IF_ERROR_STUCK(gpio_init(gpiof_p, GGPIO_PIN_0, OUTPUT, PULL_PUSH, VERY_HIGH_SPEED, 0));
}
void camera_read_id() {
uint8_t data[3];
data[0] = 0x30, data[1] = 0x0A;
i2c1.send_it_dep(OV5640_I2C_ADDR, data, 2, 10);
i2c1.read_block_dep(OV5640_I2C_ADDR, 1, 10);
data[0] = 0x30, data[1] = 0x0B;
i2c1.send_it_dep(OV5640_I2C_ADDR, data, 2, 10);
i2c1.read_block_dep(OV5640_I2C_ADDR, 1, 10);
// I should have read 0x56 and 0x40 (I check this use debug mode)
}
void camera_init() {
camera_clock_init();
camera_uart_int();
camera_i2c_init();
camera_sleep_init();
IF_ERROR_STUCK(ov5640_write_reg(OV5640_Common, sizeof(OV5640_Common))); // init_old camera
IF_ERROR_STUCK(ov5640_write_reg(OV5640_PF_JPEG, sizeof(OV5640_PF_JPEG)));
uint16_t tmp_addr[1][2] = {{OV5640_TIMING_TC_REG21, 0xA8}};
// setup for jpeg mode
IF_ERROR_STUCK(ov5640_read_reg(tmp_addr[0]));
tmp_addr[0][1] |= (uint8_t) (1 << 5);
IF_ERROR_STUCK(ov5640_write_reg(tmp_addr, 1));
tmp_addr[0][0] = OV5640_SYSREM_RESET02;
IF_ERROR_STUCK(ov5640_read_reg(tmp_addr[0]));
tmp_addr[0][1] &= ~((1 << 2) | (1 << 3) | (1 << 4));
IF_ERROR_STUCK(ov5640_write_reg(tmp_addr, 1));
tmp_addr[0][0] = OV5640_CLOCK_ENABLE02;
IF_ERROR_STUCK(ov5640_read_reg(tmp_addr[0]));
tmp_addr[0][1] |= (1 << 3) | (1 << 5);
IF_ERROR_STUCK(ov5640_write_reg(tmp_addr, 1));
// end setup for jpeg mode
// dma_s *dcmi_dma = dma1_p;
dcmi_gpio_setup();
dma10.init(86,
DMA_DATA_WIDTH_32_BITS, DMA_DATA_WIDTH_32_BITS,
DMA_ADDR_FIX, DMA_ADDR_INC,
DMA_TYPE_PREPHERIAL, DMA_TYPE_MEMORY, PICTURE_BUFFER_SIZE * 4);
dcmi.init_old();
}

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stm32u5/examples/cam_board/5640/ov5640.h Executable file
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#include <stdint.h>
#ifndef STM32U5_OV5640_H
#define STM32U5_OV5640_H
#define OV5640_SYSREM_RESET00 0x3000U
#define OV5640_SYSREM_RESET01 0x3001U
#define OV5640_SYSREM_RESET02 0x3002U
#define OV5640_SYSREM_RESET03 0x3003U
#define OV5640_CLOCK_ENABLE00 0x3004U
#define OV5640_CLOCK_ENABLE01 0x3005U
#define OV5640_CLOCK_ENABLE02 0x3006U
#define OV5640_CLOCK_ENABLE03 0x3007U
#define OV5640_SYSTEM_CTROL0 0x3008U
#define OV5640_CHIP_ID_HIGH_BYTE 0x300AU
#define OV5640_CHIP_ID_LOW_BYTE 0x300BU
#define OV5640_MIPI_CONTROL00 0x300EU
#define OV5640_PAD_OUTPUT_ENABLE00 0x3016U
#define OV5640_PAD_OUTPUT_ENABLE01 0x3017U
#define OV5640_PAD_OUTPUT_ENABLE02 0x3018U
#define OV5640_PAD_OUTPUT_VALUE00 0x3019U
#define OV5640_PAD_OUTPUT_VALUE01 0x301AU
#define OV5640_PAD_OUTPUT_VALUE02 0x301BU
#define OV5640_PAD_SELECT00 0x301CU
#define OV5640_PAD_SELECT01 0x301DU
#define OV5640_PAD_SELECT02 0x301EU
#define OV5640_CHIP_REVISION 0x302AU
#define OV5640_PAD_CONTROL00 0x301CU
#define OV5640_SC_PWC 0x3031U
#define OV5640_SC_PLL_CONTRL0 0x3034U
#define OV5640_SC_PLL_CONTRL1 0x3035U
#define OV5640_SC_PLL_CONTRL2 0x3036U
#define OV5640_SC_PLL_CONTRL3 0x3037U
#define OV5640_SC_PLL_CONTRL4 0x3038U
#define OV5640_SC_PLL_CONTRL5 0x3039U
#define OV5640_SC_PLLS_CTRL0 0x303AU
#define OV5640_SC_PLLS_CTRL1 0x303BU
#define OV5640_SC_PLLS_CTRL2 0x303CU
#define OV5640_SC_PLLS_CTRL3 0x303DU
#define OV5640_IO_PAD_VALUE00 0x3050U
#define OV5640_IO_PAD_VALUE01 0x3051U
#define OV5640_IO_PAD_VALUE02 0x3052U
/* SCCB control [0x3100 ~ 0x3108] */
#define OV5640_SCCB_ID 0x3100U
#define OV5640_SCCB_SYSTEM_CTRL0 0x3102U
#define OV5640_SCCB_SYSTEM_CTRL1 0x3103U
#define OV5640_SYSTEM_ROOT_DIVIDER 0x3108U
/* SRB control [0x3200 ~ 0x3213] */
#define OV5640_GROUP_ADDR0 0x3200U
#define OV5640_GROUP_ADDR1 0x3201U
#define OV5640_GROUP_ADDR2 0x3202U
#define OV5640_GROUP_ADDR3 0x3203U
#define OV5640_SRM_GROUP_ACCESS 0x3212U
#define OV5640_SRM_GROUP_STATUS 0x3213U
/* AWB gain control [0x3400 ~ 0x3406] */
#define OV5640_AWB_R_GAIN_MSB 0x3400U
#define OV5640_AWB_R_GAIN_LSB 0x3401U
#define OV5640_AWB_G_GAIN_MSB 0x3402U
#define OV5640_AWB_G_GAIN_LSB 0x3403U
#define OV5640_AWB_B_GAIN_MSB 0x3404U
#define OV5640_AWB_B_GAIN_LSB 0x3405U
#define OV5640_AWB_MANUAL_CONTROL 0x3406U
/* AEC/AGC control [0x3500 ~ 0x350D] */
#define OV5640_AEC_PK_EXPOSURE_19_16 0x3500U
#define OV5640_AEC_PK_EXPOSURE_HIGH 0x3501U
#define OV5640_AEC_PK_EXPOSURE_LOW 0x3502U
#define OV5640_AEC_PK_MANUAL 0x3503U
#define OV5640_AEC_PK_REAL_GAIN_9_8 0x350AU
#define OV5640_AEC_PK_REAL_GAIN_LOW 0x350BU
#define OV5640_AEC_PK_VTS_HIGH 0x350CU
#define OV5640_AEC_PK_VTS_LOW 0x350DU
/* VCM control [0x3600 ~ 0x3606] */
#define OV5640_VCM_CONTROL_0 0x3602U
#define OV5640_VCM_CONTROL_1 0x3603U
#define OV5640_VCM_CONTROL_2 0x3604U
#define OV5640_VCM_CONTROL_3 0x3605U
#define OV5640_VCM_CONTROL_4 0x3606U
/* timing control [0x3800 ~ 0x3821] */
#define OV5640_TIMING_HS_HIGH 0x3800U
#define OV5640_TIMING_HS_LOW 0x3801U
#define OV5640_TIMING_VS_HIGH 0x3802U
#define OV5640_TIMING_VS_LOW 0x3803U
#define OV5640_TIMING_HW_HIGH 0x3804U
#define OV5640_TIMING_HW_LOW 0x3805U
#define OV5640_TIMING_VH_HIGH 0x3806U
#define OV5640_TIMING_VH_LOW 0x3807U
#define OV5640_TIMING_DVPHO_HIGH 0x3808U
#define OV5640_TIMING_DVPHO_LOW 0x3809U
#define OV5640_TIMING_DVPVO_HIGH 0x380AU
#define OV5640_TIMING_DVPVO_LOW 0x380BU
#define OV5640_TIMING_HTS_HIGH 0x380CU
#define OV5640_TIMING_HTS_LOW 0x380DU
#define OV5640_TIMING_VTS_HIGH 0x380EU
#define OV5640_TIMING_VTS_LOW 0x380FU
#define OV5640_TIMING_HOFFSET_HIGH 0x3810U
#define OV5640_TIMING_HOFFSET_LOW 0x3811U
#define OV5640_TIMING_VOFFSET_HIGH 0x3812U
#define OV5640_TIMING_VOFFSET_LOW 0x3813U
#define OV5640_TIMING_X_INC 0x3814U
#define OV5640_TIMING_Y_INC 0x3815U
#define OV5640_HSYNC_START_HIGH 0x3816U
#define OV5640_HSYNC_START_LOW 0x3817U
#define OV5640_HSYNC_WIDTH_HIGH 0x3818U
#define OV5640_HSYNC_WIDTH_LOW 0x3819U
#define OV5640_TIMING_TC_REG20 0x3820U
#define OV5640_TIMING_TC_REG21 0x3821U
/* AEC/AGC power down domain control [0x3A00 ~ 0x3A25] */
#define OV5640_AEC_CTRL00 0x3A00U
#define OV5640_AEC_CTRL01 0x3A01U
#define OV5640_AEC_CTRL02 0x3A02U
#define OV5640_AEC_CTRL03 0x3A03U
#define OV5640_AEC_CTRL04 0x3A04U
#define OV5640_AEC_CTRL05 0x3A05U
#define OV5640_AEC_CTRL06 0x3A06U
#define OV5640_AEC_CTRL07 0x3A07U
#define OV5640_AEC_B50_STEP_HIGH 0x3A08U
#define OV5640_AEC_B50_STEP_LOW 0x3A09U
#define OV5640_AEC_B60_STEP_HIGH 0x3A0AU
#define OV5640_AEC_B60_STEP_LOW 0x3A0BU
#define OV5640_AEC_AEC_CTRL0C 0x3A0CU
#define OV5640_AEC_CTRL0D 0x3A0DU
#define OV5640_AEC_CTRL0E 0x3A0EU
#define OV5640_AEC_CTRL0F 0x3A0FU
#define OV5640_AEC_CTRL10 0x3A10U
#define OV5640_AEC_CTRL11 0x3A11U
#define OV5640_AEC_CTRL13 0x3A13U
#define OV5640_AEC_MAX_EXPO_HIGH 0x3A14U
#define OV5640_AEC_MAX_EXPO_LOW 0x3A15U
#define OV5640_AEC_CTRL17 0x3A17U
#define OV5640_AEC_GAIN_CEILING_HIGH 0x3A18U
#define OV5640_AEC_GAIN_CEILING_LOW 0x3A19U
#define OV5640_AEC_DIFF_MIN 0x3A1AU
#define OV5640_AEC_CTRL1B 0x3A1BU
#define OV5640_LED_ADD_ROW_HIGH 0x3A1CU
#define OV5640_LED_ADD_ROW_LOW 0x3A1DU
#define OV5640_AEC_CTRL1E 0x3A1EU
#define OV5640_AEC_CTRL1F 0x3A1FU
#define OV5640_AEC_CTRL20 0x3A20U
#define OV5640_AEC_CTRL21 0x3A21U
#define OV5640_AEC_CTRL25 0x3A25U
/* strobe control [0x3B00 ~ 0x3B0C] */
#define OV5640_STROBE_CTRL 0x3B00U
#define OV5640_FREX_EXPOSURE02 0x3B01U
#define OV5640_FREX_SHUTTER_DLY01 0x3B02U
#define OV5640_FREX_SHUTTER_DLY00 0x3B03U
#define OV5640_FREX_EXPOSURE01 0x3B04U
#define OV5640_FREX_EXPOSURE00 0x3B05U
#define OV5640_FREX_CTRL07 0x3B06U
#define OV5640_FREX_MODE 0x3B07U
#define OV5640_FREX_RQST 0x3B08U
#define OV5640_FREX_HREF_DLY 0x3B09U
#define OV5640_FREX_RST_LENGTH 0x3B0AU
#define OV5640_STROBE_WIDTH_HIGH 0x3B0BU
#define OV5640_STROBE_WIDTH_LOW 0x3B0CU
/* 50/60Hz detector control [0x3C00 ~ 0x3C1E] */
#define OV5640_5060HZ_CTRL00 0x3C00U
#define OV5640_5060HZ_CTRL01 0x3C01U
#define OV5640_5060HZ_CTRL02 0x3C02U
#define OV5640_5060HZ_CTRL03 0x3C03U
#define OV5640_5060HZ_CTRL04 0x3C04U
#define OV5640_5060HZ_CTRL05 0x3C05U
#define OV5640_LIGHTMETER1_TH_HIGH 0x3C06U
#define OV5640_LIGHTMETER1_TH_LOW 0x3C07U
#define OV5640_LIGHTMETER2_TH_HIGH 0x3C08U
#define OV5640_LIGHTMETER2_TH_LOW 0x3C09U
#define OV5640_SAMPLE_NUMBER_HIGH 0x3C0AU
#define OV5640_SAMPLE_NUMBER_LOW 0x3C0BU
#define OV5640_SIGMA_DELTA_CTRL0C 0x3C0CU
#define OV5640_SUM50_BYTE4 0x3C0DU
#define OV5640_SUM50_BYTE3 0x3C0EU
#define OV5640_SUM50_BYTE2 0x3C0FU
#define OV5640_SUM50_BYTE1 0x3C10U
#define OV5640_SUM60_BYTE4 0x3C11U
#define OV5640_SUM60_BYTE3 0x3C12U
#define OV5640_SUM60_BYTE2 0x3C13U
#define OV5640_SUM60_BYTE1 0x3C14U
#define OV5640_SUM5060_HIGH 0x3C15U
#define OV5640_SUM5060_LOW 0x3C16U
#define OV5640_BLOCK_CNTR_HIGH 0x3C17U
#define OV5640_BLOCK_CNTR_LOW 0x3C18U
#define OV5640_B6_HIGH 0x3C19U
#define OV5640_B6_LOW 0x3C1AU
#define OV5640_LIGHTMETER_OUTPUT_BYTE3 0x3C1BU
#define OV5640_LIGHTMETER_OUTPUT_BYTE2 0x3C1CU
#define OV5640_LIGHTMETER_OUTPUT_BYTE1 0x3C1DU
#define OV5640_SUM_THRESHOLD 0x3C1EU
/* OTP control [0x3D00 ~ 0x3D21] */
/* MC control [0x3F00 ~ 0x3F0D] */
/* BLC control [0x4000 ~ 0x4033] */
#define OV5640_BLC_CTRL00 0x4000U
#define OV5640_BLC_CTRL01 0x4001U
#define OV5640_BLC_CTRL02 0x4002U
#define OV5640_BLC_CTRL03 0x4003U
#define OV5640_BLC_CTRL04 0x4004U
#define OV5640_BLC_CTRL05 0x4005U
/* frame control [0x4201 ~ 0x4202] */
#define OV5640_FRAME_CTRL01 0x4201U
#define OV5640_FRAME_CTRL02 0x4202U
/* format control [0x4300 ~ 0x430D] */
#define OV5640_FORMAT_CTRL00 0x4300U
#define OV5640_FORMAT_CTRL01 0x4301U
#define OV5640_YMAX_VAL_HIGH 0x4302U
#define OV5640_YMAX_VAL_LOW 0x4303U
#define OV5640_YMIN_VAL_HIGH 0x4304U
#define OV5640_YMIN_VAL_LOW 0x4305U
#define OV5640_UMAX_VAL_HIGH 0x4306U
#define OV5640_UMAX_VAL_LOW 0x4307U
#define OV5640_UMIN_VAL_HIGH 0x4308U
#define OV5640_UMIN_VAL_LOW 0x4309U
#define OV5640_VMAX_VAL_HIGH 0x430AU
#define OV5640_VMAX_VAL_LOW 0x430BU
#define OV5640_VMIN_VAL_HIGH 0x430CU
#define OV5640_VMIN_VAL_LOW 0x430DU
/* JPEG control [0x4400 ~ 0x4431] */
#define OV5640_JPEG_CTRL00 0x4400U
#define OV5640_JPEG_CTRL01 0x4401U
#define OV5640_JPEG_CTRL02 0x4402U
#define OV5640_JPEG_CTRL03 0x4403U
#define OV5640_JPEG_CTRL04 0x4404U
#define OV5640_JPEG_CTRL05 0x4405U
#define OV5640_JPEG_CTRL06 0x4406U
#define OV5640_JPEG_CTRL07 0x4407U
#define OV5640_JPEG_ISI_CTRL1 0x4408U
#define OV5640_JPEG_CTRL09 0x4409U
#define OV5640_JPEG_CTRL0A 0x440AU
#define OV5640_JPEG_CTRL0B 0x440BU
#define OV5640_JPEG_CTRL0C 0x440CU
#define OV5640_JPEG_QT_DATA 0x4410U
#define OV5640_JPEG_QT_ADDR 0x4411U
#define OV5640_JPEG_ISI_DATA 0x4412U
#define OV5640_JPEG_ISI_CTRL2 0x4413U
#define OV5640_JPEG_LENGTH_BYTE3 0x4414U
#define OV5640_JPEG_LENGTH_BYTE2 0x4415U
#define OV5640_JPEG_LENGTH_BYTE1 0x4416U
#define OV5640_JFIFO_OVERFLOW 0x4417U
/* VFIFO control [0x4600 ~ 0x460D] */
#define OV5640_VFIFO_CTRL00 0x4600U
#define OV5640_VFIFO_HSIZE_HIGH 0x4602U
#define OV5640_VFIFO_HSIZE_LOW 0x4603U
#define OV5640_VFIFO_VSIZE_HIGH 0x4604U
#define OV5640_VFIFO_VSIZE_LOW 0x4605U
#define OV5640_VFIFO_CTRL0C 0x460CU
#define OV5640_VFIFO_CTRL0D 0x460DU
/* DVP control [0x4709 ~ 0x4745] */
#define OV5640_DVP_VSYNC_WIDTH0 0x4709U
#define OV5640_DVP_VSYNC_WIDTH1 0x470AU
#define OV5640_DVP_VSYNC_WIDTH2 0x470BU
#define OV5640_PAD_LEFT_CTRL 0x4711U
#define OV5640_PAD_RIGHT_CTRL 0x4712U
#define OV5640_JPG_MODE_SELECT 0x4713U
#define OV5640_656_DUMMY_LINE 0x4715U
#define OV5640_CCIR656_CTRL 0x4719U
#define OV5640_HSYNC_CTRL00 0x471BU
#define OV5640_DVP_VSYN_CTRL 0x471DU
#define OV5640_DVP_HREF_CTRL 0x471FU
#define OV5640_VSTART_OFFSET 0x4721U
#define OV5640_VEND_OFFSET 0x4722U
#define OV5640_DVP_CTRL23 0x4723U
#define OV5640_CCIR656_CTRL00 0x4730U
#define OV5640_CCIR656_CTRL01 0x4731U
#define OV5640_CCIR656_FS 0x4732U
#define OV5640_CCIR656_FE 0x4733U
#define OV5640_CCIR656_LS 0x4734U
#define OV5640_CCIR656_LE 0x4735U
#define OV5640_CCIR656_CTRL06 0x4736U
#define OV5640_CCIR656_CTRL07 0x4737U
#define OV5640_CCIR656_CTRL08 0x4738U
#define OV5640_POLARITY_CTRL 0x4740U
#define OV5640_TEST_PATTERN 0x4741U
#define OV5640_DATA_ORDER 0x4745U
/* MIPI control [0x4800 ~ 0x4837] */
#define OV5640_MIPI_CTRL00 0x4800U
#define OV5640_MIPI_CTRL01 0x4801U
#define OV5640_MIPI_CTRL05 0x4805U
#define OV5640_MIPI_DATA_ORDER 0x480AU
#define OV5640_MIN_HS_ZERO_HIGH 0x4818U
#define OV5640_MIN_HS_ZERO_LOW 0x4819U
#define OV5640_MIN_MIPI_HS_TRAIL_HIGH 0x481AU
#define OV5640_MIN_MIPI_HS_TRAIL_LOW 0x481BU
#define OV5640_MIN_MIPI_CLK_ZERO_HIGH 0x481CU
#define OV5640_MIN_MIPI_CLK_ZERO_LOW 0x481DU
#define OV5640_MIN_MIPI_CLK_PREPARE_HIGH 0x481EU
#define OV5640_MIN_MIPI_CLK_PREPARE_LOW 0x481FU
#define OV5640_MIN_CLK_POST_HIGH 0x4820U
#define OV5640_MIN_CLK_POST_LOW 0x4821U
#define OV5640_MIN_CLK_TRAIL_HIGH 0x4822U
#define OV5640_MIN_CLK_TRAIL_LOW 0x4823U
#define OV5640_MIN_LPX_PCLK_HIGH 0x4824U
#define OV5640_MIN_LPX_PCLK_LOW 0x4825U
#define OV5640_MIN_HS_PREPARE_HIGH 0x4826U
#define OV5640_MIN_HS_PREPARE_LOW 0x4827U
#define OV5640_MIN_HS_EXIT_HIGH 0x4828U
#define OV5640_MIN_HS_EXIT_LOW 0x4829U
#define OV5640_MIN_HS_ZERO_UI 0x482AU
#define OV5640_MIN_HS_TRAIL_UI 0x482BU
#define OV5640_MIN_CLK_ZERO_UI 0x482CU
#define OV5640_MIN_CLK_PREPARE_UI 0x482DU
#define OV5640_MIN_CLK_POST_UI 0x482EU
#define OV5640_MIN_CLK_TRAIL_UI 0x482FU
#define OV5640_MIN_LPX_PCLK_UI 0x4830U
#define OV5640_MIN_HS_PREPARE_UI 0x4831U
#define OV5640_MIN_HS_EXIT_UI 0x4832U
#define OV5640_PCLK_PERIOD 0x4837U
/* ISP frame control [0x4901 ~ 0x4902] */
#define OV5640_ISP_FRAME_CTRL01 0x4901U
#define OV5640_ISP_FRAME_CTRL02 0x4902U
/* ISP top control [0x5000 ~ 0x5063] */
#define OV5640_ISP_CONTROL00 0x5000U
#define OV5640_ISP_CONTROL01 0x5001U
#define OV5640_ISP_CONTROL03 0x5003U
#define OV5640_ISP_CONTROL05 0x5005U
#define OV5640_ISP_MISC0 0x501DU
#define OV5640_ISP_MISC1 0x501EU
#define OV5640_FORMAT_MUX_CTRL 0x501FU
#define OV5640_DITHER_CTRL0 0x5020U
#define OV5640_DRAW_WINDOW_CTRL00 0x5027U
#define OV5640_DRAW_WINDOW_LEFT_CTRL_HIGH 0x5028U
#define OV5640_DRAW_WINDOW_LEFT_CTRL_LOW 0x5029U
#define OV5640_DRAW_WINDOW_RIGHT_CTRL_HIGH 0x502AU
#define OV5640_DRAW_WINDOW_RIGHT_CTRL_LOW 0x502BU
#define OV5640_DRAW_WINDOW_TOP_CTRL_HIGH 0x502CU
#define OV5640_DRAW_WINDOW_TOP_CTRL_LOW 0x502DU
#define OV5640_DRAW_WINDOW_BOTTOM_CTRL_HIGH 0x502EU
#define OV5640_DRAW_WINDOW_BOTTOM_CTRL_LOW 0x502FU
#define OV5640_DRAW_WINDOW_HBW_CTRL_HIGH 0x5030U /* HBW: Horizontal Boundary Width */
#define OV5640_DRAW_WINDOW_HBW_CTRL_LOW 0x5031U
#define OV5640_DRAW_WINDOW_VBW_CTRL_HIGH 0x5032U /* VBW: Vertical Boundary Width */
#define OV5640_DRAW_WINDOW_VBW_CTRL_LOW 0x5033U
#define OV5640_DRAW_WINDOW_Y_CTRL 0x5034U
#define OV5640_DRAW_WINDOW_U_CTRL 0x5035U
#define OV5640_DRAW_WINDOW_V_CTRL 0x5036U
#define OV5640_PRE_ISP_TEST_SETTING1 0x503DU
#define OV5640_ISP_SENSOR_BIAS_I 0x5061U
#define OV5640_ISP_SENSOR_GAIN1_I 0x5062U
#define OV5640_ISP_SENSOR_GAIN2_I 0x5063U
/* AWB control [0x5180 ~ 0x51D0] */
#define OV5640_AWB_CTRL00 0x5180U
#define OV5640_AWB_CTRL01 0x5181U
#define OV5640_AWB_CTRL02 0x5182U
#define OV5640_AWB_CTRL03 0x5183U
#define OV5640_AWB_CTRL04 0x5184U
#define OV5640_AWB_CTRL05 0x5185U
#define OV5640_AWB_CTRL06 0x5186U /* Advanced AWB control registers: 0x5186 ~ 0x5190 */
#define OV5640_AWB_CTRL07 0x5187U
#define OV5640_AWB_CTRL08 0x5188U
#define OV5640_AWB_CTRL09 0x5189U
#define OV5640_AWB_CTRL10 0x518AU
#define OV5640_AWB_CTRL11 0x518BU
#define OV5640_AWB_CTRL12 0x518CU
#define OV5640_AWB_CTRL13 0x518DU
#define OV5640_AWB_CTRL14 0x518EU
#define OV5640_AWB_CTRL15 0x518FU
#define OV5640_AWB_CTRL16 0x5190U
#define OV5640_AWB_CTRL17 0x5191U
#define OV5640_AWB_CTRL18 0x5192U
#define OV5640_AWB_CTRL19 0x5193U
#define OV5640_AWB_CTRL20 0x5194U
#define OV5640_AWB_CTRL21 0x5195U
#define OV5640_AWB_CTRL22 0x5196U
#define OV5640_AWB_CTRL23 0x5197U
#define OV5640_AWB_CTRL24 0x5198U
#define OV5640_AWB_CTRL25 0x5199U
#define OV5640_AWB_CTRL26 0x519AU
#define OV5640_AWB_CTRL27 0x519BU
#define OV5640_AWB_CTRL28 0x519CU
#define OV5640_AWB_CTRL29 0x519DU
#define OV5640_AWB_CTRL30 0x519EU
#define OV5640_AWB_CURRENT_R_GAIN_HIGH 0x519FU
#define OV5640_AWB_CURRENT_R_GAIN_LOW 0x51A0U
#define OV5640_AWB_CURRENT_G_GAIN_HIGH 0x51A1U
#define OV5640_AWB_CURRENT_G_GAIN_LOW 0x51A2U
#define OV5640_AWB_CURRENT_B_GAIN_HIGH 0x51A3U
#define OV5640_AWB_CURRENT_B_GAIN_LOW 0x51A4U
#define OV5640_AWB_AVERAGE_R 0x51A5U
#define OV5640_AWB_AVERAGE_G 0x51A6U
#define OV5640_AWB_AVERAGE_B 0x51A7U
#define OV5640_AWB_CTRL74 0x5180U
/* CIP control [0x5300 ~ 0x530F] */
#define OV5640_CIP_SHARPENMT_TH1 0x5300U
#define OV5640_CIP_SHARPENMT_TH2 0x5301U
#define OV5640_CIP_SHARPENMT_OFFSET1 0x5302U
#define OV5640_CIP_SHARPENMT_OFFSET2 0x5303U
#define OV5640_CIP_DNS_TH1 0x5304U
#define OV5640_CIP_DNS_TH2 0x5305U
#define OV5640_CIP_DNS_OFFSET1 0x5306U
#define OV5640_CIP_DNS_OFFSET2 0x5307U
#define OV5640_CIP_CTRL 0x5308U
#define OV5640_CIP_SHARPENTH_TH1 0x5309U
#define OV5640_CIP_SHARPENTH_TH2 0x530AU
#define OV5640_CIP_SHARPENTH_OFFSET1 0x530BU
#define OV5640_CIP_SHARPENTH_OFFSET2 0x530CU
#define OV5640_CIP_EDGE_MT_AUTO 0x530DU
#define OV5640_CIP_DNS_TH_AUTO 0x530EU
#define OV5640_CIP_SHARPEN_TH_AUTO 0x530FU
/* CMX control [0x5380 ~ 0x538B] */
#define OV5640_CMX_CTRL 0x5380U
#define OV5640_CMX1 0x5381U
#define OV5640_CMX2 0x5382U
#define OV5640_CMX3 0x5383U
#define OV5640_CMX4 0x5384U
#define OV5640_CMX5 0x5385U
#define OV5640_CMX6 0x5386U
#define OV5640_CMX7 0x5387U
#define OV5640_CMX8 0x5388U
#define OV5640_CMX9 0x5389U
#define OV5640_CMXSIGN_HIGH 0x538AU
#define OV5640_CMXSIGN_LOW 0x538BU
/* gamma control [0x5480 ~ 0x5490] */
#define OV5640_GAMMA_CTRL00 0x5480U
#define OV5640_GAMMA_YST00 0x5481U
#define OV5640_GAMMA_YST01 0x5482U
#define OV5640_GAMMA_YST02 0x5483U
#define OV5640_GAMMA_YST03 0x5484U
#define OV5640_GAMMA_YST04 0x5485U
#define OV5640_GAMMA_YST05 0x5486U
#define OV5640_GAMMA_YST06 0x5487U
#define OV5640_GAMMA_YST07 0x5488U
#define OV5640_GAMMA_YST08 0x5489U
#define OV5640_GAMMA_YST09 0x548AU
#define OV5640_GAMMA_YST0A 0x548BU
#define OV5640_GAMMA_YST0B 0x548CU
#define OV5640_GAMMA_YST0C 0x548DU
#define OV5640_GAMMA_YST0D 0x548EU
#define OV5640_GAMMA_YST0E 0x548FU
#define OV5640_GAMMA_YST0F 0x5490U
/* SDE control [0x5580 ~ 0x558C] */
#define OV5640_SDE_CTRL0 0x5580U
#define OV5640_SDE_CTRL1 0x5581U
#define OV5640_SDE_CTRL2 0x5582U
#define OV5640_SDE_CTRL3 0x5583U
#define OV5640_SDE_CTRL4 0x5584U
#define OV5640_SDE_CTRL5 0x5585U
#define OV5640_SDE_CTRL6 0x5586U
#define OV5640_SDE_CTRL7 0x5587U
#define OV5640_SDE_CTRL8 0x5588U
#define OV5640_SDE_CTRL9 0x5589U
#define OV5640_SDE_CTRL10 0x558AU
#define OV5640_SDE_CTRL11 0x558BU
#define OV5640_SDE_CTRL12 0x558CU
/* scale control [0x5600 ~ 0x5606] */
#define OV5640_SCALE_CTRL0 0x5600U
#define OV5640_SCALE_CTRL1 0x5601U
#define OV5640_SCALE_CTRL2 0x5602U
#define OV5640_SCALE_CTRL3 0x5603U
#define OV5640_SCALE_CTRL4 0x5604U
#define OV5640_SCALE_CTRL5 0x5605U
#define OV5640_SCALE_CTRL6 0x5606U
/* AVG control [0x5680 ~ 0x56A2] */
#define OV5640_X_START_HIGH 0x5680U
#define OV5640_X_START_LOW 0x5681U
#define OV5640_Y_START_HIGH 0x5682U
#define OV5640_Y_START_LOW 0x5683U
#define OV5640_X_WINDOW_HIGH 0x5684U
#define OV5640_X_WINDOW_LOW 0x5685U
#define OV5640_Y_WINDOW_HIGH 0x5686U
#define OV5640_Y_WINDOW_LOW 0x5687U
#define OV5640_WEIGHT00 0x5688U
#define OV5640_WEIGHT01 0x5689U
#define OV5640_WEIGHT02 0x568AU
#define OV5640_WEIGHT03 0x568BU
#define OV5640_WEIGHT04 0x568CU
#define OV5640_WEIGHT05 0x568DU
#define OV5640_WEIGHT06 0x568EU
#define OV5640_WEIGHT07 0x568FU
#define OV5640_AVG_CTRL10 0x5690U
#define OV5640_AVG_WIN_00 0x5691U
#define OV5640_AVG_WIN_01 0x5692U
#define OV5640_AVG_WIN_02 0x5693U
#define OV5640_AVG_WIN_03 0x5694U
#define OV5640_AVG_WIN_10 0x5695U
#define OV5640_AVG_WIN_11 0x5696U
#define OV5640_AVG_WIN_12 0x5697U
#define OV5640_AVG_WIN_13 0x5698U
#define OV5640_AVG_WIN_20 0x5699U
#define OV5640_AVG_WIN_21 0x569AU
#define OV5640_AVG_WIN_22 0x569BU
#define OV5640_AVG_WIN_23 0x569CU
#define OV5640_AVG_WIN_30 0x569DU
#define OV5640_AVG_WIN_31 0x569EU
#define OV5640_AVG_WIN_32 0x569FU
#define OV5640_AVG_WIN_33 0x56A0U
#define OV5640_AVG_READOUT 0x56A1U
#define OV5640_AVG_WEIGHT_SUM 0x56A2U
/* LENC control [0x5800 ~ 0x5849] */
#define OV5640_GMTRX00 0x5800U
#define OV5640_GMTRX01 0x5801U
#define OV5640_GMTRX02 0x5802U
#define OV5640_GMTRX03 0x5803U
#define OV5640_GMTRX04 0x5804U
#define OV5640_GMTRX05 0x5805U
#define OV5640_GMTRX10 0x5806U
#define OV5640_GMTRX11 0x5807U
#define OV5640_GMTRX12 0x5808U
#define OV5640_GMTRX13 0x5809U
#define OV5640_GMTRX14 0x580AU
#define OV5640_GMTRX15 0x580BU
#define OV5640_GMTRX20 0x580CU
#define OV5640_GMTRX21 0x580DU
#define OV5640_GMTRX22 0x580EU
#define OV5640_GMTRX23 0x580FU
#define OV5640_GMTRX24 0x5810U
#define OV5640_GMTRX25 0x5811U
#define OV5640_GMTRX30 0x5812U
#define OV5640_GMTRX31 0x5813U
#define OV5640_GMTRX32 0x5814U
#define OV5640_GMTRX33 0x5815U
#define OV5640_GMTRX34 0x5816U
#define OV5640_GMTRX35 0x5817U
#define OV5640_GMTRX40 0x5818U
#define OV5640_GMTRX41 0x5819U
#define OV5640_GMTRX42 0x581AU
#define OV5640_GMTRX43 0x581BU
#define OV5640_GMTRX44 0x581CU
#define OV5640_GMTRX45 0x581DU
#define OV5640_GMTRX50 0x581EU
#define OV5640_GMTRX51 0x581FU
#define OV5640_GMTRX52 0x5820U
#define OV5640_GMTRX53 0x5821U
#define OV5640_GMTRX54 0x5822U
#define OV5640_GMTRX55 0x5823U
#define OV5640_BRMATRX00 0x5824U
#define OV5640_BRMATRX01 0x5825U
#define OV5640_BRMATRX02 0x5826U
#define OV5640_BRMATRX03 0x5827U
#define OV5640_BRMATRX04 0x5828U
#define OV5640_BRMATRX05 0x5829U
#define OV5640_BRMATRX06 0x582AU
#define OV5640_BRMATRX07 0x582BU
#define OV5640_BRMATRX08 0x582CU
#define OV5640_BRMATRX09 0x582DU
#define OV5640_BRMATRX20 0x582EU
#define OV5640_BRMATRX21 0x582FU
#define OV5640_BRMATRX22 0x5830U
#define OV5640_BRMATRX23 0x5831U
#define OV5640_BRMATRX24 0x5832U
#define OV5640_BRMATRX30 0x5833U
#define OV5640_BRMATRX31 0x5834U
#define OV5640_BRMATRX32 0x5835U
#define OV5640_BRMATRX33 0x5836U
#define OV5640_BRMATRX34 0x5837U
#define OV5640_BRMATRX40 0x5838U
#define OV5640_BRMATRX41 0x5839U
#define OV5640_BRMATRX42 0x583AU
#define OV5640_BRMATRX43 0x583BU
#define OV5640_BRMATRX44 0x583CU
#define OV5640_LENC_BR_OFFSET 0x583DU
#define OV5640_MAX_GAIN 0x583EU
#define OV5640_MIN_GAIN 0x583FU
#define OV5640_MIN_Q 0x5840U
#define OV5640_LENC_CTRL59 0x5841U
#define OV5640_BR_HSCALE_HIGH 0x5842U
#define OV5640_BR_HSCALE_LOW 0x5843U
#define OV5640_BR_VSCALE_HIGH 0x5844U
#define OV5640_BR_VSCALE_LOW 0x5845U
#define OV5640_G_HSCALE_HIGH 0x5846U
#define OV5640_G_HSCALE_LOW 0x5847U
#define OV5640_G_VSCALE_HIGH 0x5848U
#define OV5640_G_VSCALE_LOW 0x5849U
/* AFC control [0x6000 ~ 0x603F] */
#define OV5640_AFC_CTRL00 0x6000U
#define OV5640_AFC_CTRL01 0x6001U
#define OV5640_AFC_CTRL02 0x6002U
#define OV5640_AFC_CTRL03 0x6003U
#define OV5640_AFC_CTRL04 0x6004U
#define OV5640_AFC_CTRL05 0x6005U
#define OV5640_AFC_CTRL06 0x6006U
#define OV5640_AFC_CTRL07 0x6007U
#define OV5640_AFC_CTRL08 0x6008U
#define OV5640_AFC_CTRL09 0x6009U
#define OV5640_AFC_CTRL10 0x600AU
#define OV5640_AFC_CTRL11 0x600BU
#define OV5640_AFC_CTRL12 0x600CU
#define OV5640_AFC_CTRL13 0x600DU
#define OV5640_AFC_CTRL14 0x600EU
#define OV5640_AFC_CTRL15 0x600FU
#define OV5640_AFC_CTRL16 0x6010U
#define OV5640_AFC_CTRL17 0x6011U
#define OV5640_AFC_CTRL18 0x6012U
#define OV5640_AFC_CTRL19 0x6013U
#define OV5640_AFC_CTRL20 0x6014U
#define OV5640_AFC_CTRL21 0x6015U
#define OV5640_AFC_CTRL22 0x6016U
#define OV5640_AFC_CTRL23 0x6017U
#define OV5640_AFC_CTRL24 0x6018U
#define OV5640_AFC_CTRL25 0x6019U
#define OV5640_AFC_CTRL26 0x601AU
#define OV5640_AFC_CTRL27 0x601BU
#define OV5640_AFC_CTRL28 0x601CU
#define OV5640_AFC_CTRL29 0x601DU
#define OV5640_AFC_CTRL30 0x601EU
#define OV5640_AFC_CTRL31 0x601FU
#define OV5640_AFC_CTRL32 0x6020U
#define OV5640_AFC_CTRL33 0x6021U
#define OV5640_AFC_CTRL34 0x6022U
#define OV5640_AFC_CTRL35 0x6023U
#define OV5640_AFC_CTRL36 0x6024U
#define OV5640_AFC_CTRL37 0x6025U
#define OV5640_AFC_CTRL38 0x6026U
#define OV5640_AFC_CTRL39 0x6027U
#define OV5640_AFC_CTRL40 0x6028U
#define OV5640_AFC_CTRL41 0x6029U
#define OV5640_AFC_CTRL42 0x602AU
#define OV5640_AFC_CTRL43 0x602BU
#define OV5640_AFC_CTRL44 0x602CU
#define OV5640_AFC_CTRL45 0x602DU
#define OV5640_AFC_CTRL46 0x602EU
#define OV5640_AFC_CTRL47 0x602FU
#define OV5640_AFC_CTRL48 0x6030U
#define OV5640_AFC_CTRL49 0x6031U
#define OV5640_AFC_CTRL50 0x6032U
#define OV5640_AFC_CTRL51 0x6033U
#define OV5640_AFC_CTRL52 0x6034U
#define OV5640_AFC_CTRL53 0x6035U
#define OV5640_AFC_CTRL54 0x6036U
#define OV5640_AFC_CTRL55 0x6037U
#define OV5640_AFC_CTRL56 0x6038U
#define OV5640_AFC_CTRL57 0x6039U
#define OV5640_AFC_CTRL58 0x603AU
#define OV5640_AFC_CTRL59 0x603BU
#define OV5640_AFC_CTRL60 0x603CU
#define OV5640_AFC_READ58 0x603DU
#define OV5640_AFC_READ59 0x603EU
#define OV5640_AFC_READ60 0x603FU
void camera_sleep();
void camera_wakeup();
void camera_init();
#define PICTURE_BUFFER_SIZE 180000 // max support 150x4 = 600k
#endif //STM32U5_OV5640_H

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stm32u5/examples/cam_board/5640/ov5640_configs.h Executable file
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//
// Created by Guangzong Chen on 2/20/23.
//
// This file should only be include in ov5640.c not other files
#include "ov5640.h"
static uint16_t OV5640_Common[][2] =
{
{OV5640_SCCB_SYSTEM_CTRL1, 0x11},
{OV5640_SYSTEM_CTROL0, 0x82},
{OV5640_SCCB_SYSTEM_CTRL1, 0x03},
{OV5640_PAD_OUTPUT_ENABLE01, 0xFF},
{OV5640_PAD_OUTPUT_ENABLE02, 0xf3},
{OV5640_SC_PLL_CONTRL0, 0x18},
{OV5640_SYSTEM_CTROL0, 0x02},
{OV5640_SC_PLL_CONTRL1, 0x41},
{OV5640_SC_PLL_CONTRL2, 0x30},
{OV5640_SC_PLL_CONTRL3, 0x13},
{OV5640_SYSTEM_ROOT_DIVIDER, 0x01},
{0x3630, 0x36},
{0x3631, 0x0e},
{0x3632, 0xe2},
{0x3633, 0x12},
{0x3621, 0xe0},
{0x3704, 0xa0},
{0x3703, 0x5a},
{0x3715, 0x78},
{0x3717, 0x01},
{0x370b, 0x60},
{0x3705, 0x1a},
{0x3905, 0x02},
{0x3906, 0x10},
{0x3901, 0x0a},
{0x3731, 0x12},
{0x3600, 0x08},
{0x3601, 0x33},
{0x302d, 0x60},
{0x3620, 0x52},
{0x371b, 0x20},
{0x471c, 0x50},
{OV5640_AEC_CTRL13, 0x43},
{OV5640_AEC_GAIN_CEILING_HIGH, 0x00},
{OV5640_AEC_GAIN_CEILING_LOW, 0xf8},
{0x3635, 0x13},
{0x3636, 0x03},
{0x3634, 0x40},
{0x3622, 0x01},
{OV5640_5060HZ_CTRL01, 0x34},
{OV5640_5060HZ_CTRL04, 0x28},
{OV5640_5060HZ_CTRL05, 0x98},
{OV5640_LIGHTMETER1_TH_HIGH, 0x00},
{OV5640_LIGHTMETER1_TH_LOW, 0x00},
{OV5640_LIGHTMETER2_TH_HIGH, 0x01},
{OV5640_LIGHTMETER2_TH_LOW, 0x2c},
{OV5640_SAMPLE_NUMBER_HIGH, 0x9c},
{OV5640_SAMPLE_NUMBER_LOW, 0x40},
{OV5640_TIMING_TC_REG20, 0x06},
{OV5640_TIMING_TC_REG21, 0x00},
// {OV5640_TIMING_X_INC, 0x31},
// {OV5640_TIMING_Y_INC, 0x31},
// {OV5640_TIMING_HS_HIGH, 0x00},
// {OV5640_TIMING_HS_LOW, 0x00},
// {OV5640_TIMING_VS_HIGH, 0x00},
// {OV5640_TIMING_VS_LOW, 0x04},
// {OV5640_TIMING_HW_HIGH, 0x0a},
// {OV5640_TIMING_HW_LOW, 0x3f},
// {OV5640_TIMING_VH_HIGH, 0x07},
// {OV5640_TIMING_VH_LOW, 0x9b},
// {OV5640_TIMING_DVPHO_HIGH, 0x03},
// {OV5640_TIMING_DVPHO_LOW, 0x20},
// {OV5640_TIMING_DVPVO_HIGH, 0x02},
// {OV5640_TIMING_DVPVO_LOW, 0x58},
// {OV5640_TIMING_HTS_HIGH, 0x06},
// {OV5640_TIMING_HTS_LOW, 0x40},
// {OV5640_TIMING_VTS_HIGH, 0x03},
// {OV5640_TIMING_VTS_LOW, 0xe8},
// {OV5640_TIMING_HOFFSET_HIGH, 0x00},
// {OV5640_TIMING_HOFFSET_LOW, 0x10},
// {OV5640_TIMING_VOFFSET_HIGH, 0x00},
// {OV5640_TIMING_VOFFSET_LOW, 0x06},
{0x3618, 0x00},
{0x3612, 0x29},
{0x3708, 0x64},
{0x3709, 0x52},
{0x370c, 0x03},
{OV5640_AEC_CTRL02, 0x03},
{OV5640_AEC_CTRL03, 0xd8},
{OV5640_AEC_B50_STEP_HIGH, 0x01},
{OV5640_AEC_B50_STEP_LOW, 0x27},
{OV5640_AEC_B60_STEP_HIGH, 0x00},
{OV5640_AEC_B60_STEP_LOW, 0xf6},
{OV5640_AEC_CTRL0E, 0x03},
{OV5640_AEC_CTRL0D, 0x04},
{OV5640_AEC_MAX_EXPO_HIGH, 0x03},
{OV5640_AEC_MAX_EXPO_LOW, 0xd8},
{OV5640_BLC_CTRL01, 0x02},
{OV5640_BLC_CTRL04, 0x02},
{OV5640_SYSREM_RESET00, 0x00},
{OV5640_SYSREM_RESET02, 0x1c},
{OV5640_CLOCK_ENABLE00, 0xff},
{OV5640_CLOCK_ENABLE02, 0xc3},
{OV5640_MIPI_CONTROL00, 0x58},
{0x302e, 0x00},
{OV5640_POLARITY_CTRL, 0x22},
{OV5640_FORMAT_CTRL00, 0x6F},
{OV5640_FORMAT_MUX_CTRL, 0x01},
{OV5640_JPG_MODE_SELECT, 0x03},
{OV5640_JPEG_CTRL07, 0x04},
{0x440e, 0x00},
{0x460b, 0x35},
{0x460c, 0x23},
{OV5640_PCLK_PERIOD, 0x22},
{0x3824, 0x02},
{OV5640_ISP_CONTROL00, 0xa7},
{OV5640_ISP_CONTROL01, 0xa3},
{OV5640_AWB_CTRL00, 0xff},
{OV5640_AWB_CTRL01, 0xf2},
{OV5640_AWB_CTRL02, 0x00},
{OV5640_AWB_CTRL03, 0x14},
{OV5640_AWB_CTRL04, 0x25},
{OV5640_AWB_CTRL05, 0x24},
{OV5640_AWB_CTRL06, 0x09},
{OV5640_AWB_CTRL07, 0x09},
{OV5640_AWB_CTRL08, 0x09},
{OV5640_AWB_CTRL09, 0x75},
{OV5640_AWB_CTRL10, 0x54},
{OV5640_AWB_CTRL11, 0xe0},
{OV5640_AWB_CTRL12, 0xb2},
{OV5640_AWB_CTRL13, 0x42},
{OV5640_AWB_CTRL14, 0x3d},
{OV5640_AWB_CTRL15, 0x56},
{OV5640_AWB_CTRL16, 0x46},
{OV5640_AWB_CTRL17, 0xf8},
{OV5640_AWB_CTRL18, 0x04},
{OV5640_AWB_CTRL19, 0x70},
{OV5640_AWB_CTRL20, 0xf0},
{OV5640_AWB_CTRL21, 0xf0},
{OV5640_AWB_CTRL22, 0x03},
{OV5640_AWB_CTRL23, 0x01},
{OV5640_AWB_CTRL24, 0x04},
{OV5640_AWB_CTRL25, 0x12},
{OV5640_AWB_CTRL26, 0x04},
{OV5640_AWB_CTRL27, 0x00},
{OV5640_AWB_CTRL28, 0x06},
{OV5640_AWB_CTRL29, 0x82},
{OV5640_AWB_CTRL30, 0x38},
{OV5640_CMX1, 0x1e},
{OV5640_CMX2, 0x5b},
{OV5640_CMX3, 0x08},
{OV5640_CMX4, 0x0a},
{OV5640_CMX5, 0x7e},
{OV5640_CMX6, 0x88},
{OV5640_CMX7, 0x7c},
{OV5640_CMX8, 0x6c},
{OV5640_CMX9, 0x10},
{OV5640_CMXSIGN_HIGH, 0x01},
{OV5640_CMXSIGN_LOW, 0x98},
{OV5640_CIP_SHARPENMT_TH1, 0x08},
{OV5640_CIP_SHARPENMT_TH2, 0x30},
{OV5640_CIP_SHARPENMT_OFFSET1, 0x10},
{OV5640_CIP_SHARPENMT_OFFSET2, 0x00},
{OV5640_CIP_DNS_TH1, 0x08},
{OV5640_CIP_DNS_TH2, 0x30},
{OV5640_CIP_DNS_OFFSET1, 0x08},
{OV5640_CIP_DNS_OFFSET2, 0x16},
{OV5640_CIP_CTRL, 0x08},
{OV5640_CIP_SHARPENTH_TH1, 0x30},
{OV5640_CIP_SHARPENTH_TH2, 0x04},
{OV5640_CIP_SHARPENTH_OFFSET1, 0x06},
{OV5640_GAMMA_CTRL00, 0x01},
{OV5640_GAMMA_YST00, 0x08},
{OV5640_GAMMA_YST01, 0x14},
{OV5640_GAMMA_YST02, 0x28},
{OV5640_GAMMA_YST03, 0x51},
{OV5640_GAMMA_YST04, 0x65},
{OV5640_GAMMA_YST05, 0x71},
{OV5640_GAMMA_YST06, 0x7d},
{OV5640_GAMMA_YST07, 0x87},
{OV5640_GAMMA_YST08, 0x91},
{OV5640_GAMMA_YST09, 0x9a},
{OV5640_GAMMA_YST0A, 0xaa},
{OV5640_GAMMA_YST0B, 0xb8},
{OV5640_GAMMA_YST0C, 0xcd},
{OV5640_GAMMA_YST0D, 0xdd},
{OV5640_GAMMA_YST0E, 0xea},
{OV5640_GAMMA_YST0F, 0x1d},
{OV5640_SDE_CTRL0, 0x02},
{OV5640_SDE_CTRL3, 0x40},
{OV5640_SDE_CTRL4, 0x10},
{OV5640_SDE_CTRL9, 0x10},
{OV5640_SDE_CTRL10, 0x00},
{OV5640_SDE_CTRL11, 0xf8},
{OV5640_GMTRX00, 0x23},
{OV5640_GMTRX01, 0x14},
{OV5640_GMTRX02, 0x0f},
{OV5640_GMTRX03, 0x0f},
{OV5640_GMTRX04, 0x12},
{OV5640_GMTRX05, 0x26},
{OV5640_GMTRX10, 0x0c},
{OV5640_GMTRX11, 0x08},
{OV5640_GMTRX12, 0x05},
{OV5640_GMTRX13, 0x05},
{OV5640_GMTRX14, 0x08},
{OV5640_GMTRX15, 0x0d},
{OV5640_GMTRX20, 0x08},
{OV5640_GMTRX21, 0x03},
{OV5640_GMTRX22, 0x00},
{OV5640_GMTRX23, 0x00},
{OV5640_GMTRX24, 0x03},
{OV5640_GMTRX25, 0x09},
{OV5640_GMTRX30, 0x07},
{OV5640_GMTRX31, 0x03},
{OV5640_GMTRX32, 0x00},
{OV5640_GMTRX33, 0x01},
{OV5640_GMTRX34, 0x03},
{OV5640_GMTRX35, 0x08},
{OV5640_GMTRX40, 0x0d},
{OV5640_GMTRX41, 0x08},
{OV5640_GMTRX42, 0x05},
{OV5640_GMTRX43, 0x06},
{OV5640_GMTRX44, 0x08},
{OV5640_GMTRX45, 0x0e},
{OV5640_GMTRX50, 0x29},
{OV5640_GMTRX51, 0x17},
{OV5640_GMTRX52, 0x11},
{OV5640_GMTRX53, 0x11},
{OV5640_GMTRX54, 0x15},
{OV5640_GMTRX55, 0x28},
{OV5640_BRMATRX00, 0x46},
{OV5640_BRMATRX01, 0x26},
{OV5640_BRMATRX02, 0x08},
{OV5640_BRMATRX03, 0x26},
{OV5640_BRMATRX04, 0x64},
{OV5640_BRMATRX05, 0x26},
{OV5640_BRMATRX06, 0x24},
{OV5640_BRMATRX07, 0x22},
{OV5640_BRMATRX08, 0x24},
{OV5640_BRMATRX09, 0x24},
{OV5640_BRMATRX20, 0x06},
{OV5640_BRMATRX21, 0x22},
{OV5640_BRMATRX22, 0x40},
{OV5640_BRMATRX23, 0x42},
{OV5640_BRMATRX24, 0x24},
{OV5640_BRMATRX30, 0x26},
{OV5640_BRMATRX31, 0x24},
{OV5640_BRMATRX32, 0x22},
{OV5640_BRMATRX33, 0x22},
{OV5640_BRMATRX34, 0x26},
{OV5640_BRMATRX40, 0x44},
{OV5640_BRMATRX41, 0x24},
{OV5640_BRMATRX42, 0x26},
{OV5640_BRMATRX43, 0x28},
{OV5640_BRMATRX44, 0x42},
{OV5640_LENC_BR_OFFSET, 0xce},
{0x5025, 0x00},
{OV5640_AEC_CTRL0F, 0x30},
{OV5640_AEC_CTRL10, 0x28},
{OV5640_AEC_CTRL1B, 0x30},
{OV5640_AEC_CTRL1E, 0x26},
{OV5640_AEC_CTRL11, 0x60},
{OV5640_AEC_CTRL1F, 0x14},
{OV5640_SYSTEM_CTROL0, 0x02},
};
static const uint16_t OV5640_PF_JPEG[][2] =
{
/* SET PIXEL FORMAT: JPEG */
{OV5640_FORMAT_CTRL00, 0x30},
{OV5640_FORMAT_MUX_CTRL, 0x00},
// set resolution
{OV5640_TIMING_DVPHO_HIGH, 0x03},
{OV5640_TIMING_DVPHO_LOW, 0x20},
{OV5640_TIMING_DVPVO_HIGH, 0x01},
{OV5640_TIMING_DVPVO_LOW, 0xE0},
};
//static const uint16_t OV5640_QQVGA[][2] =
// {
// {OV5640_TIMING_DVPHO_HIGH, 0x00},
// {OV5640_TIMING_DVPHO_LOW, 0xA0},
// {OV5640_TIMING_DVPVO_HIGH, 0x00},
// {OV5640_TIMING_DVPVO_LOW, 0x78},
// };
//static const uint16_t OV5640_PF_YUV422[][2] =
// {
// /* SET PIXEL FORMAT: YUV422 */
// {OV5640_FORMAT_CTRL00, 0x30},
// {OV5640_FORMAT_MUX_CTRL, 0x00},
// };
//
//static const uint16_t OV5640_PF_RGB888[][2] =
// {
// /* SET PIXEL FORMAT: RGB888 (RGBRGB)*/
// {OV5640_FORMAT_CTRL00, 0x23},
// {OV5640_FORMAT_MUX_CTRL, 0x01},
// };
//static const uint16_t OV5640_VGA[][2] =
// {
// {OV5640_TIMING_DVPHO_HIGH, 0x02},
// {OV5640_TIMING_DVPHO_LOW, 0x80},
// {OV5640_TIMING_DVPVO_HIGH, 0x01},
// {OV5640_TIMING_DVPVO_LOW, 0xE0},
// };
///* Initialization sequence for WVGA resolution (800x480)*/
//static const uint16_t OV5640_WVGA[][2] =
// {
// {OV5640_TIMING_DVPHO_HIGH, 0x03},
// {OV5640_TIMING_DVPHO_LOW, 0x20},
// {OV5640_TIMING_DVPVO_HIGH, 0x01},
// {OV5640_TIMING_DVPVO_LOW, 0xE0},
// };
//
//
///* Initialization sequence for 480x272 resolution */
//static const uint16_t OV5640_480x272[][2] =
// {
// {OV5640_TIMING_DVPHO_HIGH, 0x01},
// {OV5640_TIMING_DVPHO_LOW, 0xE0},
// {OV5640_TIMING_DVPVO_HIGH, 0x01},
// {OV5640_TIMING_DVPVO_LOW, 0x10},
// };
/* Initialization sequence for QVGA resolution (320x240) */
// static const uint16_t OV5640_QVGA[][2] =
// {
// {OV5640_TIMING_DVPHO_HIGH, 0x01},
// {OV5640_TIMING_DVPHO_LOW, 0x40},
// {OV5640_TIMING_DVPVO_HIGH, 0x00},
// {OV5640_TIMING_DVPVO_LOW, 0xF0},
// };

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stm32u5/examples/cam_board/custom_prephrals.cpp Executable file
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//
// Created by Guangzong Chen on 8/5/23.
//
#include "custom_prephrals.h"
#include "bsp.h"
GpioPin<&pc, 3> led1;
GpioPin<&pc, 4> led2;
GpioPin<&pc, 5> led3;
GpioPin<&pb, 4> i2c3_sda;
GpioPin<&pc, 0> i2c3_scl;
GpioPin<&pb, 0> cam_pdwn;
GpioPin<&pb, 1> cam_resetb;
GpioPin<&pa, 8> cam_xclk; // tim1 ch1
GpioPin<&pc, 6> cam_d0;
GpioPin<&pc, 7> cam_d1;
GpioPin<&pc, 8> cam_d2;
GpioPin<&pc, 9> cam_d3;
GpioPin<&pc, 11> cam_d4;
GpioPin<&pb, 6> cam_d5;
GpioPin<&pb, 8> cam_d6;
GpioPin<&pb, 9> cam_d7;
GpioPin<&pb, 7> cam_vsync;
GpioPin<&pa, 4> cam_hsync;
GpioPin<&pa, 6> cam_pclk;
GpioPin<&pb, 2> cus_btn;
GpioPin<&pc, 1> sd_ck;
GpioPin<&pa, 0> sd_cmd;
GpioPin<&pb, 14> sd_d0;
void setup_pins() {
led1.setup(), led2.setup(), led3.setup();
i2c3_sda.setup(AF, 4, OPEN_DRAIN, LL_PULLUP);
i2c3_scl.setup(AF, 4, OPEN_DRAIN, LL_PULLUP);
cam_pdwn.setup(), cam_resetb.setup();
cam_xclk.setup(AF, 1);
cam_d0.setup(AF, 10);
cam_d1.setup(AF, 10);
cam_d2.setup(AF, 10);
cam_d3.setup(AF, 4);
cam_d4.setup(AF, 10);
cam_d5.setup(AF, 10);
cam_d6.setup(AF, 10);
cam_d7.setup(AF, 10);
cam_pclk.setup(AF, 4);
cam_hsync.setup(AF, 10);
cam_vsync.setup(AF, 10);
cus_btn.setup(INPUT, 0, PULL_PUSH, LL_PULLUP); // The circuit should be change
// delay.ms(100, true);
sd_ck.setup(AF, 12);
sd_cmd.setup(AF, 12);
sd_d0.setup(AF, 12);
}
void setup_timer() {
tim1.init_default();
tim1.set_pwm(CH1, 4, 4);
tim1.enable_output(CH1); // tim1 init_old
}
void cam_board_init(){
system_init();
setup_prepherials();
setup_pins(), setup_timer(), cam_i2c.init();
cam_pdwn.set_low();
cam_resetb.set_high();
}

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stm32u5/examples/cam_board/custom_prephrals.h Executable file
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//
// Created by Guangzong Chen on 8/5/23.
//
#ifndef STM32U5XX_HAL_PREPHRALS_H
#define STM32U5XX_HAL_PREPHRALS_H
#include <gpio.h>
#include <prepherials.h>
extern GpioPin<&pc, 3> led1;
extern GpioPin<&pc, 4> led2;
extern GpioPin<&pc, 5> led3;
extern GpioPin<&pb, 4> i2c3_sda;
extern GpioPin<&pc, 0> i2c3_scl;
extern GpioPin<&pb, 0> cam_pdwn;
extern GpioPin<&pb, 1> cam_resetb;
extern GpioPin<&pa, 8> cam_xclk;
extern GpioPin<&pc, 6> cam_d0;
extern GpioPin<&pc, 7> cam_d1;
extern GpioPin<&pc, 8> cam_d2;
extern GpioPin<&pc, 9> cam_d3;
extern GpioPin<&pc, 11> cam_d4;
extern GpioPin<&pb, 6> cam_d5;
extern GpioPin<&pb, 8> cam_d6;
extern GpioPin<&pb, 9> cam_d7;
extern GpioPin<&pb, 7> cam_vsync;
extern GpioPin<&pa, 4> cam_hsync;
extern GpioPin<&pa, 6> cam_pclk;
extern GpioPin<&pb, 2> cus_btn;
#define cam_i2c i2c3
void setup_pins();
void setup_timer();
void cam_board_init();
#endif // STM32U5XX_HAL_PREPHRALS_H

40
stm32u5/examples/cam_board/i2c/CMakeLists.txt Executable file
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cmake_minimum_required(VERSION 3.23)
set(CMAKE_C_COMPILER_WORKS 1)
set(CMAKE_CXX_COMPILER_WORKS 1)
project(example_i2c LANGUAGES C CXX ASM)
set(EXAMPLE_NAME "cam_i2c")
set(CMAKE_EXPORT_COMPILE_COMMANDS on) # for clangd
### set includes and library
set(Stm32U5Lib_DIR ../../../)
find_package(Stm32U5Lib REQUIRED)
include_directories(../)
file(GLOB_RECURSE SOURCES
./ex_i2c.cpp
../custom_prephrals.cpp
../../../startup/startup_stm32u575zitxq.s
)
#add_executable(${EXAMPLE_NAME}.elf ${SOURCES} ${LINKER_SCRIPT} ${LIB_BIN})
# if LIB_SOURCES is not empty, then add it to the target
if(NOT LIB_SOURCES)
message(STATUS "LIB_SOURCES is empty")
add_executable(${EXAMPLE_NAME}.elf ${SOURCES} ${LINKER_SCRIPT})
# add the library to the target
target_link_libraries(${EXAMPLE_NAME}.elf ${LIB_BIN})
else()
message(STATUS "LIB_SOURCES is not empty")
add_executable(${EXAMPLE_NAME}.elf ${SOURCES} ${LINKER_SCRIPT} ${LIB_SOURCES})
endif()
set(HEX_FILE ${EXAMPLE_NAME}.hex)
set(BIN_FILE ${EXAMPLE_NAME}.bin)
add_custom_command(TARGET ${EXAMPLE_NAME}.elf POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${HEX_FILE}
COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${BIN_FILE}
COMMENT "Building ${HEX_FILE}
Building ${BIN_FILE}")

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stm32u5/examples/cam_board/i2c/ex_i2c.cpp Executable file
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#include "bsp.h"
#include "custom_prephrals.h"
#include "prepherials.h"
//#include <cstdio>
#define cam_i2c i2c3
#define OV2640_I2C_ADDR 0x60
int main() {
system_init();
setup_prepherials();
setup_pins();
setup_timer();
cam_i2c.init();
led1.set_high();
cam_pdwn.set_low();
cam_resetb.set_high();
delay.ms(100);
cam_pdwn.set_high();
delay.ms(100, true);
uint8_t data[2] = {0x00, 0x00};
while (1) {
led1.set_high();
delay.ms(500);
led1.set_low();
delay.ms(500);
// data[0] = 0x0A;
// hal_status_e ret;
// ret = cam_i2c.send(0x60, data, 1);
// ret = cam_i2c.read(0x60, data + 1, 1);
// printf("0x60 0x0A: %x\n", ret);
};
}

38
stm32u5/examples/cam_board/led/CMakeLists.txt Executable file
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cmake_minimum_required(VERSION 3.23)
#project(sdcard_example C ASM)
set(CMAKE_C_COMPILER_WORKS 1)
set(CMAKE_CXX_COMPILER_WORKS 1)
project(led LANGUAGES C CXX ASM)
set(EXAMPLE_NAME "CAM_LED")
set(CMAKE_EXPORT_COMPILE_COMMANDS on) # for clangd
SET(CMAKE_C_STANDARD 17)
SET(CMAKE_CXX_STANDARD 17)
### set includes and library
set(Stm32U5Lib_DIR ../../../)
find_package(Stm32U5Lib REQUIRED)
add_definitions(-DSTM32U575xx)
include_directories(./)
include_directories(../)
add_compile_options(-g
# -Ofast
)
file(GLOB_RECURSE SOURCES
./*.c
./*.cpp
../custom_prephrals.cpp
)
add_executable(${EXAMPLE_NAME}.elf ${SOURCES} ${LINKER_SCRIPT} ${LIB_SOURCES} )
set(HEX_FILE ${EXAMPLE_NAME}.hex)
set(BIN_FILE ${EXAMPLE_NAME}.bin)
add_custom_command(TARGET ${EXAMPLE_NAME}.elf POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${HEX_FILE}
COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${BIN_FILE}
COMMENT "Building ${HEX_FILE}
Building ${BIN_FILE}")

18
stm32u5/examples/cam_board/led/led.cpp Executable file
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#include "bsp.h"
#include "custom_prephrals.h"
int main() {
// delay_init();
system_init();
setup_prepherials();
// pb.init(LED_BLUE_PIN);
led1.setup(), led2.setup(), led3.setup(), i2c3_sda.setup(), i2c3_scl.setup();
cam_pdwn.setup(), cam_resetb.setup();
while (1) {
led1.toggle();
delay.ms(500, true);
led2.toggle();
delay.ms(800, true);
};
}

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stm32u5/examples/cam_board/ov2640/CMakeLists.txt Executable file
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cmake_minimum_required(VERSION 3.23)
#project(example_i2c C ASM)
set(EXAMPLE_NAME "cam_ov2640")
set(CMAKE_EXPORT_COMPILE_COMMANDS on) # for clangd
### set includes and library
set(Stm32U5Lib_DIR ../../../)
find_package(Stm32U5Lib REQUIRED)
add_definitions(-DSTM32U575xx)
include_directories(./ ../)
add_compile_options(
# -g
# -Ofast
)
file(GLOB_RECURSE SOURCES
./*.c
./*.cpp
../custom_prephrals.cpp
)
add_executable(${EXAMPLE_NAME}.elf ${SOURCES} ${LINKER_SCRIPT} ${LIB_SOURCES})
set(HEX_FILE ${EXAMPLE_NAME}.hex)
set(BIN_FILE ${EXAMPLE_NAME}.bin)
add_custom_command(TARGET ${EXAMPLE_NAME}.elf POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${HEX_FILE}
COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${BIN_FILE}
COMMENT "Building ${HEX_FILE}
Building ${BIN_FILE}")

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stm32u5/examples/cam_board/ov2640/main.cpp Executable file
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#include "bsp.h"
#include "custom_prephrals.h"
#include "prepherials.h"
#include <cstdio>
#include "ov2640.h"
#include <cstring>
//#define cam_i2c i2c3
#define OV2640_I2C_ADDR 0x60
#define PICTURE_BUFFER_SIZE 60000
uint32_t picture[PICTURE_BUFFER_SIZE];
int main() {
system_init();
setup_prepherials();
setup_pins(), setup_timer(), cam_i2c.init();
led3.set_high();
led1.set_high();
cam_resetb.set_high();
cam_pdwn.set_low();
delay.delay_ms(10);
ov2640_start();
led2.toggle();
delay.delay_ms(100, true);
dma10.init(86, DMA_DATA_WIDTH_32_BITS, DMA_DATA_WIDTH_32_BITS, DMA_ADDR_FIX,
DMA_ADDR_INC, DMA_TYPE_PREPHERIAL,
DMA_TYPE_MEMORY, PICTURE_BUFFER_SIZE * 5);
dcmi.init_old();
while (1) {
dma10.dma_start((uint32_t) &DCMI->DR, (uint32_t) picture, 4 * PICTURE_BUFFER_SIZE);
// first few frames may cause green screen, if so we can extend the Delay to skip them.
delay_ms(100, true); // wait for camera to be ready -- skip first frame 12.5fps = 80ms
dcmi.enable();
dcmi.capture_enable();
delay_s(2, true); // wait for picture to be captured then stop dma
// dma_stop(dcmi_dma);
// disable(dcmi_p);
auto *tmp = (uint8_t *) picture;
uint32_t i = 0;
for (i = 0; i < 4 * PICTURE_BUFFER_SIZE - 1; i++) {
if (tmp[i] == 0xff && tmp[i + 1] == 0xd9) {
printf("%lu\n", i);
break;
}
}
cam_pdwn.set_high();
cam_resetb.set_low();
if (i == 4 * PICTURE_BUFFER_SIZE - 1)
i = 0;
// if (uart_send_massive(usart1_p, (uint8_t *) picture, i + 5) != HAL_OK)
// printf("no enough space in uart buffer\n");
memset(picture, 0, sizeof(picture));
// delay_s(2, true);
printf("%lu\n", i);
// tim1.tim_out_enable();
TIM1->CCER &= ~TIM_CCER_CC1E;
led2.set_low();
while (1) {
asm volatile ("wfi");
}
}
}

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stm32u5/examples/cam_board/ov2640/ov2640.cpp Executable file
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//
// Created by Guangzong Chen on 2/8/23.
//
#include "ov2640.h"
#include <stdint.h>
#include <stm32u5xx.h>
//#include "prepherials.h"
#include "custom_prephrals.h"
#define OV2640_I2C_ADDR 0x60
const unsigned char OV2640_JPEG_INIT[][2] = {{0xff, 0x00},
{0x2c, 0xff},
{0x2e, 0xdf},
{0xff, 0x01},
{0x3c, 0x32},
{0x11, 0x00},
{0x09, 0x02},
{0x04, 0x28},
{0x13, 0xe5},
{0x14, 0x48},
{0x2c, 0x0c},
{0x33, 0x78},
{0x3a, 0x33},
{0x3b, 0xfB},
{0x3e, 0x00},
{0x43, 0x11},
{0x16, 0x10},
{0x39, 0x92},
{0x35, 0xda},
{0x22, 0x1a},
{0x37, 0xc3},
{0x23, 0x00},
{0x34, 0xc0},
{0x36, 0x1a},
{0x06, 0x88},
{0x07, 0xc0},
{0x0d, 0x87},
{0x0e, 0x41},
{0x4c, 0x00},
{0x48, 0x00},
{0x5B, 0x00},
{0x42, 0x03},
{0x4a, 0x81},
{0x21, 0x99},
{0x24, 0x40},
{0x25, 0x38},
{0x26, 0x82},
{0x5c, 0x00},
{0x63, 0x00},
{0x61, 0x70},
{0x62, 0x80},
{0x7c, 0x05},
{0x20, 0x80},
{0x28, 0x30},
{0x6c, 0x00},
{0x6d, 0x80},
{0x6e, 0x00},
{0x70, 0x02},
{0x71, 0x94},
{0x73, 0xc1},
{0x12, 0x40},
{0x17, 0x11},
{0x18, 0x43},
{0x19, 0x00},
{0x1a, 0x4b},
{0x32, 0x09},
{0x37, 0xc0},
{0x4f, 0x60},
{0x50, 0xa8},
{0x6d, 0x00},
{0x3d, 0x38},
{0x46, 0x3f},
{0x4f, 0x60},
{0x0c, 0x3c},
{0xff, 0x00},
{0xe5, 0x7f},
{0xf9, 0xc0},
{0x41, 0x24},
{0xe0, 0x14},
{0x76, 0xff},
{0x33, 0xa0},
{0x42, 0x20},
{0x43, 0x18},
{0x4c, 0x00},
{0x87, 0xd5},
{0x88, 0x3f},
{0xd7, 0x03},
{0xd9, 0x10},
{0xd3, 0x82},
{0xc8, 0x08},
{0xc9, 0x80},
{0x7c, 0x00},
{0x7d, 0x00},
{0x7c, 0x03},
{0x7d, 0x48},
{0x7d, 0x48},
{0x7c, 0x08},
{0x7d, 0x20},
{0x7d, 0x10},
{0x7d, 0x0e},
{0x90, 0x00},
{0x91, 0x0e},
{0x91, 0x1a},
{0x91, 0x31},
{0x91, 0x5a},
{0x91, 0x69},
{0x91, 0x75},
{0x91, 0x7e},
{0x91, 0x88},
{0x91, 0x8f},
{0x91, 0x96},
{0x91, 0xa3},
{0x91, 0xaf},
{0x91, 0xc4},
{0x91, 0xd7},
{0x91, 0xe8},
{0x91, 0x20},
{0x92, 0x00},
{0x93, 0x06},
{0x93, 0xe3},
{0x93, 0x05},
{0x93, 0x05},
{0x93, 0x00},
{0x93, 0x04},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x96, 0x00},
{0x97, 0x08},
{0x97, 0x19},
{0x97, 0x02},
{0x97, 0x0c},
{0x97, 0x24},
{0x97, 0x30},
{0x97, 0x28},
{0x97, 0x26},
{0x97, 0x02},
{0x97, 0x98},
{0x97, 0x80},
{0x97, 0x00},
{0x97, 0x00},
{0xc3, 0xed},
{0xa4, 0x00},
{0xa8, 0x00},
{0xc5, 0x11},
{0xc6, 0x51},
{0xbf, 0x80},
{0xc7, 0x10},
{0xb6, 0x66},
{0xb8, 0xA5},
{0xb7, 0x64},
{0xb9, 0x7C},
{0xb3, 0xaf},
{0xb4, 0x97},
{0xb5, 0xFF},
{0xb0, 0xC5},
{0xb1, 0x94},
{0xb2, 0x0f},
{0xc4, 0x5c},
{0xc0, 0x64},
{0xc1, 0x4B},
{0x8c, 0x00},
{0x86, 0x3D},
{0x50, 0x00},
{0x51, 0xC8},
{0x52, 0x96},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x00},
{0x5a, 0xC8},
{0x5b, 0x96},
{0x5c, 0x00},
{0xd3, 0x00},
{0xc3, 0xed},
{0x7f, 0x00},
{0xda, 0x00},
{0xe5, 0x1f},
{0xe1, 0x67},
{0xe0, 0x00},
{0xdd, 0x7f},
{0x05, 0x00},
{0x12, 0x40},
{0xd3, 0x04},
{0xc0, 0x16},
{0xC1, 0x12},
{0x8c, 0x00},
{0x86, 0x3d},
{0x50, 0x00},
{0x51, 0x2C},
{0x52, 0x24},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x00},
{0x5A, 0x2c},
{0x5b, 0x24},
{0x5c, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_YUV422[][2] = {{0xFF, 0x00},
{0x05, 0x00},
{0xDA, 0x10},
{0xD7, 0x03},
{0xDF, 0x00},
{0x33, 0x80},
{0x3C, 0x40},
{0xe1, 0x77},
{0x00, 0x00},
{0xff, 0xff},};
const unsigned char OV2640_JPEG[][2] = {{0xe0, 0x14},
{0xe1, 0x77},
{0xe5, 0x1f},
{0xd7, 0x03},
{0xda, 0x10},
{0xe0, 0x00},
{0xFF, 0x01},
{0x04, 0x08},
{0xff, 0xff},};
const unsigned char OV2640_160x120_JPEG[][2] = {{0xFF, 0x01},
{0x12, 0x40},
{0x17, 0x11},
{0x18, 0x43},
{0x19, 0x00},
{0x1a, 0x4b},
{0x32, 0x09},
{0x4f, 0xca},
{0x50, 0xa8},
{0x5a, 0x23},
{0x6d, 0x00},
{0x39, 0x12},
{0x35, 0xda},
{0x22, 0x1a},
{0x37, 0xc3},
{0x23, 0x00},
{0x34, 0xc0},
{0x36, 0x1a},
{0x06, 0x88},
{0x07, 0xc0},
{0x0d, 0x87},
{0x0e, 0x41},
{0x4c, 0x00},
{0xFF, 0x00},
{0xe0, 0x04},
{0xc0, 0x64},
{0xc1, 0x4b},
{0x86, 0x35},
{0x50, 0x92},
{0x51, 0xc8},
{0x52, 0x96},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x00},
{0x57, 0x00},
{0x5a, 0x2c},
{0x5b, 0x24},
{0x5c, 0x00},
{0xe0, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_320x240_JPEG[][2] = {{0xff, 0x01},
{0x12, 0x40},
{0x17, 0x11},
{0x18, 0x43},
{0x19, 0x00},
{0x1a, 0x4b},
{0x32, 0x09},
{0x4f, 0xca},
{0x50, 0xa8},
{0x5a, 0x23},
{0x6d, 0x00},
{0x39, 0x12},
{0x35, 0xda},
{0x22, 0x1a},
{0x37, 0xc3},
{0x23, 0x00},
{0x34, 0xc0},
{0x36, 0x1a},
{0x06, 0x88},
{0x07, 0xc0},
{0x0d, 0x87},
{0x0e, 0x41},
{0x4c, 0x00},
{0xff, 0x00},
{0xe0, 0x04},
{0xc0, 0x64},
{0xc1, 0x4b},
{0x86, 0x35},
{0x50, 0x89},
{0x51, 0xc8},
{0x52, 0x96},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x00},
{0x57, 0x00},
{0x5a, 0x50},
{0x5b, 0x3c},
{0x5c, 0x00},
{0xe0, 0x00},
{0xff, 0xff},};
const unsigned char OV2640_640x480_JPEG[][2] = {{0xff, 0x01},
{0x11, 0x01},
{0x12, 0x00},
{0x17, 0x11},
{0x18, 0x75},
{0x32, 0x36},
{0x19, 0x01},
{0x1a, 0x97},
{0x03, 0x0f},
{0x37, 0x40},
{0x4f, 0xbb},
{0x50, 0x9c},
{0x5a, 0x57},
{0x6d, 0x80},
{0x3d, 0x34},
{0x39, 0x02},
{0x35, 0x88},
{0x22, 0x0a},
{0x37, 0x40},
{0x34, 0xa0},
{0x06, 0x02},
{0x0d, 0xb7},
{0x0e, 0x01},
{0xff, 0x00},
{0xe0, 0x04},
{0xc0, 0xc8},
{0xc1, 0x96},
{0x86, 0x3d},
{0x50, 0x89},
{0x51, 0x90},
{0x52, 0x2c},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x88},
{0x57, 0x00},
{0x5a, 0xa0},
{0x5b, 0x78},
{0x5c, 0x00},
{0xd3, 0x04},
{0xe0, 0x00},
{0xff, 0xff},};
const unsigned char OV2640_800x600_JPEG[][2] = {{0xFF, 0x01},
{0x11, 0x01},
{0x12, 0x00},
{0x17, 0x11},
{0x18, 0x75},
{0x32, 0x36},
{0x19, 0x01},
{0x1a, 0x97},
{0x03, 0x0f},
{0x37, 0x40},
{0x4f, 0xbb},
{0x50, 0x9c},
{0x5a, 0x57},
{0x6d, 0x80},
{0x3d, 0x34},
{0x39, 0x02},
{0x35, 0x88},
{0x22, 0x0a},
{0x37, 0x40},
{0x34, 0xa0},
{0x06, 0x02},
{0x0d, 0xb7},
{0x0e, 0x01},
{0xFF, 0x00},
{0xe0, 0x04},
{0xc0, 0xc8},
{0xc1, 0x96},
{0x86, 0x35},
{0x50, 0x89},
{0x51, 0x90},
{0x52, 0x2c},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x88},
{0x57, 0x00},
{0x5a, 0xc8},
{0x5b, 0x96},
{0x5c, 0x00},
{0xd3, 0x02},
{0xe0, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_1024x768_JPEG[][2] = {{0xFF, 0x01},
{0x11, 0x01},
{0x12, 0x00},
{0x17, 0x11},
{0x18, 0x75},
{0x32, 0x36},
{0x19, 0x01},
{0x1a, 0x97},
{0x03, 0x0f},
{0x37, 0x40},
{0x4f, 0xbb},
{0x50, 0x9c},
{0x5a, 0x57},
{0x6d, 0x80},
{0x3d, 0x34},
{0x39, 0x02},
{0x35, 0x88},
{0x22, 0x0a},
{0x37, 0x40},
{0x34, 0xa0},
{0x06, 0x02},
{0x0d, 0xb7},
{0x0e, 0x01},
{0xFF, 0x00},
{0xc0, 0xC8},
{0xc1, 0x96},
{0x8c, 0x00},
{0x86, 0x3D},
{0x50, 0x00},
{0x51, 0x90},
{0x52, 0x2C},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x88},
{0x5a, 0x00},
{0x5b, 0xC0},
{0x5c, 0x01},
{0xd3, 0x02},
{0xff, 0xff}};
const unsigned char OV2640_1280x960_JPEG[][2] = {{0xFF, 0x01},
{0x11, 0x01},
{0x12, 0x00},
{0x17, 0x11},
{0x18, 0x75},
{0x32, 0x36},
{0x19, 0x01},
{0x1a, 0x97},
{0x03, 0x0f},
{0x37, 0x40},
{0x4f, 0xbb},
{0x50, 0x9c},
{0x5a, 0x57},
{0x6d, 0x80},
{0x3d, 0x34},
{0x39, 0x02},
{0x35, 0x88},
{0x22, 0x0a},
{0x37, 0x40},
{0x34, 0xa0},
{0x06, 0x02},
{0x0d, 0xb7},
{0x0e, 0x01},
{0xFF, 0x00},
{0xe0, 0x04},
{0xc0, 0xc8},
{0xc1, 0x96},
{0x86, 0x3d},
{0x50, 0x00},
{0x51, 0x90},
{0x52, 0x2c},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x88},
{0x57, 0x00},
{0x5a, 0x40},
{0x5b, 0xf0},
{0x5c, 0x01},
{0xd3, 0x02},
{0xe0, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_CONTRAST2[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x07},
{0x7d, 0x20},
{0x7d, 0x28},
{0x7d, 0x0c},
{0x7d, 0x06},
{0xff, 0xff}};
const unsigned char OV2640_CONTRAST1[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x07},
{0x7d, 0x20},
{0x7d, 0x24},
{0x7d, 0x16},
{0x7d, 0x06},
{0xff, 0xff}};
const unsigned char OV2640_CONTRAST0[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x07},
{0x7d, 0x20},
{0x7d, 0x20},
{0x7d, 0x20},
{0x7d, 0x06},
{0xff, 0xff}};
const unsigned char OV2640_CONTRAST_1[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x07},
{0x7d, 0x20},
{0x7d, 0x1c},
{0x7d, 0x2a},
{0x7d, 0x06},
{0xff, 0xff}};
const unsigned char OV2640_CONTRAST_2[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x07},
{0x7d, 0x20},
{0x7d, 0x18},
{0x7d, 0x34},
{0x7d, 0x06},
{0xff, 0xff}};
const unsigned char OV2640_SATURATION2[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x02},
{0x7c, 0x03},
{0x7d, 0x68},
{0x7d, 0x68},
{0xff, 0xff}};
const unsigned char OV2640_SATURATION1[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x02},
{0x7c, 0x03},
{0x7d, 0x58},
{0x7d, 0x68},
{0xff, 0xff}};
const unsigned char OV2640_SATURATION0[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x02},
{0x7c, 0x03},
{0x7d, 0x48},
{0x7d, 0x48},
{0xff, 0xff}};
const unsigned char OV2640_SATURATION_1[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x02},
{0x7c, 0x03},
{0x7d, 0x38},
{0x7d, 0x38},
{0xff, 0xff}};
const unsigned char OV2640_SATURATION_2[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x02},
{0x7c, 0x03},
{0x7d, 0x28},
{0x7d, 0x28},
{0xff, 0xff}};
const unsigned char OV2640_BRIGHTNESS2[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x09},
{0x7d, 0x40},
{0x7d, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_BRIGHTNESS1[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x09},
{0x7d, 0x30},
{0x7d, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_BRIGHTNESS0[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x09},
{0x7d, 0x20},
{0x7d, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_BRIGHTNESS_1[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x09},
{0x7d, 0x10},
{0x7d, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_BRIGHTNESS_2[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x09},
{0x7d, 0x00},
{0x7d, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_NORMAL[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x00},
{0x7c, 0x05},
{0x7d, 0x80},
{0x7d, 0x80},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_ANTIQUE[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x18},
{0x7c, 0x05},
{0x7d, 0x40},
{0x7d, 0xa6},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_BLACK_NEGATIVE[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x58},
{0x7c, 0x05},
{0x7d, 0x80},
{0x7d, 0x80},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_BLUISH[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x18},
{0x7c, 0x05},
{0x7d, 0xa0},
{0x7d, 0x40},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_BLACK[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x18},
{0x7c, 0x05},
{0x7d, 0x80},
{0x7d, 0x80},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_NEGATIVE[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x40},
{0x7c, 0x05},
{0x7d, 0x80},
{0x7d, 0x80},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_GREENISH[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x18},
{0x7c, 0x05},
{0x7d, 0x40},
{0x7d, 0x40},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_REDDISH[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x18},
{0x7c, 0x05},
{0x7d, 0x40},
{0x7d, 0xc0},
{0xff, 0xff}};
const unsigned char OV2640_LIGHT_MODE_AUTO[][2] = {{0xff, 0x00},
{0xc7, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_LIGHT_MODE_SUNNY[][2] = {{0xff, 0x00},
{0xc7, 0x40},
{0xcc, 0x5e},
{0xcd, 0x41},
{0xce, 0x54},
{0xff, 0xff}};
const unsigned char OV2640_LIGHT_MODE_CLOUDY[][2] = {{0xff, 0x00},
{0xc7, 0x40},
{0xcc, 0x65},
{0xcd, 0x41},
{0xce, 0x4f},
{0xff, 0xff}};
const unsigned char OV2640_LIGHT_MODE_OFFICE[][2] = {{0xff, 0x00},
{0xc7, 0x40},
{0xcc, 0x52},
{0xcd, 0x41},
{0xce, 0x66},
{0xff, 0xff}};
const unsigned char OV2640_LIGHT_MODE_HOME[][2] = {{0xff, 0x00},
{0xc7, 0x40},
{0xcc, 0x42},
{0xcd, 0x3f},
{0xce, 0x71},
{0xff, 0xff}};
/**
* this function should be after i2c and Delay init_old
*/
void ov2640_start() {
uint8_t data[2] = {0x00, 0x00};
// setup camera
data[0] = 0xff, data[1] = 0x01;
hal_status_e ret;
ret = cam_i2c.send(OV2640_I2C_ADDR, data, 2);
if (ret != HAL_OK)
while (true) {};
data[0] = 0x12, data[1] = 0x80;
delay_ms(100, true);
for (int i = 0; i < sizeof(OV2640_JPEG_INIT) / 2; i++) {
ret = cam_i2c.send(OV2640_I2C_ADDR, OV2640_JPEG_INIT[i], 2);
if (ret != HAL_OK)
while (true) {};
}
for (int i = 0; i < sizeof(OV2640_YUV422) / 2; i++) {
ret = cam_i2c.send(OV2640_I2C_ADDR, OV2640_YUV422[i], 2);
if (ret != HAL_OK)
while (true) {};
}
// for (auto i: OV2640_JPEG) {
for (int i = 0; i < sizeof(OV2640_JPEG) / 2; i++) {
ret = cam_i2c.send(OV2640_I2C_ADDR, OV2640_JPEG[i], 2);
if (ret != HAL_OK)
while (true) {};
}
delay_ms(10, true);
data[0] = 0xff, data[1] = 0x01;
ret = cam_i2c.send(OV2640_I2C_ADDR, data, 2);
if (ret != HAL_OK)
while (true) {};
delay_ms(10, true);
data[0] = 0x15, data[1] = 0x00;
ret = cam_i2c.send(OV2640_I2C_ADDR, data, 2);
if (ret != HAL_OK)
while (true) {};
// for (auto i: OV2640_1280x960_JPEG) {
for (int i = 0; i < sizeof(OV2640_640x480_JPEG) / 2; i++) {
ret = cam_i2c.send(OV2640_I2C_ADDR, OV2640_640x480_JPEG[i], 2);
if (ret != HAL_OK)
while (true) {};
}
delay_ms(100, true);
}

8
stm32u5/examples/cam_board/ov2640/ov2640.h Executable file
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#ifndef OV2640_H
#define OV2640_H
//#include "tim.h"
void ov2640_start();
#endif //DCMI_OV2640_H

26
stm32u5/examples/cam_board/readme.md Executable file
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The content in this folder is for custome camera board.
## pin layout
| Pin | Function | alternate function | note |
|------|---------------------|--------------------|---------------------------------|
| pc3 | LED1 | | |
| pc4 | LED2 | | |
| pc5 | LED3 | | |
| pb4 | I2c3_SDA | 4 | |
| pc0 | I2c3_SCL | 4 | |
| pb0 | CAM_PDWN | | set low to enter low power mode |
| pb1 | CAM_RESETB | | set low to reset the camera |
| pa8 | CAM_XCLK (TIM1_CH1) | 1 | |
| pc6 | DCMI_D0 | 10 | |
| pc7 | DCMI_D1 | 10 | |
| pc8 | DCMI_D2 | 10 | |
| pc9 | DCMI_D3 | 4 | |
| pc11 | DCMI_D4 | 10 | check the pinout |
| pb6 | DCMI_D5 | 10 | check the pinout |
| pb8 | DCMI_D6 | 10 | check the pinout |
| pb9 | DCMI_D7 | 10 | check the pinout |
| pb7 | DCMI_VSYNC | 10 | |
| pa4 | DCMI_HSYNC | 10 | |
| pa6 | DCMI_PIXCLK | 10 | check the pinout |
| pb2 | EXTI2 | 0 | |

33
stm32u5/examples/cam_board/rtc/CMakeLists.txt Executable file
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cmake_minimum_required(VERSION 3.23)
#project(example_i2c C ASM)
set(EXAMPLE_NAME "cam_rtc")
set(CMAKE_EXPORT_COMPILE_COMMANDS on) # for clangd
### set includes and library
set(Stm32U5Lib_DIR ../../../)
find_package(Stm32U5Lib REQUIRED)
add_definitions(-DSTM32U575xx)
include_directories(./ ../)
add_compile_options(
-g
# -Ofast
)
file(GLOB_RECURSE SOURCES
./*.c
./*.cpp
../custom_prephrals.cpp
)
add_executable(${EXAMPLE_NAME}.elf ${SOURCES} ${LINKER_SCRIPT} ${LIB_SOURCES})
set(HEX_FILE ${EXAMPLE_NAME}.hex)
set(BIN_FILE ${EXAMPLE_NAME}.bin)
add_custom_command(TARGET ${EXAMPLE_NAME}.elf POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${HEX_FILE}
COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${BIN_FILE}
COMMENT "Building ${HEX_FILE}
Building ${BIN_FILE}")

115
stm32u5/examples/cam_board/rtc/main.cpp Executable file
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// this example use uart to update rtc
#include "bsp.h"
#include <stm32u575xx.h>
#include "prepherials.h"
#include "command.h"
#include "custom_prephrals.h"
#include <string.h>
static void usart_event_handler();
int __io_putchar(int ch) {
return usart1.send((uint8_t *) &ch, 1);
}
#include <stdio.h>
void led_toggle() {
uint8_t val;
rtc.rtc_get_hour(&val);
val = val % 12;
while (val--) {
led1.set_high();
delay.delay_ms(200, true);
led1.set_low();
delay.delay_ms(200, true);
}
delay_s(1, true);
rtc.rtc_get_minute(&val);
val = val % 10;
while (val--) {
led3.set_high();
delay.delay_ms(200, true);
led3.set_low();
delay.delay_ms(200, true);
}
}
int main() {
uint32_t reset_reason = RCC->CSR; // get reset reason
system_init();
setup_prepherials();
setup_pins();
exti.set_trigger(0, 0, led_toggle);
rtc.rtc_setup_time(23, 8, 6, 14, 35, 0);
while (1) {
asm volatile ("wfi");
}
}
void usart_event_handler() {
char data[50];
uint32_t len = 50;
if (usart1.get_line((uint8_t *) data, len) != HAL_OK) {
return;
}
if (len == 0) {
return;
}
char *argv[10];
uint8_t argc = 10;
command_parse(data, len, argv, &argc);
if (argc == 0) {
printf("no command found.\n "
"rtc_set year month day hour minute second"
"rtc_get second|minute|hour|day|month|year|time"
"\n");
return;
}
if (strcmp(argv[0], "rtc_set") == 0) {
if (argc != 7) {
printf("rtc_set year month day hour minute second\n");
return;
}
printf("rtc_set %s %s %s %s %s %s\n", argv[1], argv[2], argv[3], argv[4], argv[5], argv[6]);
rtc.rtc_setup_time((uint8_t) atoi(argv[1]), (uint8_t) atoi(argv[2]), (uint8_t) atoi(argv[3]),
(uint8_t) atoi(argv[4]), (uint8_t) atoi(argv[5]), (uint8_t) atoi(argv[6]));
} else if (strcmp(argv[0], "rtc_get") == 0) {
if (argc != 2) {
printf("rtc_get second|minute|hour|day|month|year|time\n");
return;
}
uint8_t val;
if (strcmp(argv[1], "second") == 0) {
rtc.rtc_get_second(&val);
printf("second: %d\n", val);
} else if (strcmp(argv[1], "minute") == 0) {
rtc.rtc_get_minute(&val);
printf("minute: %d\n", val);
} else if (strcmp(argv[1], "hour") == 0) {
rtc.rtc_get_hour(&val);
printf("hour: %d\n", val);
} else if (strcmp(argv[1], "day") == 0) {
rtc.rtc_get_day(&val);
printf("day: %d\n", val);
} else if (strcmp(argv[1], "month") == 0) {
rtc.rtc_get_month(&val);
printf("month: %d\n", val);
} else if (strcmp(argv[1], "year") == 0) {
rtc.rtc_get_year(&val);
printf("year: %d\n", val);
} else if (strcmp(argv[1], "time") == 0) {
uint8_t second, minute, hour, day, month, year;
rtc.rtc_get_datetime(&year, &month, &day, &hour, &minute, &second);
printf("%02d-%02d-%02d %02d:%02d:%02d\n", year, month, day, hour, minute, second);
} else {
printf("unknown command. rtc_get second|minute|hour|day|month|year|time");
}
} else {
printf("unkonw command %s.\n"
"rtc_set year month day hour minute second\n"
"rtc_get second|minute|hour|day|month|year|time"
"\n", argv[0]);
}
}

33
stm32u5/examples/cam_board/sdcard/CMakeLists.txt Executable file
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cmake_minimum_required(VERSION 3.23)
#project(sdcard_example C ASM)
set(EXAMPLE_NAME "cam_sdcard")
set(CMAKE_EXPORT_COMPILE_COMMANDS on) # for clangd
### set includes and library
set(Stm32U5Lib_DIR ../../../)
find_package(Stm32U5Lib REQUIRED)
add_definitions(-DSTM32U575xx)
include_directories(./ ../)
add_compile_options(
-g
# -O0
# -Ofast
)
file(GLOB_RECURSE SOURCES
./*.c
./*.cpp
../custom_prephrals.cpp
)
add_executable(${EXAMPLE_NAME}.elf ${SOURCES} ${LINKER_SCRIPT} ${LIB_SOURCES})
set(HEX_FILE ${EXAMPLE_NAME}.hex)
set(BIN_FILE ${EXAMPLE_NAME}.bin)
add_custom_command(TARGET ${EXAMPLE_NAME}.elf POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${HEX_FILE}
COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${BIN_FILE}
COMMENT "Building ${HEX_FILE}
Building ${BIN_FILE}")

51
stm32u5/examples/cam_board/sdcard/ex_sdcard.cpp Executable file
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//#include "gpio.h"
#include "bsp.h"
#include "delay.h"
#include "custom_prephrals.h"
#include "fx_api.h"
extern "C" {
VOID fx_ggeta_driver(FX_MEDIA *media_ptr);
}
FX_MEDIA sdio_disk;
FX_FILE file;
UINT status;
UINT media_memory[1024];
int main() {
system_init();
// setup_pins();
setup_pins();
setup_prepherials();
led1.set_low();
led3.set_high();
delay.delay_ms(200);
sdmmc2.sdmmc_init();
delay.delay_ms(200);
uint8_t buffer[1024] = {0};
uint8_t buffer1[1024] = {0};
delay_ms(100, true);
status = fx_media_open(&sdio_disk, "STM32_SDIO", fx_ggeta_driver, 0, (VOID *) media_memory, sizeof(media_memory));
ULONG BYTES;
fx_media_space_available(&sdio_disk, &BYTES);
// printf("BYTES: %lu\n", BYTES);
status = fx_file_create(&sdio_disk, "newmake.txt");
status = fx_file_open(&sdio_disk, &file, "newmake.txt", FX_OPEN_FOR_WRITE);
status = fx_file_seek(&file, 0);
uint8_t data[20] = "qqqasdfsafsdf2\n";
status = fx_file_write(&file, data, 16);
status = fx_file_close(&file);
status = fx_media_close(&sdio_disk);
led1.set_high();
led2.set_high();
while (1) {
}
}

269
stm32u5/examples/cam_board/sdcard/fx_stm32_sd_driver.cpp Executable file
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#include "fx_api.h"
#include "sdmmc.h"
#include <stdio.h>
#include "prepherials.h"
extern "C" {
UINT _fx_partition_offset_calculate(void *partition_sector, UINT partition,
ULONG *partition_start, ULONG *partition_size);
ULONG partition_start;
ULONG partition_size;
VOID fx_ggeta_driver(FX_MEDIA *media_ptr) {
hal_status_e ret;
switch (media_ptr->fx_media_driver_request) {
case FX_DRIVER_INIT: {
// sdcard will be init_old by the user sperately
media_ptr->fx_media_driver_status = FX_SUCCESS;
break;
}
case FX_DRIVER_UNINIT:
break;
case FX_DRIVER_READ:
ret = sdmmc2.sdmmc_read_multiple_block((uint32_t)media_ptr->fx_media_driver_buffer,
media_ptr->fx_media_driver_logical_sector +
media_ptr->fx_media_hidden_sectors,
media_ptr->fx_media_driver_sectors);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
case FX_DRIVER_WRITE:
ret = sdmmc2.sdmmc_write_multiple_block((uint32_t)media_ptr->fx_media_driver_buffer,
media_ptr->fx_media_driver_logical_sector +
media_ptr->fx_media_hidden_sectors,
media_ptr->fx_media_driver_sectors);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
case FX_DRIVER_BOOT_READ:
ret = sdmmc2.sdmmc_read_multiple_block((uint32_t)media_ptr->fx_media_driver_buffer, 0,
media_ptr->fx_media_driver_sectors);
_fx_partition_offset_calculate(media_ptr->fx_media_driver_buffer, 0, &partition_start,
&partition_size);
IF_ERROR_STUCK(ret);
ret = sdmmc2.sdmmc_read_multiple_block((uint32_t)media_ptr->fx_media_driver_buffer,
partition_start, media_ptr->fx_media_driver_sectors);
IF_ERROR_STUCK(ret);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
case FX_DRIVER_BOOT_WRITE: {
// ret = sdmmc_write_multiple_block(sd1,
// (uint32_t) media_ptr->fx_media_driver_buffer,
// partition_start,
// 1);
ret = sdmmc2.sdmmc_write_single_block((uint32_t)media_ptr->fx_media_driver_buffer,
partition_start);
IF_ERROR_STUCK(ret);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
}
default:
media_ptr->fx_media_driver_status = FX_NOT_IMPLEMENTED;
break;
}
}
}
//void fx_stm32_sd_driver(FX_MEDIA *media_ptr) {
// UINT status;
// UINT unaligned_buffer;
// ULONG partition_start;
// ULONG partition_size;
//
//#if (FX_STM32_SD_INIT == 0)
// /* the SD was initialized by the application */
// is_initialized = 1;
//#endif
// /* before performing any operation, check the status of the SD IP */
// if (is_initialized == 1) {
// if (check_sd_status(FX_STM32_SD_INSTANCE) != 0) {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// return;
// }
// }
//
//#if (FX_STM32_SD_DMA_API == 1)
// /* the SD DMA requires a 4-byte aligned buffers */
// unaligned_buffer = (UINT)(media_ptr->fx_media_driver_buffer) & 0x3;
//#else
// /* if the DMA is not used there isn't any constraint on buffer alignment */
// unaligned_buffer = 0;
//#endif
// /* Process the driver request specified in the media control block. */
// switch (media_ptr->fx_media_driver_request) {
// case FX_DRIVER_INIT: {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
//
// FX_STM32_SD_PRE_INIT(media_ptr);
//
//#if (FX_STM32_SD_INIT == 1)
// /* Initialize the SD instance */
// if (is_initialized == 0)
// {
// status = fx_stm32_sd_init(FX_STM32_SD_INSTANCE);
//
// if (status == 0)
// {
// is_initialized = 1;
// }
// else
// {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// }
// }
//#endif
// /* call post init_old user macro */
// FX_STM32_SD_POST_INIT(media_ptr);
// break;
// }
//
// case FX_DRIVER_UNINIT: {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
//
//#if (FX_STM32_SD_INIT == 1)
// status = fx_stm32_sd_deinit(FX_STM32_SD_INSTANCE);
//
// if (status != 0)
// {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// }
// else
// {
// is_initialized = 0;
// }
//#endif
// /* call post deinit processing */
// FX_STM32_SD_POST_DEINIT(media_ptr);
//
// break;
// }
//
// case FX_DRIVER_READ: {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
//
// if (sd_read_data(media_ptr, media_ptr->fx_media_driver_logical_sector + media_ptr->fx_media_hidden_sectors,
// media_ptr->fx_media_driver_sectors, unaligned_buffer) == FX_SUCCESS) {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// }
//
// break;
// }
//
// case FX_DRIVER_WRITE: {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
//
// if (sd_write_data(media_ptr, media_ptr->fx_media_driver_logical_sector + media_ptr->fx_media_hidden_sectors,
// media_ptr->fx_media_driver_sectors, unaligned_buffer) == FX_SUCCESS) {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// }
//
// break;
// }
//
// case FX_DRIVER_FLUSH: {
// /* Return driver success. */
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// break;
// }
//
// case FX_DRIVER_ABORT: {
// /* Return driver success. */
// media_ptr->fx_media_driver_status = FX_SUCCESS;
//
// FX_STM32_SD_POST_ABORT(media_ptr);
// break;
// }
//
// case FX_DRIVER_BOOT_READ: {
// /* the boot sector is the sector zero */
// status = sd_read_data(media_ptr, 0, media_ptr->fx_media_driver_sectors, unaligned_buffer);
//
// if (status != FX_SUCCESS) {
// media_ptr->fx_media_driver_status = status;
// break;
// }
//
// /* Check if the sector 0 is the actual boot sector, otherwise calculate the offset into it.
// Please note that this should belong to higher level of MW to do this check and it is here
// as a temporary work solution */
//
// partition_start = 0;
//
// status = _fx_partition_offset_calculate(media_ptr->fx_media_driver_buffer, 0,
// &partition_start, &partition_size);
//
// /* Check partition read error. */
// if (status) {
// /* Unsuccessful driver request. */
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// break;
// }
//
// /* Now determine if there is a partition... */
// if (partition_start) {
//
// if (check_sd_status(FX_STM32_SD_INSTANCE) != 0) {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// break;
// }
//
// /* Yes, now lets read the actual boot record. */
// status = sd_read_data(media_ptr, partition_start, media_ptr->fx_media_driver_sectors, unaligned_buffer);
//
// if (status != FX_SUCCESS) {
// media_ptr->fx_media_driver_status = status;
// break;
// }
// }
//
// /* Successful driver request. */
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// break;
// }
//
// case FX_DRIVER_BOOT_WRITE: {
// status = sd_write_data(media_ptr, 0, media_ptr->fx_media_driver_sectors, unaligned_buffer);
//
// media_ptr->fx_media_driver_status = status;
//
// break;
// }
//
// default: {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// break;
// }
// }
//}
/**
* @brief Read data from uSD into destination buffer
* @param FX_MEDIA *media_ptr a pointer the main FileX structure
* @param ULONG start_sector first sector to start reading from
* @param UINT num_sectors number of sectors to be read
* @param UINT use_scratch_buffer to enable scratch buffer usage or not.
* @retval FX_SUCCESS on success FX_BUFFER_ERROR / FX_ACCESS_ERROR / FX_IO_ERROR otherwise
*/
//static UINT sd_read_data(FX_MEDIA *media_ptr, ULONG start_sector, UINT num_sectors, UINT use_scratch_buffer)
/**
* @brief write data buffer into the uSD
* @param FX_MEDIA *media_ptr a pointer the main FileX structure
* @param ULONG start_sector first sector to start writing from
* @param UINT num_sectors number of sectors to be written
* @param UINT use_scratch_buffer to enable scratch buffer usage or not.
* @retval FX_SUCCESS on success FX_BUFFER_ERROR / FX_ACCESS_ERROR / FX_IO_ERROR otherwise
*/
// static UINT sd_write_data(FX_MEDIA *media_ptr, ULONG start_sector, UINT num_sectors, UINT use_scratch_buffer);

47
stm32u5/examples/cam_board/sdcard_ov2640/CMakeLists.txt Executable file
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cmake_minimum_required(VERSION 3.23)
set(CMAKE_C_COMPILER_WORKS 1)
set(CMAKE_CXX_COMPILER_WORKS 1)
project(ov2640 LANGUAGES C CXX ASM)
set(EXAMPLE_NAME "cam_sdcard_ov2640")
set(CMAKE_EXPORT_COMPILE_COMMANDS on) # for clangd
### set includes and library
set(Stm32U5Lib_DIR ../../../)
find_package(Stm32U5Lib REQUIRED)
add_definitions(-DSTM32U575xx)
include_directories(./ ../)
add_compile_options(
-g
-O0
# -Ofast
)
file(GLOB_RECURSE SOURCES
main.cpp
../custom_prephrals.cpp
./fx_stm32_sd_driver.cpp
../../../startup/startup_stm32u575zitxq.s
./ov2640.cpp
)
if(NOT LIB_SOURCES)
message(STATUS "LIB_SOURCES is empty")
add_executable(${EXAMPLE_NAME}.elf ${SOURCES} ${LINKER_SCRIPT})
# add the library to the target
target_link_libraries(${EXAMPLE_NAME}.elf ${LIB_BIN})
else()
message(STATUS "LIB_SOURCES is not empty")
add_executable(${EXAMPLE_NAME}.elf ${SOURCES} ${LINKER_SCRIPT} ${LIB_SOURCES})
endif()
set(HEX_FILE ${EXAMPLE_NAME}.hex)
set(BIN_FILE ${EXAMPLE_NAME}.bin)
add_custom_command(TARGET ${EXAMPLE_NAME}.elf POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${HEX_FILE}
COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${BIN_FILE}
COMMENT "Building ${HEX_FILE}
Building ${BIN_FILE}")

270
stm32u5/examples/cam_board/sdcard_ov2640/fx_stm32_sd_driver.cpp Executable file
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#include "fx_api.h"
#include "sdmmc.h"
#include <stdio.h>
#include "prepherials.h"
extern "C" {
UINT
_fx_partition_offset_calculate(void *partition_sector, UINT partition, ULONG *partition_start, ULONG *partition_size);
ULONG partition_start;
ULONG partition_size;
VOID fx_ggeta_driver(FX_MEDIA *media_ptr) {
hal_status_e ret;
switch (media_ptr->fx_media_driver_request) {
case FX_DRIVER_INIT: {
// sdcard will be init_old by the user sperately
media_ptr->fx_media_driver_status = FX_SUCCESS;
break;
}
case FX_DRIVER_UNINIT:
break;
case FX_DRIVER_READ:
ret = sdmmc2.sdmmc_read_multiple_block((uint32_t) media_ptr->fx_media_driver_buffer,
media_ptr->fx_media_driver_logical_sector +
media_ptr->fx_media_hidden_sectors,
media_ptr->fx_media_driver_sectors);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
case FX_DRIVER_WRITE:
ret = sdmmc2.sdmmc_write_multiple_block((uint32_t) media_ptr->fx_media_driver_buffer,
media_ptr->fx_media_driver_logical_sector +
media_ptr->fx_media_hidden_sectors,
media_ptr->fx_media_driver_sectors);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
case FX_DRIVER_BOOT_READ:
ret = sdmmc2.sdmmc_read_multiple_block((uint32_t) media_ptr->fx_media_driver_buffer, 0,
media_ptr->fx_media_driver_sectors);
_fx_partition_offset_calculate(media_ptr->fx_media_driver_buffer, 0, &partition_start, &partition_size);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else {
media_ptr->fx_media_driver_status = FX_IO_ERROR;
return;
}
ret = sdmmc2.sdmmc_read_multiple_block((uint32_t) media_ptr->fx_media_driver_buffer, partition_start,
media_ptr->fx_media_driver_sectors);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
case FX_DRIVER_BOOT_WRITE: {
// ret = sdmmc_write_multiple_block(sd1,
// (uint32_t) media_ptr->fx_media_driver_buffer,
// partition_start,
// 1);
ret = sdmmc2.sdmmc_write_single_block((uint32_t) media_ptr->fx_media_driver_buffer, partition_start);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
}
default:
media_ptr->fx_media_driver_status = FX_NOT_IMPLEMENTED;
break;
}
}
}
//void fx_stm32_sd_driver(FX_MEDIA *media_ptr) {
// UINT status;
// UINT unaligned_buffer;
// ULONG partition_start;
// ULONG partition_size;
//
//#if (FX_STM32_SD_INIT == 0)
// /* the SD was initialized by the application */
// is_initialized = 1;
//#endif
// /* before performing any operation, check the status of the SD IP */
// if (is_initialized == 1) {
// if (check_sd_status(FX_STM32_SD_INSTANCE) != 0) {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// return;
// }
// }
//
//#if (FX_STM32_SD_DMA_API == 1)
// /* the SD DMA requires a 4-byte aligned buffers */
// unaligned_buffer = (UINT)(media_ptr->fx_media_driver_buffer) & 0x3;
//#else
// /* if the DMA is not used there isn't any constraint on buffer alignment */
// unaligned_buffer = 0;
//#endif
// /* Process the driver request specified in the media control block. */
// switch (media_ptr->fx_media_driver_request) {
// case FX_DRIVER_INIT: {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
//
// FX_STM32_SD_PRE_INIT(media_ptr);
//
//#if (FX_STM32_SD_INIT == 1)
// /* Initialize the SD instance */
// if (is_initialized == 0)
// {
// status = fx_stm32_sd_init(FX_STM32_SD_INSTANCE);
//
// if (status == 0)
// {
// is_initialized = 1;
// }
// else
// {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// }
// }
//#endif
// /* call post init_old user macro */
// FX_STM32_SD_POST_INIT(media_ptr);
// break;
// }
//
// case FX_DRIVER_UNINIT: {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
//
//#if (FX_STM32_SD_INIT == 1)
// status = fx_stm32_sd_deinit(FX_STM32_SD_INSTANCE);
//
// if (status != 0)
// {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// }
// else
// {
// is_initialized = 0;
// }
//#endif
// /* call post deinit processing */
// FX_STM32_SD_POST_DEINIT(media_ptr);
//
// break;
// }
//
// case FX_DRIVER_READ: {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
//
// if (sd_read_data(media_ptr, media_ptr->fx_media_driver_logical_sector + media_ptr->fx_media_hidden_sectors,
// media_ptr->fx_media_driver_sectors, unaligned_buffer) == FX_SUCCESS) {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// }
//
// break;
// }
//
// case FX_DRIVER_WRITE: {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
//
// if (sd_write_data(media_ptr, media_ptr->fx_media_driver_logical_sector + media_ptr->fx_media_hidden_sectors,
// media_ptr->fx_media_driver_sectors, unaligned_buffer) == FX_SUCCESS) {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// }
//
// break;
// }
//
// case FX_DRIVER_FLUSH: {
// /* Return driver success. */
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// break;
// }
//
// case FX_DRIVER_ABORT: {
// /* Return driver success. */
// media_ptr->fx_media_driver_status = FX_SUCCESS;
//
// FX_STM32_SD_POST_ABORT(media_ptr);
// break;
// }
//
// case FX_DRIVER_BOOT_READ: {
// /* the boot sector is the sector zero */
// status = sd_read_data(media_ptr, 0, media_ptr->fx_media_driver_sectors, unaligned_buffer);
//
// if (status != FX_SUCCESS) {
// media_ptr->fx_media_driver_status = status;
// break;
// }
//
// /* Check if the sector 0 is the actual boot sector, otherwise calculate the offset into it.
// Please note that this should belong to higher level of MW to do this check and it is here
// as a temporary work solution */
//
// partition_start = 0;
//
// status = _fx_partition_offset_calculate(media_ptr->fx_media_driver_buffer, 0,
// &partition_start, &partition_size);
//
// /* Check partition read error. */
// if (status) {
// /* Unsuccessful driver request. */
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// break;
// }
//
// /* Now determine if there is a partition... */
// if (partition_start) {
//
// if (check_sd_status(FX_STM32_SD_INSTANCE) != 0) {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// break;
// }
//
// /* Yes, now lets read the actual boot record. */
// status = sd_read_data(media_ptr, partition_start, media_ptr->fx_media_driver_sectors, unaligned_buffer);
//
// if (status != FX_SUCCESS) {
// media_ptr->fx_media_driver_status = status;
// break;
// }
// }
//
// /* Successful driver request. */
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// break;
// }
//
// case FX_DRIVER_BOOT_WRITE: {
// status = sd_write_data(media_ptr, 0, media_ptr->fx_media_driver_sectors, unaligned_buffer);
//
// media_ptr->fx_media_driver_status = status;
//
// break;
// }
//
// default: {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// break;
// }
// }
//}
/**
* @brief Read data from uSD into destination buffer
* @param FX_MEDIA *media_ptr a pointer the main FileX structure
* @param ULONG start_sector first sector to start reading from
* @param UINT num_sectors number of sectors to be read
* @param UINT use_scratch_buffer to enable scratch buffer usage or not.
* @retval FX_SUCCESS on success FX_BUFFER_ERROR / FX_ACCESS_ERROR / FX_IO_ERROR otherwise
*/
//static UINT sd_read_data(FX_MEDIA *media_ptr, ULONG start_sector, UINT num_sectors, UINT use_scratch_buffer)
/**
* @brief write data buffer into the uSD
* @param FX_MEDIA *media_ptr a pointer the main FileX structure
* @param ULONG start_sector first sector to start writing from
* @param UINT num_sectors number of sectors to be written
* @param UINT use_scratch_buffer to enable scratch buffer usage or not.
* @retval FX_SUCCESS on success FX_BUFFER_ERROR / FX_ACCESS_ERROR / FX_IO_ERROR otherwise
*/
// static UINT sd_write_data(FX_MEDIA *media_ptr, ULONG start_sector, UINT num_sectors, UINT use_scratch_buffer);

89
stm32u5/examples/cam_board/sdcard_ov2640/main.cpp Executable file
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#include "custom_prephrals.h"
#include <string>
#include "ov2640.h"
#include "fx_api.h"
#define OV2640_I2C_ADDR 0x60
#define PICTURE_BUFFER_SIZE 60000
uint32_t picture[PICTURE_BUFFER_SIZE];
extern "C" {
VOID fx_ggeta_driver(FX_MEDIA *media_ptr);
}
FX_MEDIA sdio_disk;
FX_FILE file;
UINT status;
UINT media_memory[1024];
int main() {
cam_board_init();
cam_resetb.set_high();
cam_pdwn.set_low();
led1.set_high();
delay_ms(200, true);
auto ret = sdmmc2.sdmmc_init();
while (ret != HAL_OK)
ret = sdmmc2.sdmmc_init();
led1.set_low();
ov2640_start();
status = fx_media_open(&sdio_disk, "STM32_SDIO", fx_ggeta_driver, 0, (VOID *) media_memory,
sizeof(media_memory));
dma10.init(86, DMA_DATA_WIDTH_32_BITS, DMA_DATA_WIDTH_32_BITS, DMA_ADDR_FIX, DMA_ADDR_INC, DMA_TYPE_PREPHERIAL,
DMA_TYPE_MEMORY, PICTURE_BUFFER_SIZE * 5);
dcmi.init_old();
int pic_cnt = 0;
status = 0;
// status = fx_media_open(&sdio_disk, (char *) "STM32_SDIO", fx_ggeta_driver, 0, (VOID *) media_memory, sizeof(media_memory));
while (1) {
dma10.dma_start((uint32_t) &DCMI->DR, (uint32_t) picture, 4 * PICTURE_BUFFER_SIZE);
// first few frames may cause green screen, if so we can extend the Delay to skip them.
delay_ms(300, true); // wait for camera to be ready -- skip first frame 12.5fps = 80ms
dcmi.enable();
dcmi.capture_enable();
// delay_s(2, true); // wait for picture to be captured then stop dma
delay.delay_ms(1000);
dma10.dma_stop();
dcmi.capture_disable();
dcmi.disable();
auto *tmp = (uint8_t *) picture;
uint32_t i = 0;
for (i = 0; i < 4 * PICTURE_BUFFER_SIZE - 1; i++) {
if (tmp[i] == 0xff && tmp[i + 1] == 0xd9) {
break;
}
}
if (i == 4 * PICTURE_BUFFER_SIZE - 1) {
continue;
}
// cam_pdwn.set_high();
// TIM1->CCER &= ~TIM_CCER_CC1E;
std::string file_name = "picture" + std::to_string(pic_cnt) + ".jpg";
pic_cnt++;
status = fx_file_create(&sdio_disk, (char *) file_name.c_str());
if (status == FX_ALREADY_CREATED) {
// delete file and create empty file
status = fx_file_delete(&sdio_disk, (char *) file_name.c_str());
status = fx_file_create(&sdio_disk, (char *) file_name.c_str());
}
status = fx_file_open(&sdio_disk, &file, (char *) file_name.c_str(), FX_OPEN_FOR_WRITE);
status = fx_file_seek(&file, 0);
status = fx_file_write(&file, (uint8_t *) picture, i+1);
status = fx_file_close(&file);
status = fx_media_flush(&sdio_disk);
// status = fx_media_close(&sdio_disk);
if (status != FX_SUCCESS) {
status = 0;
continue;
}
status = 0;
led2.set_high();
delay.delay_ms(100);
led2.set_low();
memset(picture, 0, PICTURE_BUFFER_SIZE * 4);
// TIM1->CCER |= TIM_CCER_CC1E;
// cam_pdwn.set_low();
}
}

753
stm32u5/examples/cam_board/sdcard_ov2640/ov2640.cpp Executable file
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//
// Created by Guangzong Chen on 2/8/23.
//
#include "ov2640.h"
#include <stdint.h>
#include <stm32u5xx.h>
//#include "prepherials.h"
#include "custom_prephrals.h"
#define OV2640_I2C_ADDR 0x60
const unsigned char OV2640_JPEG_INIT[][2] = {{0xff, 0x00},
{0x2c, 0xff},
{0x2e, 0xdf},
{0xff, 0x01},
{0x3c, 0x32},
{0x11, 0x00},
{0x09, 0x02},
{0x04, 0x28},
{0x13, 0xe5},
{0x14, 0x48},
{0x2c, 0x0c},
{0x33, 0x78},
{0x3a, 0x33},
{0x3b, 0xfB},
{0x3e, 0x00},
{0x43, 0x11},
{0x16, 0x10},
{0x39, 0x92},
{0x35, 0xda},
{0x22, 0x1a},
{0x37, 0xc3},
{0x23, 0x00},
{0x34, 0xc0},
{0x36, 0x1a},
{0x06, 0x88},
{0x07, 0xc0},
{0x0d, 0x87},
{0x0e, 0x41},
{0x4c, 0x00},
{0x48, 0x00},
{0x5B, 0x00},
{0x42, 0x03},
{0x4a, 0x81},
{0x21, 0x99},
{0x24, 0x40},
{0x25, 0x38},
{0x26, 0x82},
{0x5c, 0x00},
{0x63, 0x00},
{0x61, 0x70},
{0x62, 0x80},
{0x7c, 0x05},
{0x20, 0x80},
{0x28, 0x30},
{0x6c, 0x00},
{0x6d, 0x80},
{0x6e, 0x00},
{0x70, 0x02},
{0x71, 0x94},
{0x73, 0xc1},
{0x12, 0x40},
{0x17, 0x11},
{0x18, 0x43},
{0x19, 0x00},
{0x1a, 0x4b},
{0x32, 0x09},
{0x37, 0xc0},
{0x4f, 0x60},
{0x50, 0xa8},
{0x6d, 0x00},
{0x3d, 0x38},
{0x46, 0x3f},
{0x4f, 0x60},
{0x0c, 0x3c},
{0xff, 0x00},
{0xe5, 0x7f},
{0xf9, 0xc0},
{0x41, 0x24},
{0xe0, 0x14},
{0x76, 0xff},
{0x33, 0xa0},
{0x42, 0x20},
{0x43, 0x18},
{0x4c, 0x00},
{0x87, 0xd5},
{0x88, 0x3f},
{0xd7, 0x03},
{0xd9, 0x10},
{0xd3, 0x82},
{0xc8, 0x08},
{0xc9, 0x80},
{0x7c, 0x00},
{0x7d, 0x00},
{0x7c, 0x03},
{0x7d, 0x48},
{0x7d, 0x48},
{0x7c, 0x08},
{0x7d, 0x20},
{0x7d, 0x10},
{0x7d, 0x0e},
{0x90, 0x00},
{0x91, 0x0e},
{0x91, 0x1a},
{0x91, 0x31},
{0x91, 0x5a},
{0x91, 0x69},
{0x91, 0x75},
{0x91, 0x7e},
{0x91, 0x88},
{0x91, 0x8f},
{0x91, 0x96},
{0x91, 0xa3},
{0x91, 0xaf},
{0x91, 0xc4},
{0x91, 0xd7},
{0x91, 0xe8},
{0x91, 0x20},
{0x92, 0x00},
{0x93, 0x06},
{0x93, 0xe3},
{0x93, 0x05},
{0x93, 0x05},
{0x93, 0x00},
{0x93, 0x04},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x96, 0x00},
{0x97, 0x08},
{0x97, 0x19},
{0x97, 0x02},
{0x97, 0x0c},
{0x97, 0x24},
{0x97, 0x30},
{0x97, 0x28},
{0x97, 0x26},
{0x97, 0x02},
{0x97, 0x98},
{0x97, 0x80},
{0x97, 0x00},
{0x97, 0x00},
{0xc3, 0xed},
{0xa4, 0x00},
{0xa8, 0x00},
{0xc5, 0x11},
{0xc6, 0x51},
{0xbf, 0x80},
{0xc7, 0x10},
{0xb6, 0x66},
{0xb8, 0xA5},
{0xb7, 0x64},
{0xb9, 0x7C},
{0xb3, 0xaf},
{0xb4, 0x97},
{0xb5, 0xFF},
{0xb0, 0xC5},
{0xb1, 0x94},
{0xb2, 0x0f},
{0xc4, 0x5c},
{0xc0, 0x64},
{0xc1, 0x4B},
{0x8c, 0x00},
{0x86, 0x3D},
{0x50, 0x00},
{0x51, 0xC8},
{0x52, 0x96},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x00},
{0x5a, 0xC8},
{0x5b, 0x96},
{0x5c, 0x00},
{0xd3, 0x00},
{0xc3, 0xed},
{0x7f, 0x00},
{0xda, 0x00},
{0xe5, 0x1f},
{0xe1, 0x67},
{0xe0, 0x00},
{0xdd, 0x7f},
{0x05, 0x00},
{0x12, 0x40},
{0xd3, 0x04},
{0xc0, 0x16},
{0xC1, 0x12},
{0x8c, 0x00},
{0x86, 0x3d},
{0x50, 0x00},
{0x51, 0x2C},
{0x52, 0x24},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x00},
{0x5A, 0x2c},
{0x5b, 0x24},
{0x5c, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_YUV422[][2] = {{0xFF, 0x00},
{0x05, 0x00},
{0xDA, 0x10},
{0xD7, 0x03},
{0xDF, 0x00},
{0x33, 0x80},
{0x3C, 0x40},
{0xe1, 0x77},
{0x00, 0x00},
{0xff, 0xff},};
const unsigned char OV2640_JPEG[][2] = {{0xe0, 0x14},
{0xe1, 0x77},
{0xe5, 0x1f},
{0xd7, 0x03},
{0xda, 0x10},
{0xe0, 0x00},
{0xFF, 0x01},
{0x04, 0x08},
{0xff, 0xff},};
const unsigned char OV2640_160x120_JPEG[][2] = {{0xFF, 0x01},
{0x12, 0x40},
{0x17, 0x11},
{0x18, 0x43},
{0x19, 0x00},
{0x1a, 0x4b},
{0x32, 0x09},
{0x4f, 0xca},
{0x50, 0xa8},
{0x5a, 0x23},
{0x6d, 0x00},
{0x39, 0x12},
{0x35, 0xda},
{0x22, 0x1a},
{0x37, 0xc3},
{0x23, 0x00},
{0x34, 0xc0},
{0x36, 0x1a},
{0x06, 0x88},
{0x07, 0xc0},
{0x0d, 0x87},
{0x0e, 0x41},
{0x4c, 0x00},
{0xFF, 0x00},
{0xe0, 0x04},
{0xc0, 0x64},
{0xc1, 0x4b},
{0x86, 0x35},
{0x50, 0x92},
{0x51, 0xc8},
{0x52, 0x96},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x00},
{0x57, 0x00},
{0x5a, 0x2c},
{0x5b, 0x24},
{0x5c, 0x00},
{0xe0, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_320x240_JPEG[][2] = {{0xff, 0x01},
{0x12, 0x40},
{0x17, 0x11},
{0x18, 0x43},
{0x19, 0x00},
{0x1a, 0x4b},
{0x32, 0x09},
{0x4f, 0xca},
{0x50, 0xa8},
{0x5a, 0x23},
{0x6d, 0x00},
{0x39, 0x12},
{0x35, 0xda},
{0x22, 0x1a},
{0x37, 0xc3},
{0x23, 0x00},
{0x34, 0xc0},
{0x36, 0x1a},
{0x06, 0x88},
{0x07, 0xc0},
{0x0d, 0x87},
{0x0e, 0x41},
{0x4c, 0x00},
{0xff, 0x00},
{0xe0, 0x04},
{0xc0, 0x64},
{0xc1, 0x4b},
{0x86, 0x35},
{0x50, 0x89},
{0x51, 0xc8},
{0x52, 0x96},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x00},
{0x57, 0x00},
{0x5a, 0x50},
{0x5b, 0x3c},
{0x5c, 0x00},
{0xe0, 0x00},
{0xff, 0xff},};
const unsigned char OV2640_640x480_JPEG[][2] = {{0xff, 0x01},
{0x11, 0x01},
{0x12, 0x00},
{0x17, 0x11},
{0x18, 0x75},
{0x32, 0x36},
{0x19, 0x01},
{0x1a, 0x97},
{0x03, 0x0f},
{0x37, 0x40},
{0x4f, 0xbb},
{0x50, 0x9c},
{0x5a, 0x57},
{0x6d, 0x80},
{0x3d, 0x34},
{0x39, 0x02},
{0x35, 0x88},
{0x22, 0x0a},
{0x37, 0x40},
{0x34, 0xa0},
{0x06, 0x02},
{0x0d, 0xb7},
{0x0e, 0x01},
{0xff, 0x00},
{0xe0, 0x04},
{0xc0, 0xc8},
{0xc1, 0x96},
{0x86, 0x3d},
{0x50, 0x89},
{0x51, 0x90},
{0x52, 0x2c},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x88},
{0x57, 0x00},
{0x5a, 0xa0},
{0x5b, 0x78},
{0x5c, 0x00},
{0xd3, 0x04},
{0xe0, 0x00},
{0xff, 0xff},};
const unsigned char OV2640_800x600_JPEG[][2] = {{0xFF, 0x01},
{0x11, 0x01},
{0x12, 0x00},
{0x17, 0x11},
{0x18, 0x75},
{0x32, 0x36},
{0x19, 0x01},
{0x1a, 0x97},
{0x03, 0x0f},
{0x37, 0x40},
{0x4f, 0xbb},
{0x50, 0x9c},
{0x5a, 0x57},
{0x6d, 0x80},
{0x3d, 0x34},
{0x39, 0x02},
{0x35, 0x88},
{0x22, 0x0a},
{0x37, 0x40},
{0x34, 0xa0},
{0x06, 0x02},
{0x0d, 0xb7},
{0x0e, 0x01},
{0xFF, 0x00},
{0xe0, 0x04},
{0xc0, 0xc8},
{0xc1, 0x96},
{0x86, 0x35},
{0x50, 0x89},
{0x51, 0x90},
{0x52, 0x2c},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x88},
{0x57, 0x00},
{0x5a, 0xc8},
{0x5b, 0x96},
{0x5c, 0x00},
{0xd3, 0x02},
{0xe0, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_1024x768_JPEG[][2] = {{0xFF, 0x01},
{0x11, 0x01},
{0x12, 0x00},
{0x17, 0x11},
{0x18, 0x75},
{0x32, 0x36},
{0x19, 0x01},
{0x1a, 0x97},
{0x03, 0x0f},
{0x37, 0x40},
{0x4f, 0xbb},
{0x50, 0x9c},
{0x5a, 0x57},
{0x6d, 0x80},
{0x3d, 0x34},
{0x39, 0x02},
{0x35, 0x88},
{0x22, 0x0a},
{0x37, 0x40},
{0x34, 0xa0},
{0x06, 0x02},
{0x0d, 0xb7},
{0x0e, 0x01},
{0xFF, 0x00},
{0xc0, 0xC8},
{0xc1, 0x96},
{0x8c, 0x00},
{0x86, 0x3D},
{0x50, 0x00},
{0x51, 0x90},
{0x52, 0x2C},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x88},
{0x5a, 0x00},
{0x5b, 0xC0},
{0x5c, 0x01},
{0xd3, 0x02},
{0xff, 0xff}};
const unsigned char OV2640_1280x960_JPEG[][2] = {{0xFF, 0x01},
{0x11, 0x01},
{0x12, 0x00},
{0x17, 0x11},
{0x18, 0x75},
{0x32, 0x36},
{0x19, 0x01},
{0x1a, 0x97},
{0x03, 0x0f},
{0x37, 0x40},
{0x4f, 0xbb},
{0x50, 0x9c},
{0x5a, 0x57},
{0x6d, 0x80},
{0x3d, 0x34},
{0x39, 0x02},
{0x35, 0x88},
{0x22, 0x0a},
{0x37, 0x40},
{0x34, 0xa0},
{0x06, 0x02},
{0x0d, 0xb7},
{0x0e, 0x01},
{0xFF, 0x00},
{0xe0, 0x04},
{0xc0, 0xc8},
{0xc1, 0x96},
{0x86, 0x3d},
{0x50, 0x00},
{0x51, 0x90},
{0x52, 0x2c},
{0x53, 0x00},
{0x54, 0x00},
{0x55, 0x88},
{0x57, 0x00},
{0x5a, 0x40},
{0x5b, 0xf0},
{0x5c, 0x01},
{0xd3, 0x02},
{0xe0, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_CONTRAST2[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x07},
{0x7d, 0x20},
{0x7d, 0x28},
{0x7d, 0x0c},
{0x7d, 0x06},
{0xff, 0xff}};
const unsigned char OV2640_CONTRAST1[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x07},
{0x7d, 0x20},
{0x7d, 0x24},
{0x7d, 0x16},
{0x7d, 0x06},
{0xff, 0xff}};
const unsigned char OV2640_CONTRAST0[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x07},
{0x7d, 0x20},
{0x7d, 0x20},
{0x7d, 0x20},
{0x7d, 0x06},
{0xff, 0xff}};
const unsigned char OV2640_CONTRAST_1[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x07},
{0x7d, 0x20},
{0x7d, 0x1c},
{0x7d, 0x2a},
{0x7d, 0x06},
{0xff, 0xff}};
const unsigned char OV2640_CONTRAST_2[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x07},
{0x7d, 0x20},
{0x7d, 0x18},
{0x7d, 0x34},
{0x7d, 0x06},
{0xff, 0xff}};
const unsigned char OV2640_SATURATION2[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x02},
{0x7c, 0x03},
{0x7d, 0x68},
{0x7d, 0x68},
{0xff, 0xff}};
const unsigned char OV2640_SATURATION1[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x02},
{0x7c, 0x03},
{0x7d, 0x58},
{0x7d, 0x68},
{0xff, 0xff}};
const unsigned char OV2640_SATURATION0[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x02},
{0x7c, 0x03},
{0x7d, 0x48},
{0x7d, 0x48},
{0xff, 0xff}};
const unsigned char OV2640_SATURATION_1[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x02},
{0x7c, 0x03},
{0x7d, 0x38},
{0x7d, 0x38},
{0xff, 0xff}};
const unsigned char OV2640_SATURATION_2[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x02},
{0x7c, 0x03},
{0x7d, 0x28},
{0x7d, 0x28},
{0xff, 0xff}};
const unsigned char OV2640_BRIGHTNESS2[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x09},
{0x7d, 0x40},
{0x7d, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_BRIGHTNESS1[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x09},
{0x7d, 0x30},
{0x7d, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_BRIGHTNESS0[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x09},
{0x7d, 0x20},
{0x7d, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_BRIGHTNESS_1[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x09},
{0x7d, 0x10},
{0x7d, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_BRIGHTNESS_2[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x04},
{0x7c, 0x09},
{0x7d, 0x00},
{0x7d, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_NORMAL[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x00},
{0x7c, 0x05},
{0x7d, 0x80},
{0x7d, 0x80},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_ANTIQUE[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x18},
{0x7c, 0x05},
{0x7d, 0x40},
{0x7d, 0xa6},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_BLACK_NEGATIVE[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x58},
{0x7c, 0x05},
{0x7d, 0x80},
{0x7d, 0x80},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_BLUISH[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x18},
{0x7c, 0x05},
{0x7d, 0xa0},
{0x7d, 0x40},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_BLACK[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x18},
{0x7c, 0x05},
{0x7d, 0x80},
{0x7d, 0x80},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_NEGATIVE[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x40},
{0x7c, 0x05},
{0x7d, 0x80},
{0x7d, 0x80},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_GREENISH[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x18},
{0x7c, 0x05},
{0x7d, 0x40},
{0x7d, 0x40},
{0xff, 0xff}};
const unsigned char OV2640_SPECIAL_EFFECTS_REDDISH[][2] = {{0xff, 0x00},
{0x7c, 0x00},
{0x7d, 0x18},
{0x7c, 0x05},
{0x7d, 0x40},
{0x7d, 0xc0},
{0xff, 0xff}};
const unsigned char OV2640_LIGHT_MODE_AUTO[][2] = {{0xff, 0x00},
{0xc7, 0x00},
{0xff, 0xff}};
const unsigned char OV2640_LIGHT_MODE_SUNNY[][2] = {{0xff, 0x00},
{0xc7, 0x40},
{0xcc, 0x5e},
{0xcd, 0x41},
{0xce, 0x54},
{0xff, 0xff}};
const unsigned char OV2640_LIGHT_MODE_CLOUDY[][2] = {{0xff, 0x00},
{0xc7, 0x40},
{0xcc, 0x65},
{0xcd, 0x41},
{0xce, 0x4f},
{0xff, 0xff}};
const unsigned char OV2640_LIGHT_MODE_OFFICE[][2] = {{0xff, 0x00},
{0xc7, 0x40},
{0xcc, 0x52},
{0xcd, 0x41},
{0xce, 0x66},
{0xff, 0xff}};
const unsigned char OV2640_LIGHT_MODE_HOME[][2] = {{0xff, 0x00},
{0xc7, 0x40},
{0xcc, 0x42},
{0xcd, 0x3f},
{0xce, 0x71},
{0xff, 0xff}};
/**
* this function should be after i2c and Delay init_old
*/
void ov2640_start() {
uint8_t data[2] = {0x00, 0x00};
// setup camera
data[0] = 0xff, data[1] = 0x01;
hal_status_e ret;
ret = cam_i2c.send(OV2640_I2C_ADDR, data, 2);
if (ret != HAL_OK)
while (true) {};
data[0] = 0x12, data[1] = 0x80;
delay_ms(100, true);
for (int i = 0; i < sizeof(OV2640_JPEG_INIT) / 2; i++) {
ret = cam_i2c.send(OV2640_I2C_ADDR, OV2640_JPEG_INIT[i], 2);
if (ret != HAL_OK)
while (true) {};
}
for (int i = 0; i < sizeof(OV2640_YUV422) / 2; i++) {
ret = cam_i2c.send(OV2640_I2C_ADDR, OV2640_YUV422[i], 2);
if (ret != HAL_OK)
while (true) {};
}
for (int i = 0; i < sizeof(OV2640_JPEG) / 2; i++) {
ret = cam_i2c.send(OV2640_I2C_ADDR, OV2640_JPEG[i], 2);
if (ret != HAL_OK)
while (true) {};
}
delay_ms(10, true);
data[0] = 0xff, data[1] = 0x01;
ret = cam_i2c.send(OV2640_I2C_ADDR, data, 2);
if (ret != HAL_OK)
while (true) {};
delay_ms(10, true);
data[0] = 0x15, data[1] = 0x00;
ret = cam_i2c.send(OV2640_I2C_ADDR, data, 2);
if (ret != HAL_OK)
while (true) {};
// for (auto i: OV2640_1280x960_JPEG) {
for (int i = 0; i < sizeof(OV2640_1280x960_JPEG) / 2; i++) {
ret = cam_i2c.send(OV2640_I2C_ADDR, OV2640_1280x960_JPEG[i], 2);
if (ret != HAL_OK)
while (true) {};
}
delay_ms(100, true);
}

8
stm32u5/examples/cam_board/sdcard_ov2640/ov2640.h Executable file
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@ -0,0 +1,8 @@
#ifndef OV2640_H
#define OV2640_H
//#include "tim.h"
void ov2640_start();
#endif //DCMI_OV2640_H

41
stm32u5/examples/cam_board/usb/CMakeLists.txt Executable file
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cmake_minimum_required(VERSION 3.23)
set(CMAKE_C_COMPILER_WORKS 1)
set(CMAKE_CXX_COMPILER_WORKS 1)
project(usb LANGUAGES C CXX ASM)
set(EXAMPLE_NAME "usb")
set(CMAKE_EXPORT_COMPILE_COMMANDS on) # for clangd
### set includes and library
set(Stm32U5Lib_DIR ../../../)
find_package(Stm32U5Lib REQUIRED)
include_directories(../)
file(GLOB_RECURSE SOURCES
main.cpp
../custom_prephrals.cpp
./fx_stm32_sd_driver.cpp
../../../startup/startup_stm32u575zitxq.s
)
#add_executable(${EXAMPLE_NAME}.elf ${SOURCES} ${LINKER_SCRIPT} ${LIB_BIN})
# if LIB_SOURCES is not empty, then add it to the target
if(NOT LIB_SOURCES)
message(STATUS "LIB_SOURCES is empty")
add_executable(${EXAMPLE_NAME}.elf ${SOURCES} ${LINKER_SCRIPT})
# add the library to the target
target_link_libraries(${EXAMPLE_NAME}.elf ${LIB_BIN})
else()
message(STATUS "LIB_SOURCES is not empty")
add_executable(${EXAMPLE_NAME}.elf ${SOURCES} ${LINKER_SCRIPT} ${LIB_SOURCES})
endif()
set(HEX_FILE ${EXAMPLE_NAME}.hex)
set(BIN_FILE ${EXAMPLE_NAME}.bin)
add_custom_command(TARGET ${EXAMPLE_NAME}.elf POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${HEX_FILE}
COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${EXAMPLE_NAME}.elf> ${BIN_FILE}
COMMENT "Building ${HEX_FILE}
Building ${BIN_FILE}")

270
stm32u5/examples/cam_board/usb/fx_stm32_sd_driver.cpp Executable file
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#include "fx_api.h"
#include "sdmmc.h"
#include <stdio.h>
#include "prepherials.h"
extern "C" {
UINT
_fx_partition_offset_calculate(void *partition_sector, UINT partition, ULONG *partition_start, ULONG *partition_size);
ULONG partition_start;
ULONG partition_size;
VOID fx_ggeta_driver(FX_MEDIA *media_ptr) {
hal_status_e ret;
switch (media_ptr->fx_media_driver_request) {
case FX_DRIVER_INIT: {
// sdcard will be init_old by the user sperately
media_ptr->fx_media_driver_status = FX_SUCCESS;
break;
}
case FX_DRIVER_UNINIT:
break;
case FX_DRIVER_READ:
ret = sdmmc2.sdmmc_read_multiple_block((uint32_t) media_ptr->fx_media_driver_buffer,
media_ptr->fx_media_driver_logical_sector +
media_ptr->fx_media_hidden_sectors,
media_ptr->fx_media_driver_sectors);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
case FX_DRIVER_WRITE:
ret = sdmmc2.sdmmc_write_multiple_block((uint32_t) media_ptr->fx_media_driver_buffer,
media_ptr->fx_media_driver_logical_sector +
media_ptr->fx_media_hidden_sectors,
media_ptr->fx_media_driver_sectors);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
case FX_DRIVER_BOOT_READ:
ret = sdmmc2.sdmmc_read_multiple_block((uint32_t) media_ptr->fx_media_driver_buffer, 0,
media_ptr->fx_media_driver_sectors);
_fx_partition_offset_calculate(media_ptr->fx_media_driver_buffer, 0, &partition_start, &partition_size);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else {
media_ptr->fx_media_driver_status = FX_IO_ERROR;
return;
}
ret = sdmmc2.sdmmc_read_multiple_block((uint32_t) media_ptr->fx_media_driver_buffer, partition_start,
media_ptr->fx_media_driver_sectors);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
case FX_DRIVER_BOOT_WRITE: {
// ret = sdmmc_write_multiple_block(sd1,
// (uint32_t) media_ptr->fx_media_driver_buffer,
// partition_start,
// 1);
ret = sdmmc2.sdmmc_write_single_block((uint32_t) media_ptr->fx_media_driver_buffer, partition_start);
if (ret == HAL_OK) media_ptr->fx_media_driver_status = FX_SUCCESS;
else
media_ptr->fx_media_driver_status = FX_IO_ERROR;
break;
}
default:
media_ptr->fx_media_driver_status = FX_NOT_IMPLEMENTED;
break;
}
}
}
//void fx_stm32_sd_driver(FX_MEDIA *media_ptr) {
// UINT status;
// UINT unaligned_buffer;
// ULONG partition_start;
// ULONG partition_size;
//
//#if (FX_STM32_SD_INIT == 0)
// /* the SD was initialized by the application */
// is_initialized = 1;
//#endif
// /* before performing any operation, check the status of the SD IP */
// if (is_initialized == 1) {
// if (check_sd_status(FX_STM32_SD_INSTANCE) != 0) {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// return;
// }
// }
//
//#if (FX_STM32_SD_DMA_API == 1)
// /* the SD DMA requires a 4-byte aligned buffers */
// unaligned_buffer = (UINT)(media_ptr->fx_media_driver_buffer) & 0x3;
//#else
// /* if the DMA is not used there isn't any constraint on buffer alignment */
// unaligned_buffer = 0;
//#endif
// /* Process the driver request specified in the media control block. */
// switch (media_ptr->fx_media_driver_request) {
// case FX_DRIVER_INIT: {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
//
// FX_STM32_SD_PRE_INIT(media_ptr);
//
//#if (FX_STM32_SD_INIT == 1)
// /* Initialize the SD instance */
// if (is_initialized == 0)
// {
// status = fx_stm32_sd_init(FX_STM32_SD_INSTANCE);
//
// if (status == 0)
// {
// is_initialized = 1;
// }
// else
// {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// }
// }
//#endif
// /* call post init_old user macro */
// FX_STM32_SD_POST_INIT(media_ptr);
// break;
// }
//
// case FX_DRIVER_UNINIT: {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
//
//#if (FX_STM32_SD_INIT == 1)
// status = fx_stm32_sd_deinit(FX_STM32_SD_INSTANCE);
//
// if (status != 0)
// {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// }
// else
// {
// is_initialized = 0;
// }
//#endif
// /* call post deinit processing */
// FX_STM32_SD_POST_DEINIT(media_ptr);
//
// break;
// }
//
// case FX_DRIVER_READ: {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
//
// if (sd_read_data(media_ptr, media_ptr->fx_media_driver_logical_sector + media_ptr->fx_media_hidden_sectors,
// media_ptr->fx_media_driver_sectors, unaligned_buffer) == FX_SUCCESS) {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// }
//
// break;
// }
//
// case FX_DRIVER_WRITE: {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
//
// if (sd_write_data(media_ptr, media_ptr->fx_media_driver_logical_sector + media_ptr->fx_media_hidden_sectors,
// media_ptr->fx_media_driver_sectors, unaligned_buffer) == FX_SUCCESS) {
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// }
//
// break;
// }
//
// case FX_DRIVER_FLUSH: {
// /* Return driver success. */
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// break;
// }
//
// case FX_DRIVER_ABORT: {
// /* Return driver success. */
// media_ptr->fx_media_driver_status = FX_SUCCESS;
//
// FX_STM32_SD_POST_ABORT(media_ptr);
// break;
// }
//
// case FX_DRIVER_BOOT_READ: {
// /* the boot sector is the sector zero */
// status = sd_read_data(media_ptr, 0, media_ptr->fx_media_driver_sectors, unaligned_buffer);
//
// if (status != FX_SUCCESS) {
// media_ptr->fx_media_driver_status = status;
// break;
// }
//
// /* Check if the sector 0 is the actual boot sector, otherwise calculate the offset into it.
// Please note that this should belong to higher level of MW to do this check and it is here
// as a temporary work solution */
//
// partition_start = 0;
//
// status = _fx_partition_offset_calculate(media_ptr->fx_media_driver_buffer, 0,
// &partition_start, &partition_size);
//
// /* Check partition read error. */
// if (status) {
// /* Unsuccessful driver request. */
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// break;
// }
//
// /* Now determine if there is a partition... */
// if (partition_start) {
//
// if (check_sd_status(FX_STM32_SD_INSTANCE) != 0) {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// break;
// }
//
// /* Yes, now lets read the actual boot record. */
// status = sd_read_data(media_ptr, partition_start, media_ptr->fx_media_driver_sectors, unaligned_buffer);
//
// if (status != FX_SUCCESS) {
// media_ptr->fx_media_driver_status = status;
// break;
// }
// }
//
// /* Successful driver request. */
// media_ptr->fx_media_driver_status = FX_SUCCESS;
// break;
// }
//
// case FX_DRIVER_BOOT_WRITE: {
// status = sd_write_data(media_ptr, 0, media_ptr->fx_media_driver_sectors, unaligned_buffer);
//
// media_ptr->fx_media_driver_status = status;
//
// break;
// }
//
// default: {
// media_ptr->fx_media_driver_status = FX_IO_ERROR;
// break;
// }
// }
//}
/**
* @brief Read data from uSD into destination buffer
* @param FX_MEDIA *media_ptr a pointer the main FileX structure
* @param ULONG start_sector first sector to start reading from
* @param UINT num_sectors number of sectors to be read
* @param UINT use_scratch_buffer to enable scratch buffer usage or not.
* @retval FX_SUCCESS on success FX_BUFFER_ERROR / FX_ACCESS_ERROR / FX_IO_ERROR otherwise
*/
//static UINT sd_read_data(FX_MEDIA *media_ptr, ULONG start_sector, UINT num_sectors, UINT use_scratch_buffer)
/**
* @brief write data buffer into the uSD
* @param FX_MEDIA *media_ptr a pointer the main FileX structure
* @param ULONG start_sector first sector to start writing from
* @param UINT num_sectors number of sectors to be written
* @param UINT use_scratch_buffer to enable scratch buffer usage or not.
* @retval FX_SUCCESS on success FX_BUFFER_ERROR / FX_ACCESS_ERROR / FX_IO_ERROR otherwise
*/
// static UINT sd_write_data(FX_MEDIA *media_ptr, ULONG start_sector, UINT num_sectors, UINT use_scratch_buffer);

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stm32u5/examples/cam_board/usb/main.cpp Executable file
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#include "bsp.h"
#include "ov5640.h"
#include "prepherials.h"
#include <string>
#include "dcmi.hpp"
#include "custom_prephrals.h"
#include "ov5640_configs.h"
uint32_t picture[PICTURE_BUFFER_SIZE];
#define OV5640_I2C_ADDR (0x78)
#include "fx_api.h"
extern "C" {
VOID fx_ggeta_driver(FX_MEDIA *media_ptr);
}
FX_MEDIA sdio_disk;
FX_FILE file;
UINT status;
UINT media_memory[1024];
int main() {
cam_board_init();
// set PA11 and PA12 to alternate function (10 for USB)
// enable clock for GPIOA
// enable VDDIO2
// enable VDDUSB
PWR->SVMCR |= PWR_SVMCR_USV;
// PWR->SVMCR |= PWR_SVMCR_IO2SV;
// enable PWREN
// RCC->AHB3ENR |= RCC_AHB3ENR_PWREN;
// // enable VDDA
// PWR->SVMCR |= PWR_SVMCR_ASV;
RCC->AHB2ENR1 |= RCC_AHB2ENR1_GPIOAEN;
// enable VDDIO2
// PWR->SVMCR |= PWR_SVMCR_IO2SV;
////////////////////////////
GPIOA->MODER &= ~(GPIO_MODER_MODE11 | GPIO_MODER_MODE12);
GPIOA->MODER |= (0x2 << GPIO_MODER_MODE11_Pos) | (0x2 << GPIO_MODER_MODE12_Pos);
GPIOA->AFR[1] &= ~(GPIO_AFRH_AFSEL11 | GPIO_AFRH_AFSEL12);
GPIOA->AFR[1] |= (0xA << GPIO_AFRH_AFSEL11_Pos) | (0xA << GPIO_AFRH_AFSEL12_Pos);
// output speed to very high
// GPIOA->OSPEEDR |= (0x3 << GPIO_OSPEEDR_OSPEED11_Pos) | (0x3 << GPIO_OSPEEDR_OSPEED12_Pos);
// set PA11 and PA12 to pull-push
// GPIOA->OTYPER &= ~(GPIO_OTYPER_OT11 | GPIO_OTYPER_OT12);
// enable usb clock
RCC->AHB2ENR1 |= RCC_AHB2ENR1_OTGEN;
//////////////////////
// translate from cube code
// USB_devInit
USB_OTG_DeviceTypeDef *USB_DE = (USB_OTG_DeviceTypeDef *) (0x42040800);
for (int i = 0; i < 15; i++)
USB_OTG_FS->DIEPTXF[i] = 0;
USB_DE->DCTL |= USB_OTG_DCTL_SDIS;
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
USB_OTG_FS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
// // restart the PHY clock
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USB_OTG_FS_BASE + USB_OTG_PCGCCTL_BASE)
// USB_OTG_PCGCCTL_BASE = 0;
USBx_PCGCCTL = 0U;
// set to full speed mode
// USB_DE->DCFG |= USB_OTG_DCFG_DSPD; // 1 or 3?
// flush all tx fifo
USB_OTG_FS->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH | (0x10 << USB_OTG_GRSTCTL_TXFNUM_Pos);
// flush rx fifo
USB_OTG_FS->GRSTCTL |= USB_OTG_GRSTCTL_RXFFLSH;
// clear all pending device interrupts
USB_DE->DIEPMSK = 0;
USB_DE->DOEPMSK = 0;
USB_DE->DAINTMSK = 0;
////// skip endpoint config
#define USBx USB_OTG_FS
#define USBx_DEVICE USB_DE
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
// USB_OTG_FS->GRXFSIZ = 0x100;
// USB_OTG_FS->DIEPTXF[0] = (0x40 << USB_OTG_DIEPTXF_INEPTXFD_Pos) | 0x100;
// USB_OTG_FS->DIEPTXF[1] = (0x80 << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (0x100 + 0x40);
// USB_OTG_FS->DIEPTXF[2] = (0xC0 << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (0x100 + 0x40 + 0x80);
// USB_OTG_FS->DIEPTXF[3] = (0x100 << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (0x100 + 0x40 + 0x80 + 0xC0);
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
/////////////////////////
//
//// USB_OTG_FS->
//// USB_OTG_PCGCCTL_BASE
//
//// set DIEPTXF to 0
// USB_OTG_FS->GCCFG |=
// USB_OTG_GCCFG_PWRDWN | USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL | USB_OTG_GCCFG_VBDEN;
// // flush FIFO
// USB_OTG_FS->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH | USB_OTG_GRSTCTL_RXFFLSH;
//
// // clear all pending interrupts
// USB_OTG_FS->GINTSTS = 0xFFFFFFFF;
//
// USB_OTG_FS->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
// // set OTG_FS TIMEout and
// USB_OTG_FS->GAHBCFG |= (0x6 << USB_OTG_GUSBCFG_TRDT_Pos);
// // unmask GINTMSK OTGINT and MMISM
// USB_OTG_FS->GINTMSK |= USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_MMISM;
// // set to device mode
// USB_OTG_FS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
// // read CMOD to check if it is in device mode
// while ((USB_OTG_FS->GINTSTS & USB_OTG_GINTSTS_CMOD) != 0) {}
//
// // initialized Device
// USB_DE->DCFG |= USB_OTG_DCFG_DSPD;
// // device speed
// // non-zero-length status OUT handshake
// USB_DE->DCFG |= USB_OTG_DCFG_NZLSOHSK;
// // periodic frame interval
// USB_DE->DCFG |= (0x6 << USB_OTG_DCFG_PFIVL_Pos);
// // clear all pending interrupts
// USB_OTG_FS->GINTSTS = 0xFFFFFFFF;
// // clear dctl.sdis
// USB_DE->DCTL &= ~USB_OTG_DCTL_SDIS;
while (true) {}
}

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stm32u5/examples/cam_board/usb/ov5640.cpp Executable file
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#include "ov5640_configs.h"
#include "ov5640.h"
#include "prepherials.h"
//#include "tim.h"
//#include "i2c.h"
//#include "dma.h"
//#include "uart.h"
#include "bsp.h"
#include "delay.h"
#include "global_variable.h"
#define OV5640_I2C_ADDR 0x78
__WARN_UNUSED_RESULT hal_status_e ov5640_read_reg(uint16_t reg[2]) {
// while (READ_BIT(i2c1_p->event, I2C_SEND_RECEIVE_COMPLETE) == 0);
uint8_t reg_addr[2];
reg_addr[0] = (reg[0] >> 8) & 0xFF;
reg_addr[1] = reg[0] & 0xFF;
i2c1.send_it_dep(OV5640_I2C_ADDR, reg_addr, 2, 10);
i2c1.read_block_dep(OV5640_I2C_ADDR, 1, 10);
uint8_t tmp_data;
i2c1.i2c_wait_for_transfer_complete(10);
i2c1.recv_queue_dep.pop(&tmp_data);
reg[1] = (uint16_t) tmp_data;
return HAL_OK;
}
__WARN_UNUSED_RESULT hal_status_e ov5640_write_reg(const uint16_t reg[][2], uint16_t len) {
for (int i = 0; i < len; i++) {
uint8_t data[3];
data[0] = (reg[i][0] >> 8) & 0xFF;
data[1] = reg[i][0] & 0xFF;
data[2] = reg[i][1] & 0xFF;
// wait for receive complete
i2c1.send_it_dep(OV5640_I2C_ADDR, data, 3, 10);
}
return HAL_OK;
}
void camera_sleep() {
pf.set_high(0);
}
void camera_wakeup() {
pf.set_low(0);
}
void camera_clock_init() {
pe.init(9, AF, 1); // PE9 ------> TIM1_CH1 for camera clock
// tim_set_gpio_ch1();
// timer_init_default(timer1);
tim1.init_default();
// timer_set_pwm(timer1, CH1, 4, 4);
tim1.set_pwm(CH1, 4, 4);
// timer_enable_output(timer1, CH1);
tim1.enable_output(CH1);
}
void camera_uart_int() {
// IF_ERROR_STUCK(uart_gpio_init(usart1_p, 0));
// IF_ERROR_STUCK(uart_init(usart1_p, 115200, 50, 20));
}
void camera_i2c_init() {
// IF_ERROR_STUCK(i2c_gpio_init(i2c1_p, 0));
// IF_ERROR_STUCK(i2c_init(i2c1_p, 20, 20));
}
void camera_sleep_init() {
// IF_ERROR_STUCK(gpio_init(gpiof_p, GGPIO_PIN_0, OUTPUT, PULL_PUSH, VERY_HIGH_SPEED, 0));
}
void camera_read_id() {
uint8_t data[3];
data[0] = 0x30, data[1] = 0x0A;
i2c1.send_it_dep(OV5640_I2C_ADDR, data, 2, 10);
i2c1.read_block_dep(OV5640_I2C_ADDR, 1, 10);
data[0] = 0x30, data[1] = 0x0B;
i2c1.send_it_dep(OV5640_I2C_ADDR, data, 2, 10);
i2c1.read_block_dep(OV5640_I2C_ADDR, 1, 10);
// I should have read 0x56 and 0x40 (I check this use debug mode)
}
void camera_init() {
camera_clock_init();
camera_uart_int();
camera_i2c_init();
camera_sleep_init();
IF_ERROR_STUCK(ov5640_write_reg(OV5640_Common, sizeof(OV5640_Common))); // init_old camera
IF_ERROR_STUCK(ov5640_write_reg(OV5640_PF_JPEG, sizeof(OV5640_PF_JPEG)));
uint16_t tmp_addr[1][2] = {{OV5640_TIMING_TC_REG21, 0xA8}};
// setup for jpeg mode
IF_ERROR_STUCK(ov5640_read_reg(tmp_addr[0]));
tmp_addr[0][1] |= (uint8_t) (1 << 5);
IF_ERROR_STUCK(ov5640_write_reg(tmp_addr, 1));
tmp_addr[0][0] = OV5640_SYSREM_RESET02;
IF_ERROR_STUCK(ov5640_read_reg(tmp_addr[0]));
tmp_addr[0][1] &= ~((1 << 2) | (1 << 3) | (1 << 4));
IF_ERROR_STUCK(ov5640_write_reg(tmp_addr, 1));
tmp_addr[0][0] = OV5640_CLOCK_ENABLE02;
IF_ERROR_STUCK(ov5640_read_reg(tmp_addr[0]));
tmp_addr[0][1] |= (1 << 3) | (1 << 5);
IF_ERROR_STUCK(ov5640_write_reg(tmp_addr, 1));
// end setup for jpeg mode
// dma_s *dcmi_dma = dma1_p;
dcmi_gpio_setup();
dma10.init(86,
DMA_DATA_WIDTH_32_BITS, DMA_DATA_WIDTH_32_BITS,
DMA_ADDR_FIX, DMA_ADDR_INC,
DMA_TYPE_PREPHERIAL, DMA_TYPE_MEMORY, PICTURE_BUFFER_SIZE * 4);
dcmi.init_old();
}

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stm32u5/examples/cam_board/usb/ov5640.h Executable file
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#include <stdint.h>
#ifndef STM32U5_OV5640_H
#define STM32U5_OV5640_H
#define OV5640_SYSREM_RESET00 0x3000U
#define OV5640_SYSREM_RESET01 0x3001U
#define OV5640_SYSREM_RESET02 0x3002U
#define OV5640_SYSREM_RESET03 0x3003U
#define OV5640_CLOCK_ENABLE00 0x3004U
#define OV5640_CLOCK_ENABLE01 0x3005U
#define OV5640_CLOCK_ENABLE02 0x3006U
#define OV5640_CLOCK_ENABLE03 0x3007U
#define OV5640_SYSTEM_CTROL0 0x3008U
#define OV5640_CHIP_ID_HIGH_BYTE 0x300AU
#define OV5640_CHIP_ID_LOW_BYTE 0x300BU
#define OV5640_MIPI_CONTROL00 0x300EU
#define OV5640_PAD_OUTPUT_ENABLE00 0x3016U
#define OV5640_PAD_OUTPUT_ENABLE01 0x3017U
#define OV5640_PAD_OUTPUT_ENABLE02 0x3018U
#define OV5640_PAD_OUTPUT_VALUE00 0x3019U
#define OV5640_PAD_OUTPUT_VALUE01 0x301AU
#define OV5640_PAD_OUTPUT_VALUE02 0x301BU
#define OV5640_PAD_SELECT00 0x301CU
#define OV5640_PAD_SELECT01 0x301DU
#define OV5640_PAD_SELECT02 0x301EU
#define OV5640_CHIP_REVISION 0x302AU
#define OV5640_PAD_CONTROL00 0x301CU
#define OV5640_SC_PWC 0x3031U
#define OV5640_SC_PLL_CONTRL0 0x3034U
#define OV5640_SC_PLL_CONTRL1 0x3035U
#define OV5640_SC_PLL_CONTRL2 0x3036U
#define OV5640_SC_PLL_CONTRL3 0x3037U
#define OV5640_SC_PLL_CONTRL4 0x3038U
#define OV5640_SC_PLL_CONTRL5 0x3039U
#define OV5640_SC_PLLS_CTRL0 0x303AU
#define OV5640_SC_PLLS_CTRL1 0x303BU
#define OV5640_SC_PLLS_CTRL2 0x303CU
#define OV5640_SC_PLLS_CTRL3 0x303DU
#define OV5640_IO_PAD_VALUE00 0x3050U
#define OV5640_IO_PAD_VALUE01 0x3051U
#define OV5640_IO_PAD_VALUE02 0x3052U
/* SCCB control [0x3100 ~ 0x3108] */
#define OV5640_SCCB_ID 0x3100U
#define OV5640_SCCB_SYSTEM_CTRL0 0x3102U
#define OV5640_SCCB_SYSTEM_CTRL1 0x3103U
#define OV5640_SYSTEM_ROOT_DIVIDER 0x3108U
/* SRB control [0x3200 ~ 0x3213] */
#define OV5640_GROUP_ADDR0 0x3200U
#define OV5640_GROUP_ADDR1 0x3201U
#define OV5640_GROUP_ADDR2 0x3202U
#define OV5640_GROUP_ADDR3 0x3203U
#define OV5640_SRM_GROUP_ACCESS 0x3212U
#define OV5640_SRM_GROUP_STATUS 0x3213U
/* AWB gain control [0x3400 ~ 0x3406] */
#define OV5640_AWB_R_GAIN_MSB 0x3400U
#define OV5640_AWB_R_GAIN_LSB 0x3401U
#define OV5640_AWB_G_GAIN_MSB 0x3402U
#define OV5640_AWB_G_GAIN_LSB 0x3403U
#define OV5640_AWB_B_GAIN_MSB 0x3404U
#define OV5640_AWB_B_GAIN_LSB 0x3405U
#define OV5640_AWB_MANUAL_CONTROL 0x3406U
/* AEC/AGC control [0x3500 ~ 0x350D] */
#define OV5640_AEC_PK_EXPOSURE_19_16 0x3500U
#define OV5640_AEC_PK_EXPOSURE_HIGH 0x3501U
#define OV5640_AEC_PK_EXPOSURE_LOW 0x3502U
#define OV5640_AEC_PK_MANUAL 0x3503U
#define OV5640_AEC_PK_REAL_GAIN_9_8 0x350AU
#define OV5640_AEC_PK_REAL_GAIN_LOW 0x350BU
#define OV5640_AEC_PK_VTS_HIGH 0x350CU
#define OV5640_AEC_PK_VTS_LOW 0x350DU
/* VCM control [0x3600 ~ 0x3606] */
#define OV5640_VCM_CONTROL_0 0x3602U
#define OV5640_VCM_CONTROL_1 0x3603U
#define OV5640_VCM_CONTROL_2 0x3604U
#define OV5640_VCM_CONTROL_3 0x3605U
#define OV5640_VCM_CONTROL_4 0x3606U
/* timing control [0x3800 ~ 0x3821] */
#define OV5640_TIMING_HS_HIGH 0x3800U
#define OV5640_TIMING_HS_LOW 0x3801U
#define OV5640_TIMING_VS_HIGH 0x3802U
#define OV5640_TIMING_VS_LOW 0x3803U
#define OV5640_TIMING_HW_HIGH 0x3804U
#define OV5640_TIMING_HW_LOW 0x3805U
#define OV5640_TIMING_VH_HIGH 0x3806U
#define OV5640_TIMING_VH_LOW 0x3807U
#define OV5640_TIMING_DVPHO_HIGH 0x3808U
#define OV5640_TIMING_DVPHO_LOW 0x3809U
#define OV5640_TIMING_DVPVO_HIGH 0x380AU
#define OV5640_TIMING_DVPVO_LOW 0x380BU
#define OV5640_TIMING_HTS_HIGH 0x380CU
#define OV5640_TIMING_HTS_LOW 0x380DU
#define OV5640_TIMING_VTS_HIGH 0x380EU
#define OV5640_TIMING_VTS_LOW 0x380FU
#define OV5640_TIMING_HOFFSET_HIGH 0x3810U
#define OV5640_TIMING_HOFFSET_LOW 0x3811U
#define OV5640_TIMING_VOFFSET_HIGH 0x3812U
#define OV5640_TIMING_VOFFSET_LOW 0x3813U
#define OV5640_TIMING_X_INC 0x3814U
#define OV5640_TIMING_Y_INC 0x3815U
#define OV5640_HSYNC_START_HIGH 0x3816U
#define OV5640_HSYNC_START_LOW 0x3817U
#define OV5640_HSYNC_WIDTH_HIGH 0x3818U
#define OV5640_HSYNC_WIDTH_LOW 0x3819U
#define OV5640_TIMING_TC_REG20 0x3820U
#define OV5640_TIMING_TC_REG21 0x3821U
/* AEC/AGC power down domain control [0x3A00 ~ 0x3A25] */
#define OV5640_AEC_CTRL00 0x3A00U
#define OV5640_AEC_CTRL01 0x3A01U
#define OV5640_AEC_CTRL02 0x3A02U
#define OV5640_AEC_CTRL03 0x3A03U
#define OV5640_AEC_CTRL04 0x3A04U
#define OV5640_AEC_CTRL05 0x3A05U
#define OV5640_AEC_CTRL06 0x3A06U
#define OV5640_AEC_CTRL07 0x3A07U
#define OV5640_AEC_B50_STEP_HIGH 0x3A08U
#define OV5640_AEC_B50_STEP_LOW 0x3A09U
#define OV5640_AEC_B60_STEP_HIGH 0x3A0AU
#define OV5640_AEC_B60_STEP_LOW 0x3A0BU
#define OV5640_AEC_AEC_CTRL0C 0x3A0CU
#define OV5640_AEC_CTRL0D 0x3A0DU
#define OV5640_AEC_CTRL0E 0x3A0EU
#define OV5640_AEC_CTRL0F 0x3A0FU
#define OV5640_AEC_CTRL10 0x3A10U
#define OV5640_AEC_CTRL11 0x3A11U
#define OV5640_AEC_CTRL13 0x3A13U
#define OV5640_AEC_MAX_EXPO_HIGH 0x3A14U
#define OV5640_AEC_MAX_EXPO_LOW 0x3A15U
#define OV5640_AEC_CTRL17 0x3A17U
#define OV5640_AEC_GAIN_CEILING_HIGH 0x3A18U
#define OV5640_AEC_GAIN_CEILING_LOW 0x3A19U
#define OV5640_AEC_DIFF_MIN 0x3A1AU
#define OV5640_AEC_CTRL1B 0x3A1BU
#define OV5640_LED_ADD_ROW_HIGH 0x3A1CU
#define OV5640_LED_ADD_ROW_LOW 0x3A1DU
#define OV5640_AEC_CTRL1E 0x3A1EU
#define OV5640_AEC_CTRL1F 0x3A1FU
#define OV5640_AEC_CTRL20 0x3A20U
#define OV5640_AEC_CTRL21 0x3A21U
#define OV5640_AEC_CTRL25 0x3A25U
/* strobe control [0x3B00 ~ 0x3B0C] */
#define OV5640_STROBE_CTRL 0x3B00U
#define OV5640_FREX_EXPOSURE02 0x3B01U
#define OV5640_FREX_SHUTTER_DLY01 0x3B02U
#define OV5640_FREX_SHUTTER_DLY00 0x3B03U
#define OV5640_FREX_EXPOSURE01 0x3B04U
#define OV5640_FREX_EXPOSURE00 0x3B05U
#define OV5640_FREX_CTRL07 0x3B06U
#define OV5640_FREX_MODE 0x3B07U
#define OV5640_FREX_RQST 0x3B08U
#define OV5640_FREX_HREF_DLY 0x3B09U
#define OV5640_FREX_RST_LENGTH 0x3B0AU
#define OV5640_STROBE_WIDTH_HIGH 0x3B0BU
#define OV5640_STROBE_WIDTH_LOW 0x3B0CU
/* 50/60Hz detector control [0x3C00 ~ 0x3C1E] */
#define OV5640_5060HZ_CTRL00 0x3C00U
#define OV5640_5060HZ_CTRL01 0x3C01U
#define OV5640_5060HZ_CTRL02 0x3C02U
#define OV5640_5060HZ_CTRL03 0x3C03U
#define OV5640_5060HZ_CTRL04 0x3C04U
#define OV5640_5060HZ_CTRL05 0x3C05U
#define OV5640_LIGHTMETER1_TH_HIGH 0x3C06U
#define OV5640_LIGHTMETER1_TH_LOW 0x3C07U
#define OV5640_LIGHTMETER2_TH_HIGH 0x3C08U
#define OV5640_LIGHTMETER2_TH_LOW 0x3C09U
#define OV5640_SAMPLE_NUMBER_HIGH 0x3C0AU
#define OV5640_SAMPLE_NUMBER_LOW 0x3C0BU
#define OV5640_SIGMA_DELTA_CTRL0C 0x3C0CU
#define OV5640_SUM50_BYTE4 0x3C0DU
#define OV5640_SUM50_BYTE3 0x3C0EU
#define OV5640_SUM50_BYTE2 0x3C0FU
#define OV5640_SUM50_BYTE1 0x3C10U
#define OV5640_SUM60_BYTE4 0x3C11U
#define OV5640_SUM60_BYTE3 0x3C12U
#define OV5640_SUM60_BYTE2 0x3C13U
#define OV5640_SUM60_BYTE1 0x3C14U
#define OV5640_SUM5060_HIGH 0x3C15U
#define OV5640_SUM5060_LOW 0x3C16U
#define OV5640_BLOCK_CNTR_HIGH 0x3C17U
#define OV5640_BLOCK_CNTR_LOW 0x3C18U
#define OV5640_B6_HIGH 0x3C19U
#define OV5640_B6_LOW 0x3C1AU
#define OV5640_LIGHTMETER_OUTPUT_BYTE3 0x3C1BU
#define OV5640_LIGHTMETER_OUTPUT_BYTE2 0x3C1CU
#define OV5640_LIGHTMETER_OUTPUT_BYTE1 0x3C1DU
#define OV5640_SUM_THRESHOLD 0x3C1EU
/* OTP control [0x3D00 ~ 0x3D21] */
/* MC control [0x3F00 ~ 0x3F0D] */
/* BLC control [0x4000 ~ 0x4033] */
#define OV5640_BLC_CTRL00 0x4000U
#define OV5640_BLC_CTRL01 0x4001U
#define OV5640_BLC_CTRL02 0x4002U
#define OV5640_BLC_CTRL03 0x4003U
#define OV5640_BLC_CTRL04 0x4004U
#define OV5640_BLC_CTRL05 0x4005U
/* frame control [0x4201 ~ 0x4202] */
#define OV5640_FRAME_CTRL01 0x4201U
#define OV5640_FRAME_CTRL02 0x4202U
/* format control [0x4300 ~ 0x430D] */
#define OV5640_FORMAT_CTRL00 0x4300U
#define OV5640_FORMAT_CTRL01 0x4301U
#define OV5640_YMAX_VAL_HIGH 0x4302U
#define OV5640_YMAX_VAL_LOW 0x4303U
#define OV5640_YMIN_VAL_HIGH 0x4304U
#define OV5640_YMIN_VAL_LOW 0x4305U
#define OV5640_UMAX_VAL_HIGH 0x4306U
#define OV5640_UMAX_VAL_LOW 0x4307U
#define OV5640_UMIN_VAL_HIGH 0x4308U
#define OV5640_UMIN_VAL_LOW 0x4309U
#define OV5640_VMAX_VAL_HIGH 0x430AU
#define OV5640_VMAX_VAL_LOW 0x430BU
#define OV5640_VMIN_VAL_HIGH 0x430CU
#define OV5640_VMIN_VAL_LOW 0x430DU
/* JPEG control [0x4400 ~ 0x4431] */
#define OV5640_JPEG_CTRL00 0x4400U
#define OV5640_JPEG_CTRL01 0x4401U
#define OV5640_JPEG_CTRL02 0x4402U
#define OV5640_JPEG_CTRL03 0x4403U
#define OV5640_JPEG_CTRL04 0x4404U
#define OV5640_JPEG_CTRL05 0x4405U
#define OV5640_JPEG_CTRL06 0x4406U
#define OV5640_JPEG_CTRL07 0x4407U
#define OV5640_JPEG_ISI_CTRL1 0x4408U
#define OV5640_JPEG_CTRL09 0x4409U
#define OV5640_JPEG_CTRL0A 0x440AU
#define OV5640_JPEG_CTRL0B 0x440BU
#define OV5640_JPEG_CTRL0C 0x440CU
#define OV5640_JPEG_QT_DATA 0x4410U
#define OV5640_JPEG_QT_ADDR 0x4411U
#define OV5640_JPEG_ISI_DATA 0x4412U
#define OV5640_JPEG_ISI_CTRL2 0x4413U
#define OV5640_JPEG_LENGTH_BYTE3 0x4414U
#define OV5640_JPEG_LENGTH_BYTE2 0x4415U
#define OV5640_JPEG_LENGTH_BYTE1 0x4416U
#define OV5640_JFIFO_OVERFLOW 0x4417U
/* VFIFO control [0x4600 ~ 0x460D] */
#define OV5640_VFIFO_CTRL00 0x4600U
#define OV5640_VFIFO_HSIZE_HIGH 0x4602U
#define OV5640_VFIFO_HSIZE_LOW 0x4603U
#define OV5640_VFIFO_VSIZE_HIGH 0x4604U
#define OV5640_VFIFO_VSIZE_LOW 0x4605U
#define OV5640_VFIFO_CTRL0C 0x460CU
#define OV5640_VFIFO_CTRL0D 0x460DU
/* DVP control [0x4709 ~ 0x4745] */
#define OV5640_DVP_VSYNC_WIDTH0 0x4709U
#define OV5640_DVP_VSYNC_WIDTH1 0x470AU
#define OV5640_DVP_VSYNC_WIDTH2 0x470BU
#define OV5640_PAD_LEFT_CTRL 0x4711U
#define OV5640_PAD_RIGHT_CTRL 0x4712U
#define OV5640_JPG_MODE_SELECT 0x4713U
#define OV5640_656_DUMMY_LINE 0x4715U
#define OV5640_CCIR656_CTRL 0x4719U
#define OV5640_HSYNC_CTRL00 0x471BU
#define OV5640_DVP_VSYN_CTRL 0x471DU
#define OV5640_DVP_HREF_CTRL 0x471FU
#define OV5640_VSTART_OFFSET 0x4721U
#define OV5640_VEND_OFFSET 0x4722U
#define OV5640_DVP_CTRL23 0x4723U
#define OV5640_CCIR656_CTRL00 0x4730U
#define OV5640_CCIR656_CTRL01 0x4731U
#define OV5640_CCIR656_FS 0x4732U
#define OV5640_CCIR656_FE 0x4733U
#define OV5640_CCIR656_LS 0x4734U
#define OV5640_CCIR656_LE 0x4735U
#define OV5640_CCIR656_CTRL06 0x4736U
#define OV5640_CCIR656_CTRL07 0x4737U
#define OV5640_CCIR656_CTRL08 0x4738U
#define OV5640_POLARITY_CTRL 0x4740U
#define OV5640_TEST_PATTERN 0x4741U
#define OV5640_DATA_ORDER 0x4745U
/* MIPI control [0x4800 ~ 0x4837] */
#define OV5640_MIPI_CTRL00 0x4800U
#define OV5640_MIPI_CTRL01 0x4801U
#define OV5640_MIPI_CTRL05 0x4805U
#define OV5640_MIPI_DATA_ORDER 0x480AU
#define OV5640_MIN_HS_ZERO_HIGH 0x4818U
#define OV5640_MIN_HS_ZERO_LOW 0x4819U
#define OV5640_MIN_MIPI_HS_TRAIL_HIGH 0x481AU
#define OV5640_MIN_MIPI_HS_TRAIL_LOW 0x481BU
#define OV5640_MIN_MIPI_CLK_ZERO_HIGH 0x481CU
#define OV5640_MIN_MIPI_CLK_ZERO_LOW 0x481DU
#define OV5640_MIN_MIPI_CLK_PREPARE_HIGH 0x481EU
#define OV5640_MIN_MIPI_CLK_PREPARE_LOW 0x481FU
#define OV5640_MIN_CLK_POST_HIGH 0x4820U
#define OV5640_MIN_CLK_POST_LOW 0x4821U
#define OV5640_MIN_CLK_TRAIL_HIGH 0x4822U
#define OV5640_MIN_CLK_TRAIL_LOW 0x4823U
#define OV5640_MIN_LPX_PCLK_HIGH 0x4824U
#define OV5640_MIN_LPX_PCLK_LOW 0x4825U
#define OV5640_MIN_HS_PREPARE_HIGH 0x4826U
#define OV5640_MIN_HS_PREPARE_LOW 0x4827U
#define OV5640_MIN_HS_EXIT_HIGH 0x4828U
#define OV5640_MIN_HS_EXIT_LOW 0x4829U
#define OV5640_MIN_HS_ZERO_UI 0x482AU
#define OV5640_MIN_HS_TRAIL_UI 0x482BU
#define OV5640_MIN_CLK_ZERO_UI 0x482CU
#define OV5640_MIN_CLK_PREPARE_UI 0x482DU
#define OV5640_MIN_CLK_POST_UI 0x482EU
#define OV5640_MIN_CLK_TRAIL_UI 0x482FU
#define OV5640_MIN_LPX_PCLK_UI 0x4830U
#define OV5640_MIN_HS_PREPARE_UI 0x4831U
#define OV5640_MIN_HS_EXIT_UI 0x4832U
#define OV5640_PCLK_PERIOD 0x4837U
/* ISP frame control [0x4901 ~ 0x4902] */
#define OV5640_ISP_FRAME_CTRL01 0x4901U
#define OV5640_ISP_FRAME_CTRL02 0x4902U
/* ISP top control [0x5000 ~ 0x5063] */
#define OV5640_ISP_CONTROL00 0x5000U
#define OV5640_ISP_CONTROL01 0x5001U
#define OV5640_ISP_CONTROL03 0x5003U
#define OV5640_ISP_CONTROL05 0x5005U
#define OV5640_ISP_MISC0 0x501DU
#define OV5640_ISP_MISC1 0x501EU
#define OV5640_FORMAT_MUX_CTRL 0x501FU
#define OV5640_DITHER_CTRL0 0x5020U
#define OV5640_DRAW_WINDOW_CTRL00 0x5027U
#define OV5640_DRAW_WINDOW_LEFT_CTRL_HIGH 0x5028U
#define OV5640_DRAW_WINDOW_LEFT_CTRL_LOW 0x5029U
#define OV5640_DRAW_WINDOW_RIGHT_CTRL_HIGH 0x502AU
#define OV5640_DRAW_WINDOW_RIGHT_CTRL_LOW 0x502BU
#define OV5640_DRAW_WINDOW_TOP_CTRL_HIGH 0x502CU
#define OV5640_DRAW_WINDOW_TOP_CTRL_LOW 0x502DU
#define OV5640_DRAW_WINDOW_BOTTOM_CTRL_HIGH 0x502EU
#define OV5640_DRAW_WINDOW_BOTTOM_CTRL_LOW 0x502FU
#define OV5640_DRAW_WINDOW_HBW_CTRL_HIGH 0x5030U /* HBW: Horizontal Boundary Width */
#define OV5640_DRAW_WINDOW_HBW_CTRL_LOW 0x5031U
#define OV5640_DRAW_WINDOW_VBW_CTRL_HIGH 0x5032U /* VBW: Vertical Boundary Width */
#define OV5640_DRAW_WINDOW_VBW_CTRL_LOW 0x5033U
#define OV5640_DRAW_WINDOW_Y_CTRL 0x5034U
#define OV5640_DRAW_WINDOW_U_CTRL 0x5035U
#define OV5640_DRAW_WINDOW_V_CTRL 0x5036U
#define OV5640_PRE_ISP_TEST_SETTING1 0x503DU
#define OV5640_ISP_SENSOR_BIAS_I 0x5061U
#define OV5640_ISP_SENSOR_GAIN1_I 0x5062U
#define OV5640_ISP_SENSOR_GAIN2_I 0x5063U
/* AWB control [0x5180 ~ 0x51D0] */
#define OV5640_AWB_CTRL00 0x5180U
#define OV5640_AWB_CTRL01 0x5181U
#define OV5640_AWB_CTRL02 0x5182U
#define OV5640_AWB_CTRL03 0x5183U
#define OV5640_AWB_CTRL04 0x5184U
#define OV5640_AWB_CTRL05 0x5185U
#define OV5640_AWB_CTRL06 0x5186U /* Advanced AWB control registers: 0x5186 ~ 0x5190 */
#define OV5640_AWB_CTRL07 0x5187U
#define OV5640_AWB_CTRL08 0x5188U
#define OV5640_AWB_CTRL09 0x5189U
#define OV5640_AWB_CTRL10 0x518AU
#define OV5640_AWB_CTRL11 0x518BU
#define OV5640_AWB_CTRL12 0x518CU
#define OV5640_AWB_CTRL13 0x518DU
#define OV5640_AWB_CTRL14 0x518EU
#define OV5640_AWB_CTRL15 0x518FU
#define OV5640_AWB_CTRL16 0x5190U
#define OV5640_AWB_CTRL17 0x5191U
#define OV5640_AWB_CTRL18 0x5192U
#define OV5640_AWB_CTRL19 0x5193U
#define OV5640_AWB_CTRL20 0x5194U
#define OV5640_AWB_CTRL21 0x5195U
#define OV5640_AWB_CTRL22 0x5196U
#define OV5640_AWB_CTRL23 0x5197U
#define OV5640_AWB_CTRL24 0x5198U
#define OV5640_AWB_CTRL25 0x5199U
#define OV5640_AWB_CTRL26 0x519AU
#define OV5640_AWB_CTRL27 0x519BU
#define OV5640_AWB_CTRL28 0x519CU
#define OV5640_AWB_CTRL29 0x519DU
#define OV5640_AWB_CTRL30 0x519EU
#define OV5640_AWB_CURRENT_R_GAIN_HIGH 0x519FU
#define OV5640_AWB_CURRENT_R_GAIN_LOW 0x51A0U
#define OV5640_AWB_CURRENT_G_GAIN_HIGH 0x51A1U
#define OV5640_AWB_CURRENT_G_GAIN_LOW 0x51A2U
#define OV5640_AWB_CURRENT_B_GAIN_HIGH 0x51A3U
#define OV5640_AWB_CURRENT_B_GAIN_LOW 0x51A4U
#define OV5640_AWB_AVERAGE_R 0x51A5U
#define OV5640_AWB_AVERAGE_G 0x51A6U
#define OV5640_AWB_AVERAGE_B 0x51A7U
#define OV5640_AWB_CTRL74 0x5180U
/* CIP control [0x5300 ~ 0x530F] */
#define OV5640_CIP_SHARPENMT_TH1 0x5300U
#define OV5640_CIP_SHARPENMT_TH2 0x5301U
#define OV5640_CIP_SHARPENMT_OFFSET1 0x5302U
#define OV5640_CIP_SHARPENMT_OFFSET2 0x5303U
#define OV5640_CIP_DNS_TH1 0x5304U
#define OV5640_CIP_DNS_TH2 0x5305U
#define OV5640_CIP_DNS_OFFSET1 0x5306U
#define OV5640_CIP_DNS_OFFSET2 0x5307U
#define OV5640_CIP_CTRL 0x5308U
#define OV5640_CIP_SHARPENTH_TH1 0x5309U
#define OV5640_CIP_SHARPENTH_TH2 0x530AU
#define OV5640_CIP_SHARPENTH_OFFSET1 0x530BU
#define OV5640_CIP_SHARPENTH_OFFSET2 0x530CU
#define OV5640_CIP_EDGE_MT_AUTO 0x530DU
#define OV5640_CIP_DNS_TH_AUTO 0x530EU
#define OV5640_CIP_SHARPEN_TH_AUTO 0x530FU
/* CMX control [0x5380 ~ 0x538B] */
#define OV5640_CMX_CTRL 0x5380U
#define OV5640_CMX1 0x5381U
#define OV5640_CMX2 0x5382U
#define OV5640_CMX3 0x5383U
#define OV5640_CMX4 0x5384U
#define OV5640_CMX5 0x5385U
#define OV5640_CMX6 0x5386U
#define OV5640_CMX7 0x5387U
#define OV5640_CMX8 0x5388U
#define OV5640_CMX9 0x5389U
#define OV5640_CMXSIGN_HIGH 0x538AU
#define OV5640_CMXSIGN_LOW 0x538BU
/* gamma control [0x5480 ~ 0x5490] */
#define OV5640_GAMMA_CTRL00 0x5480U
#define OV5640_GAMMA_YST00 0x5481U
#define OV5640_GAMMA_YST01 0x5482U
#define OV5640_GAMMA_YST02 0x5483U
#define OV5640_GAMMA_YST03 0x5484U
#define OV5640_GAMMA_YST04 0x5485U
#define OV5640_GAMMA_YST05 0x5486U
#define OV5640_GAMMA_YST06 0x5487U
#define OV5640_GAMMA_YST07 0x5488U
#define OV5640_GAMMA_YST08 0x5489U
#define OV5640_GAMMA_YST09 0x548AU
#define OV5640_GAMMA_YST0A 0x548BU
#define OV5640_GAMMA_YST0B 0x548CU
#define OV5640_GAMMA_YST0C 0x548DU
#define OV5640_GAMMA_YST0D 0x548EU
#define OV5640_GAMMA_YST0E 0x548FU
#define OV5640_GAMMA_YST0F 0x5490U
/* SDE control [0x5580 ~ 0x558C] */
#define OV5640_SDE_CTRL0 0x5580U
#define OV5640_SDE_CTRL1 0x5581U
#define OV5640_SDE_CTRL2 0x5582U
#define OV5640_SDE_CTRL3 0x5583U
#define OV5640_SDE_CTRL4 0x5584U
#define OV5640_SDE_CTRL5 0x5585U
#define OV5640_SDE_CTRL6 0x5586U
#define OV5640_SDE_CTRL7 0x5587U
#define OV5640_SDE_CTRL8 0x5588U
#define OV5640_SDE_CTRL9 0x5589U
#define OV5640_SDE_CTRL10 0x558AU
#define OV5640_SDE_CTRL11 0x558BU
#define OV5640_SDE_CTRL12 0x558CU
/* scale control [0x5600 ~ 0x5606] */
#define OV5640_SCALE_CTRL0 0x5600U
#define OV5640_SCALE_CTRL1 0x5601U
#define OV5640_SCALE_CTRL2 0x5602U
#define OV5640_SCALE_CTRL3 0x5603U
#define OV5640_SCALE_CTRL4 0x5604U
#define OV5640_SCALE_CTRL5 0x5605U
#define OV5640_SCALE_CTRL6 0x5606U
/* AVG control [0x5680 ~ 0x56A2] */
#define OV5640_X_START_HIGH 0x5680U
#define OV5640_X_START_LOW 0x5681U
#define OV5640_Y_START_HIGH 0x5682U
#define OV5640_Y_START_LOW 0x5683U
#define OV5640_X_WINDOW_HIGH 0x5684U
#define OV5640_X_WINDOW_LOW 0x5685U
#define OV5640_Y_WINDOW_HIGH 0x5686U
#define OV5640_Y_WINDOW_LOW 0x5687U
#define OV5640_WEIGHT00 0x5688U
#define OV5640_WEIGHT01 0x5689U
#define OV5640_WEIGHT02 0x568AU
#define OV5640_WEIGHT03 0x568BU
#define OV5640_WEIGHT04 0x568CU
#define OV5640_WEIGHT05 0x568DU
#define OV5640_WEIGHT06 0x568EU
#define OV5640_WEIGHT07 0x568FU
#define OV5640_AVG_CTRL10 0x5690U
#define OV5640_AVG_WIN_00 0x5691U
#define OV5640_AVG_WIN_01 0x5692U
#define OV5640_AVG_WIN_02 0x5693U
#define OV5640_AVG_WIN_03 0x5694U
#define OV5640_AVG_WIN_10 0x5695U
#define OV5640_AVG_WIN_11 0x5696U
#define OV5640_AVG_WIN_12 0x5697U
#define OV5640_AVG_WIN_13 0x5698U
#define OV5640_AVG_WIN_20 0x5699U
#define OV5640_AVG_WIN_21 0x569AU
#define OV5640_AVG_WIN_22 0x569BU
#define OV5640_AVG_WIN_23 0x569CU
#define OV5640_AVG_WIN_30 0x569DU
#define OV5640_AVG_WIN_31 0x569EU
#define OV5640_AVG_WIN_32 0x569FU
#define OV5640_AVG_WIN_33 0x56A0U
#define OV5640_AVG_READOUT 0x56A1U
#define OV5640_AVG_WEIGHT_SUM 0x56A2U
/* LENC control [0x5800 ~ 0x5849] */
#define OV5640_GMTRX00 0x5800U
#define OV5640_GMTRX01 0x5801U
#define OV5640_GMTRX02 0x5802U
#define OV5640_GMTRX03 0x5803U
#define OV5640_GMTRX04 0x5804U
#define OV5640_GMTRX05 0x5805U
#define OV5640_GMTRX10 0x5806U
#define OV5640_GMTRX11 0x5807U
#define OV5640_GMTRX12 0x5808U
#define OV5640_GMTRX13 0x5809U
#define OV5640_GMTRX14 0x580AU
#define OV5640_GMTRX15 0x580BU
#define OV5640_GMTRX20 0x580CU
#define OV5640_GMTRX21 0x580DU
#define OV5640_GMTRX22 0x580EU
#define OV5640_GMTRX23 0x580FU
#define OV5640_GMTRX24 0x5810U
#define OV5640_GMTRX25 0x5811U
#define OV5640_GMTRX30 0x5812U
#define OV5640_GMTRX31 0x5813U
#define OV5640_GMTRX32 0x5814U
#define OV5640_GMTRX33 0x5815U
#define OV5640_GMTRX34 0x5816U
#define OV5640_GMTRX35 0x5817U
#define OV5640_GMTRX40 0x5818U
#define OV5640_GMTRX41 0x5819U
#define OV5640_GMTRX42 0x581AU
#define OV5640_GMTRX43 0x581BU
#define OV5640_GMTRX44 0x581CU
#define OV5640_GMTRX45 0x581DU
#define OV5640_GMTRX50 0x581EU
#define OV5640_GMTRX51 0x581FU
#define OV5640_GMTRX52 0x5820U
#define OV5640_GMTRX53 0x5821U
#define OV5640_GMTRX54 0x5822U
#define OV5640_GMTRX55 0x5823U
#define OV5640_BRMATRX00 0x5824U
#define OV5640_BRMATRX01 0x5825U
#define OV5640_BRMATRX02 0x5826U
#define OV5640_BRMATRX03 0x5827U
#define OV5640_BRMATRX04 0x5828U
#define OV5640_BRMATRX05 0x5829U
#define OV5640_BRMATRX06 0x582AU
#define OV5640_BRMATRX07 0x582BU
#define OV5640_BRMATRX08 0x582CU
#define OV5640_BRMATRX09 0x582DU
#define OV5640_BRMATRX20 0x582EU
#define OV5640_BRMATRX21 0x582FU
#define OV5640_BRMATRX22 0x5830U
#define OV5640_BRMATRX23 0x5831U
#define OV5640_BRMATRX24 0x5832U
#define OV5640_BRMATRX30 0x5833U
#define OV5640_BRMATRX31 0x5834U
#define OV5640_BRMATRX32 0x5835U
#define OV5640_BRMATRX33 0x5836U
#define OV5640_BRMATRX34 0x5837U
#define OV5640_BRMATRX40 0x5838U
#define OV5640_BRMATRX41 0x5839U
#define OV5640_BRMATRX42 0x583AU
#define OV5640_BRMATRX43 0x583BU
#define OV5640_BRMATRX44 0x583CU
#define OV5640_LENC_BR_OFFSET 0x583DU
#define OV5640_MAX_GAIN 0x583EU
#define OV5640_MIN_GAIN 0x583FU
#define OV5640_MIN_Q 0x5840U
#define OV5640_LENC_CTRL59 0x5841U
#define OV5640_BR_HSCALE_HIGH 0x5842U
#define OV5640_BR_HSCALE_LOW 0x5843U
#define OV5640_BR_VSCALE_HIGH 0x5844U
#define OV5640_BR_VSCALE_LOW 0x5845U
#define OV5640_G_HSCALE_HIGH 0x5846U
#define OV5640_G_HSCALE_LOW 0x5847U
#define OV5640_G_VSCALE_HIGH 0x5848U
#define OV5640_G_VSCALE_LOW 0x5849U
/* AFC control [0x6000 ~ 0x603F] */
#define OV5640_AFC_CTRL00 0x6000U
#define OV5640_AFC_CTRL01 0x6001U
#define OV5640_AFC_CTRL02 0x6002U
#define OV5640_AFC_CTRL03 0x6003U
#define OV5640_AFC_CTRL04 0x6004U
#define OV5640_AFC_CTRL05 0x6005U
#define OV5640_AFC_CTRL06 0x6006U
#define OV5640_AFC_CTRL07 0x6007U
#define OV5640_AFC_CTRL08 0x6008U
#define OV5640_AFC_CTRL09 0x6009U
#define OV5640_AFC_CTRL10 0x600AU
#define OV5640_AFC_CTRL11 0x600BU
#define OV5640_AFC_CTRL12 0x600CU
#define OV5640_AFC_CTRL13 0x600DU
#define OV5640_AFC_CTRL14 0x600EU
#define OV5640_AFC_CTRL15 0x600FU
#define OV5640_AFC_CTRL16 0x6010U
#define OV5640_AFC_CTRL17 0x6011U
#define OV5640_AFC_CTRL18 0x6012U
#define OV5640_AFC_CTRL19 0x6013U
#define OV5640_AFC_CTRL20 0x6014U
#define OV5640_AFC_CTRL21 0x6015U
#define OV5640_AFC_CTRL22 0x6016U
#define OV5640_AFC_CTRL23 0x6017U
#define OV5640_AFC_CTRL24 0x6018U
#define OV5640_AFC_CTRL25 0x6019U
#define OV5640_AFC_CTRL26 0x601AU
#define OV5640_AFC_CTRL27 0x601BU
#define OV5640_AFC_CTRL28 0x601CU
#define OV5640_AFC_CTRL29 0x601DU
#define OV5640_AFC_CTRL30 0x601EU
#define OV5640_AFC_CTRL31 0x601FU
#define OV5640_AFC_CTRL32 0x6020U
#define OV5640_AFC_CTRL33 0x6021U
#define OV5640_AFC_CTRL34 0x6022U
#define OV5640_AFC_CTRL35 0x6023U
#define OV5640_AFC_CTRL36 0x6024U
#define OV5640_AFC_CTRL37 0x6025U
#define OV5640_AFC_CTRL38 0x6026U
#define OV5640_AFC_CTRL39 0x6027U
#define OV5640_AFC_CTRL40 0x6028U
#define OV5640_AFC_CTRL41 0x6029U
#define OV5640_AFC_CTRL42 0x602AU
#define OV5640_AFC_CTRL43 0x602BU
#define OV5640_AFC_CTRL44 0x602CU
#define OV5640_AFC_CTRL45 0x602DU
#define OV5640_AFC_CTRL46 0x602EU
#define OV5640_AFC_CTRL47 0x602FU
#define OV5640_AFC_CTRL48 0x6030U
#define OV5640_AFC_CTRL49 0x6031U
#define OV5640_AFC_CTRL50 0x6032U
#define OV5640_AFC_CTRL51 0x6033U
#define OV5640_AFC_CTRL52 0x6034U
#define OV5640_AFC_CTRL53 0x6035U
#define OV5640_AFC_CTRL54 0x6036U
#define OV5640_AFC_CTRL55 0x6037U
#define OV5640_AFC_CTRL56 0x6038U
#define OV5640_AFC_CTRL57 0x6039U
#define OV5640_AFC_CTRL58 0x603AU
#define OV5640_AFC_CTRL59 0x603BU
#define OV5640_AFC_CTRL60 0x603CU
#define OV5640_AFC_READ58 0x603DU
#define OV5640_AFC_READ59 0x603EU
#define OV5640_AFC_READ60 0x603FU
void camera_sleep();
void camera_wakeup();
void camera_init();
#define PICTURE_BUFFER_SIZE 180000 // max support 150x4 = 600k
#endif //STM32U5_OV5640_H

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stm32u5/examples/cam_board/usb/ov5640_configs.h Executable file
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//
// Created by Guangzong Chen on 2/20/23.
//
// This file should only be include in ov5640.c not other files
#include "ov5640.h"
static uint16_t OV5640_Common[][2] =
{
{OV5640_SCCB_SYSTEM_CTRL1, 0x11},
{OV5640_SYSTEM_CTROL0, 0x82},
{OV5640_SCCB_SYSTEM_CTRL1, 0x03},
{OV5640_PAD_OUTPUT_ENABLE01, 0xFF},
{OV5640_PAD_OUTPUT_ENABLE02, 0xf3},
{OV5640_SC_PLL_CONTRL0, 0x18},
{OV5640_SYSTEM_CTROL0, 0x02},
{OV5640_SC_PLL_CONTRL1, 0x41},
{OV5640_SC_PLL_CONTRL2, 0x30},
{OV5640_SC_PLL_CONTRL3, 0x13},
{OV5640_SYSTEM_ROOT_DIVIDER, 0x01},
{0x3630, 0x36},
{0x3631, 0x0e},
{0x3632, 0xe2},
{0x3633, 0x12},
{0x3621, 0xe0},
{0x3704, 0xa0},
{0x3703, 0x5a},
{0x3715, 0x78},
{0x3717, 0x01},
{0x370b, 0x60},
{0x3705, 0x1a},
{0x3905, 0x02},
{0x3906, 0x10},
{0x3901, 0x0a},
{0x3731, 0x12},
{0x3600, 0x08},
{0x3601, 0x33},
{0x302d, 0x60},
{0x3620, 0x52},
{0x371b, 0x20},
{0x471c, 0x50},
{OV5640_AEC_CTRL13, 0x43},
{OV5640_AEC_GAIN_CEILING_HIGH, 0x00},
{OV5640_AEC_GAIN_CEILING_LOW, 0xf8},
{0x3635, 0x13},
{0x3636, 0x03},
{0x3634, 0x40},
{0x3622, 0x01},
{OV5640_5060HZ_CTRL01, 0x34},
{OV5640_5060HZ_CTRL04, 0x28},
{OV5640_5060HZ_CTRL05, 0x98},
{OV5640_LIGHTMETER1_TH_HIGH, 0x00},
{OV5640_LIGHTMETER1_TH_LOW, 0x00},
{OV5640_LIGHTMETER2_TH_HIGH, 0x01},
{OV5640_LIGHTMETER2_TH_LOW, 0x2c},
{OV5640_SAMPLE_NUMBER_HIGH, 0x9c},
{OV5640_SAMPLE_NUMBER_LOW, 0x40},
{OV5640_TIMING_TC_REG20, 0x06},
{OV5640_TIMING_TC_REG21, 0x00},
// {OV5640_TIMING_X_INC, 0x31},
// {OV5640_TIMING_Y_INC, 0x31},
// {OV5640_TIMING_HS_HIGH, 0x00},
// {OV5640_TIMING_HS_LOW, 0x00},
// {OV5640_TIMING_VS_HIGH, 0x00},
// {OV5640_TIMING_VS_LOW, 0x04},
// {OV5640_TIMING_HW_HIGH, 0x0a},
// {OV5640_TIMING_HW_LOW, 0x3f},
// {OV5640_TIMING_VH_HIGH, 0x07},
// {OV5640_TIMING_VH_LOW, 0x9b},
// {OV5640_TIMING_DVPHO_HIGH, 0x03},
// {OV5640_TIMING_DVPHO_LOW, 0x20},
// {OV5640_TIMING_DVPVO_HIGH, 0x02},
// {OV5640_TIMING_DVPVO_LOW, 0x58},
// {OV5640_TIMING_HTS_HIGH, 0x06},
// {OV5640_TIMING_HTS_LOW, 0x40},
// {OV5640_TIMING_VTS_HIGH, 0x03},
// {OV5640_TIMING_VTS_LOW, 0xe8},
// {OV5640_TIMING_HOFFSET_HIGH, 0x00},
// {OV5640_TIMING_HOFFSET_LOW, 0x10},
// {OV5640_TIMING_VOFFSET_HIGH, 0x00},
// {OV5640_TIMING_VOFFSET_LOW, 0x06},
{0x3618, 0x00},
{0x3612, 0x29},
{0x3708, 0x64},
{0x3709, 0x52},
{0x370c, 0x03},
{OV5640_AEC_CTRL02, 0x03},
{OV5640_AEC_CTRL03, 0xd8},
{OV5640_AEC_B50_STEP_HIGH, 0x01},
{OV5640_AEC_B50_STEP_LOW, 0x27},
{OV5640_AEC_B60_STEP_HIGH, 0x00},
{OV5640_AEC_B60_STEP_LOW, 0xf6},
{OV5640_AEC_CTRL0E, 0x03},
{OV5640_AEC_CTRL0D, 0x04},
{OV5640_AEC_MAX_EXPO_HIGH, 0x03},
{OV5640_AEC_MAX_EXPO_LOW, 0xd8},
{OV5640_BLC_CTRL01, 0x02},
{OV5640_BLC_CTRL04, 0x02},
{OV5640_SYSREM_RESET00, 0x00},
{OV5640_SYSREM_RESET02, 0x1c},
{OV5640_CLOCK_ENABLE00, 0xff},
{OV5640_CLOCK_ENABLE02, 0xc3},
{OV5640_MIPI_CONTROL00, 0x58},
{0x302e, 0x00},
{OV5640_POLARITY_CTRL, 0x22},
{OV5640_FORMAT_CTRL00, 0x6F},
{OV5640_FORMAT_MUX_CTRL, 0x01},
{OV5640_JPG_MODE_SELECT, 0x03},
{OV5640_JPEG_CTRL07, 0x04},
{0x440e, 0x00},
{0x460b, 0x35},
{0x460c, 0x23},
{OV5640_PCLK_PERIOD, 0x22},
{0x3824, 0x02},
{OV5640_ISP_CONTROL00, 0xa7},
{OV5640_ISP_CONTROL01, 0xa3},
{OV5640_AWB_CTRL00, 0xff},
{OV5640_AWB_CTRL01, 0xf2},
{OV5640_AWB_CTRL02, 0x00},
{OV5640_AWB_CTRL03, 0x14},
{OV5640_AWB_CTRL04, 0x25},
{OV5640_AWB_CTRL05, 0x24},
{OV5640_AWB_CTRL06, 0x09},
{OV5640_AWB_CTRL07, 0x09},
{OV5640_AWB_CTRL08, 0x09},
{OV5640_AWB_CTRL09, 0x75},
{OV5640_AWB_CTRL10, 0x54},
{OV5640_AWB_CTRL11, 0xe0},
{OV5640_AWB_CTRL12, 0xb2},
{OV5640_AWB_CTRL13, 0x42},
{OV5640_AWB_CTRL14, 0x3d},
{OV5640_AWB_CTRL15, 0x56},
{OV5640_AWB_CTRL16, 0x46},
{OV5640_AWB_CTRL17, 0xf8},
{OV5640_AWB_CTRL18, 0x04},
{OV5640_AWB_CTRL19, 0x70},
{OV5640_AWB_CTRL20, 0xf0},
{OV5640_AWB_CTRL21, 0xf0},
{OV5640_AWB_CTRL22, 0x03},
{OV5640_AWB_CTRL23, 0x01},
{OV5640_AWB_CTRL24, 0x04},
{OV5640_AWB_CTRL25, 0x12},
{OV5640_AWB_CTRL26, 0x04},
{OV5640_AWB_CTRL27, 0x00},
{OV5640_AWB_CTRL28, 0x06},
{OV5640_AWB_CTRL29, 0x82},
{OV5640_AWB_CTRL30, 0x38},
{OV5640_CMX1, 0x1e},
{OV5640_CMX2, 0x5b},
{OV5640_CMX3, 0x08},
{OV5640_CMX4, 0x0a},
{OV5640_CMX5, 0x7e},
{OV5640_CMX6, 0x88},
{OV5640_CMX7, 0x7c},
{OV5640_CMX8, 0x6c},
{OV5640_CMX9, 0x10},
{OV5640_CMXSIGN_HIGH, 0x01},
{OV5640_CMXSIGN_LOW, 0x98},
{OV5640_CIP_SHARPENMT_TH1, 0x08},
{OV5640_CIP_SHARPENMT_TH2, 0x30},
{OV5640_CIP_SHARPENMT_OFFSET1, 0x10},
{OV5640_CIP_SHARPENMT_OFFSET2, 0x00},
{OV5640_CIP_DNS_TH1, 0x08},
{OV5640_CIP_DNS_TH2, 0x30},
{OV5640_CIP_DNS_OFFSET1, 0x08},
{OV5640_CIP_DNS_OFFSET2, 0x16},
{OV5640_CIP_CTRL, 0x08},
{OV5640_CIP_SHARPENTH_TH1, 0x30},
{OV5640_CIP_SHARPENTH_TH2, 0x04},
{OV5640_CIP_SHARPENTH_OFFSET1, 0x06},
{OV5640_GAMMA_CTRL00, 0x01},
{OV5640_GAMMA_YST00, 0x08},
{OV5640_GAMMA_YST01, 0x14},
{OV5640_GAMMA_YST02, 0x28},
{OV5640_GAMMA_YST03, 0x51},
{OV5640_GAMMA_YST04, 0x65},
{OV5640_GAMMA_YST05, 0x71},
{OV5640_GAMMA_YST06, 0x7d},
{OV5640_GAMMA_YST07, 0x87},
{OV5640_GAMMA_YST08, 0x91},
{OV5640_GAMMA_YST09, 0x9a},
{OV5640_GAMMA_YST0A, 0xaa},
{OV5640_GAMMA_YST0B, 0xb8},
{OV5640_GAMMA_YST0C, 0xcd},
{OV5640_GAMMA_YST0D, 0xdd},
{OV5640_GAMMA_YST0E, 0xea},
{OV5640_GAMMA_YST0F, 0x1d},
{OV5640_SDE_CTRL0, 0x02},
{OV5640_SDE_CTRL3, 0x40},
{OV5640_SDE_CTRL4, 0x10},
{OV5640_SDE_CTRL9, 0x10},
{OV5640_SDE_CTRL10, 0x00},
{OV5640_SDE_CTRL11, 0xf8},
{OV5640_GMTRX00, 0x23},
{OV5640_GMTRX01, 0x14},
{OV5640_GMTRX02, 0x0f},
{OV5640_GMTRX03, 0x0f},
{OV5640_GMTRX04, 0x12},
{OV5640_GMTRX05, 0x26},
{OV5640_GMTRX10, 0x0c},
{OV5640_GMTRX11, 0x08},
{OV5640_GMTRX12, 0x05},
{OV5640_GMTRX13, 0x05},
{OV5640_GMTRX14, 0x08},
{OV5640_GMTRX15, 0x0d},
{OV5640_GMTRX20, 0x08},
{OV5640_GMTRX21, 0x03},
{OV5640_GMTRX22, 0x00},
{OV5640_GMTRX23, 0x00},
{OV5640_GMTRX24, 0x03},
{OV5640_GMTRX25, 0x09},
{OV5640_GMTRX30, 0x07},
{OV5640_GMTRX31, 0x03},
{OV5640_GMTRX32, 0x00},
{OV5640_GMTRX33, 0x01},
{OV5640_GMTRX34, 0x03},
{OV5640_GMTRX35, 0x08},
{OV5640_GMTRX40, 0x0d},
{OV5640_GMTRX41, 0x08},
{OV5640_GMTRX42, 0x05},
{OV5640_GMTRX43, 0x06},
{OV5640_GMTRX44, 0x08},
{OV5640_GMTRX45, 0x0e},
{OV5640_GMTRX50, 0x29},
{OV5640_GMTRX51, 0x17},
{OV5640_GMTRX52, 0x11},
{OV5640_GMTRX53, 0x11},
{OV5640_GMTRX54, 0x15},
{OV5640_GMTRX55, 0x28},
{OV5640_BRMATRX00, 0x46},
{OV5640_BRMATRX01, 0x26},
{OV5640_BRMATRX02, 0x08},
{OV5640_BRMATRX03, 0x26},
{OV5640_BRMATRX04, 0x64},
{OV5640_BRMATRX05, 0x26},
{OV5640_BRMATRX06, 0x24},
{OV5640_BRMATRX07, 0x22},
{OV5640_BRMATRX08, 0x24},
{OV5640_BRMATRX09, 0x24},
{OV5640_BRMATRX20, 0x06},
{OV5640_BRMATRX21, 0x22},
{OV5640_BRMATRX22, 0x40},
{OV5640_BRMATRX23, 0x42},
{OV5640_BRMATRX24, 0x24},
{OV5640_BRMATRX30, 0x26},
{OV5640_BRMATRX31, 0x24},
{OV5640_BRMATRX32, 0x22},
{OV5640_BRMATRX33, 0x22},
{OV5640_BRMATRX34, 0x26},
{OV5640_BRMATRX40, 0x44},
{OV5640_BRMATRX41, 0x24},
{OV5640_BRMATRX42, 0x26},
{OV5640_BRMATRX43, 0x28},
{OV5640_BRMATRX44, 0x42},
{OV5640_LENC_BR_OFFSET, 0xce},
{0x5025, 0x00},
{OV5640_AEC_CTRL0F, 0x30},
{OV5640_AEC_CTRL10, 0x28},
{OV5640_AEC_CTRL1B, 0x30},
{OV5640_AEC_CTRL1E, 0x26},
{OV5640_AEC_CTRL11, 0x60},
{OV5640_AEC_CTRL1F, 0x14},
{OV5640_SYSTEM_CTROL0, 0x02},
};
static const uint16_t OV5640_PF_JPEG[][2] =
{
/* SET PIXEL FORMAT: JPEG */
{OV5640_FORMAT_CTRL00, 0x30},
{OV5640_FORMAT_MUX_CTRL, 0x00},
// set resolution
{OV5640_TIMING_DVPHO_HIGH, 0x03},
{OV5640_TIMING_DVPHO_LOW, 0x20},
{OV5640_TIMING_DVPVO_HIGH, 0x01},
{OV5640_TIMING_DVPVO_LOW, 0xE0},
};
//static const uint16_t OV5640_QQVGA[][2] =
// {
// {OV5640_TIMING_DVPHO_HIGH, 0x00},
// {OV5640_TIMING_DVPHO_LOW, 0xA0},
// {OV5640_TIMING_DVPVO_HIGH, 0x00},
// {OV5640_TIMING_DVPVO_LOW, 0x78},
// };
//static const uint16_t OV5640_PF_YUV422[][2] =
// {
// /* SET PIXEL FORMAT: YUV422 */
// {OV5640_FORMAT_CTRL00, 0x30},
// {OV5640_FORMAT_MUX_CTRL, 0x00},
// };
//
//static const uint16_t OV5640_PF_RGB888[][2] =
// {
// /* SET PIXEL FORMAT: RGB888 (RGBRGB)*/
// {OV5640_FORMAT_CTRL00, 0x23},
// {OV5640_FORMAT_MUX_CTRL, 0x01},
// };
//static const uint16_t OV5640_VGA[][2] =
// {
// {OV5640_TIMING_DVPHO_HIGH, 0x02},
// {OV5640_TIMING_DVPHO_LOW, 0x80},
// {OV5640_TIMING_DVPVO_HIGH, 0x01},
// {OV5640_TIMING_DVPVO_LOW, 0xE0},
// };
///* Initialization sequence for WVGA resolution (800x480)*/
//static const uint16_t OV5640_WVGA[][2] =
// {
// {OV5640_TIMING_DVPHO_HIGH, 0x03},
// {OV5640_TIMING_DVPHO_LOW, 0x20},
// {OV5640_TIMING_DVPVO_HIGH, 0x01},
// {OV5640_TIMING_DVPVO_LOW, 0xE0},
// };
//
//
///* Initialization sequence for 480x272 resolution */
//static const uint16_t OV5640_480x272[][2] =
// {
// {OV5640_TIMING_DVPHO_HIGH, 0x01},
// {OV5640_TIMING_DVPHO_LOW, 0xE0},
// {OV5640_TIMING_DVPVO_HIGH, 0x01},
// {OV5640_TIMING_DVPVO_LOW, 0x10},
// };
/* Initialization sequence for QVGA resolution (320x240) */
// static const uint16_t OV5640_QVGA[][2] =
// {
// {OV5640_TIMING_DVPHO_HIGH, 0x01},
// {OV5640_TIMING_DVPHO_LOW, 0x40},
// {OV5640_TIMING_DVPVO_HIGH, 0x00},
// {OV5640_TIMING_DVPVO_LOW, 0xF0},
// };

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stm32u5/examples/connie/CMSIS/Include/cmsis_armcc.h Executable file
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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2019 IAR Systems
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __PROGRAM_START
#define __PROGRAM_START __iar_program_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP CSTACK$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT CSTACK$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __vector_table
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.3
* @date 24. June 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 13. March 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t vectors = 0x0U;
(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = 0x0U;
return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.1
* @date 12. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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