308 lines
14 KiB
C
Executable File
308 lines
14 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t pwrctrl : 2; // 0 SDMMC state control bits
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uint32_t vswitch : 1; // 2 Voltage switch sequence start
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uint32_t vswitchen : 1; // 3 Voltage switch procedure enable
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uint32_t dirpol : 1; // 4 Data and command direction signals polarity selection
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uint32_t reserve0 : 27; // 5 Reserve
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} reg_sdmmc_power_t2;
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typedef struct {
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uint32_t clkdiv : 10; // 0 Clock divide factor
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uint32_t reserve0 : 2; // 10 Reserve
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uint32_t pwrsav : 1; // 12 Power saving configuration bit
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uint32_t reserve1 : 1; // 13 Reserve
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uint32_t widbus : 2; // 14 Wide bus mode enable bit
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uint32_t negedge : 1; // 16 SDIO_CK dephasing selection bit
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uint32_t hwfc_en : 1; // 17 HW Flow Control enable
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uint32_t ddr : 1; // 18 Data rate signaling selection
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uint32_t busspeed : 1; // 19 Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50, SDR104
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uint32_t selclkrx : 2; // 20 Receive clock selection
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uint32_t reserve2 : 10; // 22 Reserve
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} reg_sdmmc_clkcr_t2;
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typedef struct {
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uint32_t cmdarg : 32; // 0 Command argument
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} reg_sdmmc_argr_t;
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typedef struct {
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uint32_t cmdindex : 6; // 0 Command index
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uint32_t cmdtrans : 1; // 6 The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM
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uint32_t cmdstop : 1; // 7 The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM
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uint32_t waitresp : 2; // 8 Wait for response bits
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uint32_t waitint : 1; // 10 CPSM waits for interrupt request
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uint32_t waitpend : 1; // 11 CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM
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uint32_t cpsmen : 1; // 12 Command path state machine (CPSM) Enable bit
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uint32_t dthold : 1; // 13 Hold new data block transmission and reception in the DPSM
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uint32_t bootmode : 1; // 14 Select the boot mode procedure to be used
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uint32_t booten : 1; // 15 Enable boot mode procedure
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uint32_t cmdsuspend: 1; // 16 The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end
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uint32_t reserve0 : 15; // 17 Reserve
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} reg_sdmmc_cmdr_t;
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typedef struct {
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uint32_t respcmd : 6; // 0 Response command index
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uint32_t reserve0 : 26; // 6 Reserve
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} reg_sdmmc_respcmdr_t;
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typedef struct {
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uint32_t cardstatus1: 32; // 0 CARDSTATUS1
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} reg_sdmmc_resp1_t;
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typedef struct {
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uint32_t cardstatus2: 32; // 0 CARDSTATUS2
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} reg_sdmmc_resp2_t;
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typedef struct {
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uint32_t cardstatus3: 32; // 0 CARDSTATUS3
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} reg_sdmmc_resp3_t;
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typedef struct {
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uint32_t cardstatus4: 32; // 0 CARDSTATUS4
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} reg_sdmmc_resp4_t;
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typedef struct {
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uint32_t datatime : 32; // 0 Data and R1b busy timeout period
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} reg_sdmmc_dtimer_t;
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typedef struct {
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uint32_t datalength: 25; // 0 Data length value
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uint32_t reserve0 : 7; // 25 Reserve
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} reg_sdmmc_dlenr_t;
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typedef struct {
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uint32_t dten : 1; // 0 DTEN
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uint32_t dtdir : 1; // 1 Data transfer direction selection
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uint32_t dtmode : 2; // 2 Data transfer mode selection
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uint32_t dblocksize: 4; // 4 Data block size
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uint32_t rwstart : 1; // 8 Read wait start
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uint32_t rwstop : 1; // 9 Read wait stop
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uint32_t rwmod : 1; // 10 Read wait mode
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uint32_t sdioen : 1; // 11 SD I/O enable functions
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uint32_t bootacken : 1; // 12 Enable the reception of the boot acknowledgment
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uint32_t fiforst : 1; // 13 FIFO reset, will flush any remaining data
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uint32_t reserve0 : 18; // 14 Reserve
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} reg_sdmmc_dctrl_t2;
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typedef struct {
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uint32_t datacount : 25; // 0 Data count value
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uint32_t reserve0 : 7; // 25 Reserve
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} reg_sdmmc_dcntr_t;
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typedef struct {
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uint32_t ccrcfail : 1; // 0 Command response received (CRC check failed)
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uint32_t dcrcfail : 1; // 1 Data block sent/received (CRC check failed)
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uint32_t ctimeout : 1; // 2 Command response timeout
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uint32_t dtimeout : 1; // 3 Data timeout
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uint32_t txunderr : 1; // 4 Transmit FIFO underrun error (masked by hardware when IDMA is enabled)
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uint32_t rxoverr : 1; // 5 Received FIFO overrun error (masked by hardware when IDMA is enabled)
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uint32_t cmdrend : 1; // 6 Command response received (CRC check passed, or no CRC)
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uint32_t cmdsent : 1; // 7 Command sent (no response required)
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uint32_t dataend : 1; // 8 Data transfer ended correctly
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uint32_t dhold : 1; // 9 Data transfer Hold
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uint32_t dbckend : 1; // 10 Data block sent/received
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uint32_t dabort : 1; // 11 Data transfer aborted by CMD12
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uint32_t dpsmact : 1; // 12 Data path state machine active, i.e. not in Idle state
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uint32_t cpsmact : 1; // 13 Command path state machine active, i.e. not in Idle state
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uint32_t txfifohe : 1; // 14 Transmit FIFO half empty
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uint32_t rxfifohf : 1; // 15 Receive FIFO half full
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uint32_t txfifof : 1; // 16 Transmit FIFO full
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uint32_t rxfifof : 1; // 17 Receive FIFO full
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uint32_t txfifoe : 1; // 18 Transmit FIFO empty
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uint32_t rxfifoe : 1; // 19 Receive FIFO empty
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uint32_t busyd0 : 1; // 20 Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response
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uint32_t busyd0end : 1; // 21 end of SDMMC_D0 Busy following a CMD response detected
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uint32_t sdioit : 1; // 22 SDIO interrupt received
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uint32_t ackfail : 1; // 23 Boot acknowledgment received (boot acknowledgment check fail)
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uint32_t acktimeout: 1; // 24 Boot acknowledgment timeout
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uint32_t vswend : 1; // 25 Voltage switch critical timing section completion
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uint32_t ckstop : 1; // 26 SDMMC_CK stopped in Voltage switch procedure
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uint32_t idmate : 1; // 27 IDMA transfer error
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uint32_t idmabtc : 1; // 28 IDMA buffer transfer complete
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uint32_t reserve0 : 3; // 29 Reserve
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} reg_sdmmc_star_t;
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typedef struct {
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uint32_t ccrcfailc : 1; // 0 CCRCFAIL flag clear bit
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uint32_t dcrcfailc : 1; // 1 DCRCFAIL flag clear bit
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uint32_t ctimeoutc : 1; // 2 CTIMEOUT flag clear bit
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uint32_t dtimeoutc : 1; // 3 DTIMEOUT flag clear bit
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uint32_t txunderrc : 1; // 4 TXUNDERR flag clear bit
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uint32_t rxoverrc : 1; // 5 RXOVERR flag clear bit
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uint32_t cmdrendc : 1; // 6 CMDREND flag clear bit
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uint32_t cmdsentc : 1; // 7 CMDSENT flag clear bit
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uint32_t dataendc : 1; // 8 DATAEND flag clear bit
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uint32_t dholdc : 1; // 9 DHOLD flag clear bit
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uint32_t dbckendc : 1; // 10 DBCKEND flag clear bit
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uint32_t dabortc : 1; // 11 DABORT flag clear bit
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uint32_t reserve0 : 9; // 12 Reserve
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uint32_t busyd0endc: 1; // 21 BUSYD0END flag clear bit
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uint32_t sdioitc : 1; // 22 SDIOIT flag clear bit
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uint32_t ackfailc : 1; // 23 ACKFAIL flag clear bit
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uint32_t acktimeoutc: 1; // 24 ACKTIMEOUT flag clear bit
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uint32_t vswendc : 1; // 25 VSWEND flag clear bit
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uint32_t ckstopc : 1; // 26 CKSTOP flag clear bit
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uint32_t idmatec : 1; // 27 IDMA transfer error clear bit
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uint32_t idmabtcc : 1; // 28 IDMA buffer transfer complete clear bit
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uint32_t reserve1 : 3; // 29 Reserve
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} reg_sdmmc_icr_t;
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typedef struct {
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uint32_t ccrcfailie: 1; // 0 Command CRC fail interrupt enable
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uint32_t dcrcfailie: 1; // 1 Data CRC fail interrupt enable
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uint32_t ctimeoutie: 1; // 2 Command timeout interrupt enable
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uint32_t dtimeoutie: 1; // 3 Data timeout interrupt enable
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uint32_t txunderrie: 1; // 4 Tx FIFO underrun error interrupt enable
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uint32_t rxoverrie : 1; // 5 Rx FIFO overrun error interrupt enable
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uint32_t cmdrendie : 1; // 6 Command response received interrupt enable
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uint32_t cmdsentie : 1; // 7 Command sent interrupt enable
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uint32_t dataendie : 1; // 8 Data end interrupt enable
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uint32_t dholdie : 1; // 9 Data hold interrupt enable
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uint32_t dbckendie : 1; // 10 Data block end interrupt enable
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uint32_t dabortie : 1; // 11 Data transfer aborted interrupt enable
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uint32_t reserve0 : 2; // 12 Reserve
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uint32_t txfifoheie: 1; // 14 Tx FIFO half empty interrupt enable
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uint32_t rxfifohfie: 1; // 15 Rx FIFO half full interrupt enable
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uint32_t reserve1 : 1; // 16 Reserve
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uint32_t rxfifofie : 1; // 17 Rx FIFO full interrupt enable
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uint32_t txfifoeie : 1; // 18 Tx FIFO empty interrupt enable
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uint32_t reserve2 : 2; // 19 Reserve
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uint32_t busyd0endie: 1; // 21 BUSYD0END interrupt enable
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uint32_t sdioitie : 1; // 22 SDIO mode interrupt received interrupt enable
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uint32_t ackfailie : 1; // 23 Acknowledgment Fail interrupt enable
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uint32_t acktimeoutie: 1; // 24 Acknowledgment timeout interrupt enable
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uint32_t vswendie : 1; // 25 Voltage switch critical timing section completion interrupt enable
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uint32_t ckstopie : 1; // 26 Voltage Switch clock stopped interrupt enable
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uint32_t reserve3 : 1; // 27 Reserve
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uint32_t idmabtcie : 1; // 28 IDMA buffer transfer complete interrupt enable
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uint32_t reserve4 : 3; // 29 Reserve
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} reg_sdmmc_maskr_t;
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typedef struct {
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uint32_t acktime : 25; // 0 Boot acknowledgment timeout period
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uint32_t reserve0 : 7; // 25 Reserve
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} reg_sdmmc_acktimer_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor0_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor1_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor2_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor3_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor4_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor5_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor6_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor7_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor8_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor9_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor10_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor11_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor12_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor13_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor14_t;
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typedef struct {
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uint32_t fifodata : 32; // 0 Receive and transmit FIFO data
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} reg_sdmmc_fifor15_t;
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typedef struct {
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uint32_t idmaen : 1; // 0 IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
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uint32_t idmabmode : 1; // 1 Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
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uint32_t reserve0 : 30; // 2 Reserve
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} reg_sdmmc_idmactrlr_t;
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typedef struct {
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uint32_t reserve0 : 5; // 0 Reserve
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uint32_t idmabndt : 12; // 5 Number of bytes per buffer
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uint32_t reserve1 : 15; // 17 Reserve
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} reg_sdmmc_idmabsizer_t;
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typedef struct {
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uint32_t idmabase : 32; // 0 Buffer memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only)
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} reg_sdmmc_idmabaser_t;
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typedef struct {
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uint32_t reserve0 : 2; // 0 Reserve
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uint32_t idmala : 14; // 2 Acknowledge linked list buffer ready
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uint32_t reserve1 : 13; // 16 Reserve
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uint32_t abr : 1; // 29 Acknowledge linked list buffer ready
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uint32_t uls : 1; // 30 Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1)
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uint32_t ula : 1; // 31 Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode)
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} reg_sdmmc_idmalar_t2;
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typedef struct {
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uint32_t reserve0 : 2; // 0 Reserve
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uint32_t idmaba : 30; // 2 Word aligned Linked list memory base address
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} reg_sdmmc_idmabar_t;
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typedef struct {
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volatile reg_sdmmc_power_t2 power;
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volatile reg_sdmmc_clkcr_t2 clkcr;
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volatile reg_sdmmc_argr_t argr;
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volatile reg_sdmmc_cmdr_t cmdr;
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volatile reg_sdmmc_respcmdr_t respcmdr;
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volatile reg_sdmmc_resp1_t resp1;
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volatile reg_sdmmc_resp2_t resp2;
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volatile reg_sdmmc_resp3_t resp3;
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volatile reg_sdmmc_resp4_t resp4;
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volatile reg_sdmmc_dtimer_t dtimer;
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volatile reg_sdmmc_dlenr_t dlenr;
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volatile reg_sdmmc_dctrl_t2 dctrl;
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volatile reg_sdmmc_dcntr_t dcntr;
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volatile reg_sdmmc_star_t star;
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volatile reg_sdmmc_icr_t icr;
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volatile reg_sdmmc_maskr_t maskr;
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volatile reg_sdmmc_acktimer_t acktimer;
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volatile uint32_t reserve0[3];
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volatile reg_sdmmc_idmactrlr_t idmactrlr;
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volatile reg_sdmmc_idmabsizer_t idmabsizer;
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volatile reg_sdmmc_idmabaser_t idmabaser;
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volatile uint32_t reserve2[2];
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volatile reg_sdmmc_idmalar_t2 idmalar;
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volatile reg_sdmmc_idmabar_t idmabar;
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} reg_sdmmc_t;
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