307 lines
10 KiB
C
Executable File
307 lines
10 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t ecce : 1; // 0 ECCE
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uint32_t reserve0 : 3; // 1 Reserve
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uint32_t ale : 1; // 4 ALE
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uint32_t reserve1 : 3; // 5 Reserve
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uint32_t sramer : 1; // 8 SRAMER
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uint32_t reserve2 : 7; // 9 Reserve
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uint32_t wsc : 3; // 16 WSC
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uint32_t reserve3 : 13; // 19 Reserve
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} reg_sec_ramcfg_ram1cr_t;
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typedef struct {
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uint32_t sedc : 1; // 0 SEDC
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uint32_t ded : 1; // 1 DED
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uint32_t reserve0 : 6; // 2 Reserve
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uint32_t srambusy : 1; // 8 SRAMBUSY
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uint32_t reserve1 : 23; // 9 Reserve
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} reg_sec_ramcfg_ram1isr_t;
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typedef struct {
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uint32_t erasekey : 8; // 0 ERASEKEY
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uint32_t reserve0 : 24; // 8 Reserve
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} reg_sec_ramcfg_ram1erkeyr_t;
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typedef struct {
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uint32_t ecce : 1; // 0 ECCE
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uint32_t reserve0 : 3; // 1 Reserve
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uint32_t ale : 1; // 4 ALE
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uint32_t reserve1 : 3; // 5 Reserve
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uint32_t sramer : 1; // 8 SRAMER
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uint32_t reserve2 : 7; // 9 Reserve
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uint32_t wsc : 3; // 16 WSC
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uint32_t reserve3 : 13; // 19 Reserve
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} reg_sec_ramcfg_ram2cr_t;
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typedef struct {
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uint32_t seie : 1; // 0 SEIE
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uint32_t deie : 1; // 1 DEIE
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uint32_t reserve0 : 1; // 2 Reserve
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uint32_t eccnmi : 1; // 3 ECCNMI
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uint32_t reserve1 : 28; // 4 Reserve
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} reg_sec_ramcfg_ram2ier_t;
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typedef struct {
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uint32_t sedc : 1; // 0 SEDC
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uint32_t ded : 1; // 1 DED
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uint32_t reserve0 : 6; // 2 Reserve
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uint32_t srambusy : 1; // 8 SRAMBUSY
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uint32_t reserve1 : 23; // 9 Reserve
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} reg_sec_ramcfg_ram2isr_t;
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typedef struct {
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uint32_t esea : 32; // 0 ESEA
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} reg_sec_ramcfg_ram2sear_t;
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typedef struct {
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uint32_t edea : 32; // 0 EDEA
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} reg_sec_ramcfg_ram2dear_t;
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typedef struct {
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uint32_t csedc : 1; // 0 CSEDC
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uint32_t cded : 1; // 1 CDED
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uint32_t reserve0 : 30; // 2 Reserve
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} reg_sec_ramcfg_ram2icr_t;
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typedef struct {
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uint32_t p0wp : 1; // 0 P0WP
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uint32_t p1wp : 1; // 1 P1WP
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uint32_t p2wp : 1; // 2 P2WP
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uint32_t p3wp : 1; // 3 P3WP
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uint32_t p4wp : 1; // 4 P4WP
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uint32_t p5wp : 1; // 5 P5WP
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uint32_t p6wp : 1; // 6 P6WP
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uint32_t p7wp : 1; // 7 P7WP
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uint32_t p8wp : 1; // 8 P8WP
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uint32_t p9wp : 1; // 9 P9WP
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uint32_t p10wp : 1; // 10 P10WP
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uint32_t p11wp : 1; // 11 P11WP
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uint32_t p12wp : 1; // 12 P12WP
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uint32_t p13wp : 1; // 13 P13WP
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uint32_t p14wp : 1; // 14 P14WP
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uint32_t p15wp : 1; // 15 P15WP
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uint32_t p16wp : 1; // 16 P16WP
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uint32_t p17wp : 1; // 17 P17WP
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uint32_t p18wp : 1; // 18 P18WP
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uint32_t p19wp : 1; // 19 P19WP
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uint32_t p20wp : 1; // 20 P20WP
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uint32_t p21wp : 1; // 21 P21WP
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uint32_t p22wp : 1; // 22 P22WP
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uint32_t p23wp : 1; // 23 P23WP
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uint32_t p24wp : 1; // 24 P24WP
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uint32_t p25wp : 1; // 25 P25WP
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uint32_t p26wp : 1; // 26 P26WP
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uint32_t p27wp : 1; // 27 P27WP
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uint32_t p28wp : 1; // 28 P28WP
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uint32_t p29wp : 1; // 29 P29WP
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uint32_t p30wp : 1; // 30 P30WP
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uint32_t p31wp : 1; // 31 P31WP
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} reg_sec_ramcfg_ram2wpr1_t;
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typedef struct {
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uint32_t p32wp : 1; // 0 P32WP
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uint32_t p33wp : 1; // 1 P33WP
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uint32_t p34wp : 1; // 2 P34WP
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uint32_t p35wp : 1; // 3 P35WP
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uint32_t p36wp : 1; // 4 P36WP
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uint32_t p37wp : 1; // 5 P37WP
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uint32_t p38wp : 1; // 6 P38WP
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uint32_t p39wp : 1; // 7 P39WP
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uint32_t p40wp : 1; // 8 P40WP
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uint32_t p41wp : 1; // 9 P41WP
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uint32_t p42wp : 1; // 10 P42WP
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uint32_t p43wp : 1; // 11 P43WP
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uint32_t p44wp : 1; // 12 P44WP
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uint32_t p45wp : 1; // 13 P45WP
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uint32_t p46wp : 1; // 14 P46WP
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uint32_t p47wp : 1; // 15 P47WP
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uint32_t p48wp : 1; // 16 P48WP
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uint32_t p49wp : 1; // 17 P49WP
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uint32_t p50wp : 1; // 18 P50WP
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uint32_t p51wp : 1; // 19 P51WP
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uint32_t p52wp : 1; // 20 P52WP
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uint32_t p53wp : 1; // 21 P53WP
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uint32_t p54wp : 1; // 22 P54WP
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uint32_t p55wp : 1; // 23 P55WP
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uint32_t p56wp : 1; // 24 P56WP
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uint32_t p57wp : 1; // 25 P57WP
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uint32_t p58wp : 1; // 26 P58WP
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uint32_t p59wp : 1; // 27 P59WP
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uint32_t p60wp : 1; // 28 P60WP
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uint32_t p61wp : 1; // 29 P61WP
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uint32_t p62wp : 1; // 30 P62WP
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uint32_t p63wp : 1; // 31 P63WP
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} reg_sec_ramcfg_ram2wpr2_t;
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typedef struct {
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uint32_t ecckey : 8; // 0 ECCKEY
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uint32_t reserve0 : 24; // 8 Reserve
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} reg_sec_ramcfg_ram2ecckeyr_t;
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typedef struct {
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uint32_t erasekey : 8; // 0 ERASEKEY
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uint32_t reserve0 : 24; // 8 Reserve
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} reg_sec_ramcfg_ram2erkeyr_t;
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typedef struct {
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uint32_t ecce : 1; // 0 ECCE
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uint32_t reserve0 : 3; // 1 Reserve
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uint32_t ale : 1; // 4 ALE
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uint32_t reserve1 : 3; // 5 Reserve
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uint32_t sramer : 1; // 8 SRAMER
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uint32_t reserve2 : 7; // 9 Reserve
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uint32_t wsc : 3; // 16 WSC
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uint32_t reserve3 : 13; // 19 Reserve
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} reg_sec_ramcfg_ram3cr_t;
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typedef struct {
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uint32_t seie : 1; // 0 SEIE
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uint32_t deie : 1; // 1 DEIE
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uint32_t reserve0 : 1; // 2 Reserve
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uint32_t eccnmi : 1; // 3 ECCNMI
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uint32_t reserve1 : 28; // 4 Reserve
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} reg_sec_ramcfg_ram3ier_t;
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typedef struct {
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uint32_t sedc : 1; // 0 SEDC
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uint32_t ded : 1; // 1 DED
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uint32_t reserve0 : 6; // 2 Reserve
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uint32_t srambusy : 1; // 8 SRAMBUSY
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uint32_t reserve1 : 23; // 9 Reserve
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} reg_sec_ramcfg_ram3isr_t;
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typedef struct {
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uint32_t esea : 32; // 0 ESEA
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} reg_sec_ramcfg_ram3sear_t;
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typedef struct {
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uint32_t edea : 32; // 0 EDEA
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} reg_sec_ramcfg_ram3dear_t;
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typedef struct {
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uint32_t csedc : 1; // 0 CSEDC
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uint32_t cded : 1; // 1 CDED
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uint32_t reserve0 : 30; // 2 Reserve
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} reg_sec_ramcfg_ram3icr_t;
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typedef struct {
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uint32_t ecckey : 8; // 0 ECCKEY
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uint32_t reserve0 : 24; // 8 Reserve
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} reg_sec_ramcfg_ram3ecckeyr_t;
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typedef struct {
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uint32_t erasekey : 8; // 0 ERASEKEY
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uint32_t reserve0 : 24; // 8 Reserve
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} reg_sec_ramcfg_ram3erkeyr_t;
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typedef struct {
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uint32_t ecce : 1; // 0 ECCE
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uint32_t reserve0 : 3; // 1 Reserve
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uint32_t ale : 1; // 4 ALE
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uint32_t reserve1 : 3; // 5 Reserve
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uint32_t sramer : 1; // 8 SRAMER
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uint32_t reserve2 : 7; // 9 Reserve
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uint32_t wsc : 3; // 16 WSC
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uint32_t reserve3 : 13; // 19 Reserve
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} reg_sec_ramcfg_ram4cr_t;
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typedef struct {
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uint32_t sedc : 1; // 0 SEDC
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uint32_t ded : 1; // 1 DED
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uint32_t reserve0 : 6; // 2 Reserve
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uint32_t srambusy : 1; // 8 SRAMBUSY
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uint32_t reserve1 : 23; // 9 Reserve
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} reg_sec_ramcfg_ram4isr_t;
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typedef struct {
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uint32_t erasekey : 8; // 0 ERASEKEY
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uint32_t reserve0 : 24; // 8 Reserve
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} reg_sec_ramcfg_ram4erkeyr_t;
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typedef struct {
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uint32_t ecce : 1; // 0 ECCE
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uint32_t reserve0 : 3; // 1 Reserve
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uint32_t ale : 1; // 4 ALE
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uint32_t reserve1 : 3; // 5 Reserve
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uint32_t sramer : 1; // 8 SRAMER
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uint32_t reserve2 : 7; // 9 Reserve
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uint32_t wsc : 3; // 16 WSC
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uint32_t reserve3 : 13; // 19 Reserve
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} reg_sec_ramcfg_ram5cr_t;
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typedef struct {
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uint32_t seie : 1; // 0 SEIE
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uint32_t deie : 1; // 1 DEIE
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uint32_t reserve0 : 1; // 2 Reserve
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uint32_t eccnmi : 1; // 3 ECCNMI
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uint32_t reserve1 : 28; // 4 Reserve
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} reg_sec_ramcfg_ram5ier_t;
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typedef struct {
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uint32_t sedc : 1; // 0 SEDC
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uint32_t ded : 1; // 1 DED
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uint32_t reserve0 : 6; // 2 Reserve
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uint32_t srambusy : 1; // 8 SRAMBUSY
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uint32_t reserve1 : 23; // 9 Reserve
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} reg_sec_ramcfg_ram5isr_t;
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typedef struct {
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uint32_t esea : 32; // 0 ESEA
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} reg_sec_ramcfg_ram5sear_t;
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typedef struct {
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uint32_t edea : 32; // 0 EDEA
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} reg_sec_ramcfg_ram5dear_t;
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typedef struct {
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uint32_t csedc : 1; // 0 CSEDC
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uint32_t cded : 1; // 1 CDED
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uint32_t reserve0 : 30; // 2 Reserve
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} reg_sec_ramcfg_ram5icr_t;
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typedef struct {
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volatile reg_sec_ramcfg_ram1cr_t ram1cr;
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volatile uint32_t reserve0[1];
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volatile reg_sec_ramcfg_ram1isr_t ram1isr;
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volatile uint32_t reserve1[7];
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volatile reg_sec_ramcfg_ram1erkeyr_t ram1erkeyr;
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volatile uint32_t reserve2[5];
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volatile reg_sec_ramcfg_ram2cr_t ram2cr;
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volatile reg_sec_ramcfg_ram2ier_t ram2ier;
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volatile reg_sec_ramcfg_ram2isr_t ram2isr;
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volatile reg_sec_ramcfg_ram2sear_t ram2sear;
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volatile reg_sec_ramcfg_ram2dear_t ram2dear;
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volatile reg_sec_ramcfg_ram2icr_t ram2icr;
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volatile reg_sec_ramcfg_ram2wpr1_t ram2wpr1;
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volatile reg_sec_ramcfg_ram2wpr2_t ram2wpr2;
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volatile uint32_t reserve3[1];
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volatile reg_sec_ramcfg_ram2ecckeyr_t ram2ecckeyr;
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volatile reg_sec_ramcfg_ram2erkeyr_t ram2erkeyr;
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volatile uint32_t reserve4[5];
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volatile reg_sec_ramcfg_ram3cr_t ram3cr;
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volatile reg_sec_ramcfg_ram3ier_t ram3ier;
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volatile reg_sec_ramcfg_ram3isr_t ram3isr;
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volatile reg_sec_ramcfg_ram3sear_t ram3sear;
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volatile reg_sec_ramcfg_ram3dear_t ram3dear;
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volatile reg_sec_ramcfg_ram3icr_t ram3icr;
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volatile uint32_t reserve5[3];
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volatile reg_sec_ramcfg_ram3ecckeyr_t ram3ecckeyr;
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volatile reg_sec_ramcfg_ram3erkeyr_t ram3erkeyr;
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volatile uint32_t reserve6[5];
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volatile reg_sec_ramcfg_ram4cr_t ram4cr;
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volatile uint32_t reserve7[1];
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volatile reg_sec_ramcfg_ram4isr_t ram4isr;
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volatile uint32_t reserve8[7];
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volatile reg_sec_ramcfg_ram4erkeyr_t ram4erkeyr;
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volatile uint32_t reserve9[5];
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volatile reg_sec_ramcfg_ram5cr_t ram5cr;
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volatile reg_sec_ramcfg_ram5ier_t ram5ier;
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volatile reg_sec_ramcfg_ram5isr_t ram5isr;
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volatile reg_sec_ramcfg_ram5sear_t ram5sear;
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volatile reg_sec_ramcfg_ram5dear_t ram5dear;
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volatile reg_sec_ramcfg_ram5icr_t ram5icr;
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} reg_sec_ramcfg_t;
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