239 lines
29 KiB
C
Executable File
239 lines
29 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t sec0 : 1; // 0 SEC0
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uint32_t sec1 : 1; // 1 SEC1
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uint32_t sec2 : 1; // 2 SEC2
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uint32_t sec3 : 1; // 3 SEC3
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uint32_t sec4 : 1; // 4 SEC4
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uint32_t sec5 : 1; // 5 SEC5
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uint32_t sec6 : 1; // 6 SEC6
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uint32_t sec7 : 1; // 7 SEC7
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uint32_t sec8 : 1; // 8 SEC8
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uint32_t sec9 : 1; // 9 SEC9
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uint32_t sec10 : 1; // 10 SEC10
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uint32_t sec11 : 1; // 11 SEC11
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uint32_t sec12 : 1; // 12 SEC12
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uint32_t sec13 : 1; // 13 SEC13
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uint32_t sec14 : 1; // 14 SEC14
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uint32_t sec15 : 1; // 15 SEC15
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_gpdma_seccfgr_t;
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typedef struct {
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uint32_t priv0 : 1; // 0 PRIV0
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uint32_t priv1 : 1; // 1 PRIV1
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uint32_t priv2 : 1; // 2 PRIV2
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uint32_t priv3 : 1; // 3 PRIV3
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uint32_t priv4 : 1; // 4 PRIV4
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uint32_t priv5 : 1; // 5 PRIV5
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uint32_t priv6 : 1; // 6 PRIV6
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uint32_t priv7 : 1; // 7 PRIV7
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uint32_t priv8 : 1; // 8 PRIV8
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uint32_t priv9 : 1; // 9 PRIV9
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uint32_t priv10 : 1; // 10 PRIV10
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uint32_t priv11 : 1; // 11 PRIV11
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uint32_t priv12 : 1; // 12 PRIV12
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uint32_t priv13 : 1; // 13 PRIV13
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uint32_t priv14 : 1; // 14 PRIV14
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uint32_t priv15 : 1; // 15 PRIV15
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_gpdma_privcfgr_t;
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typedef struct {
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uint32_t lock0 : 1; // 0 LOCK0
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uint32_t lock1 : 1; // 1 LOCK1
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uint32_t lock2 : 1; // 2 LOCK2
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uint32_t lock3 : 1; // 3 LOCK3
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uint32_t lock4 : 1; // 4 LOCK4
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uint32_t lock5 : 1; // 5 LOCK5
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uint32_t lock6 : 1; // 6 LOCK6
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uint32_t lock7 : 1; // 7 LOCK7
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uint32_t lock8 : 1; // 8 LOCK8
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uint32_t lock9 : 1; // 9 LOCK9
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uint32_t lock10 : 1; // 10 LOCK10
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uint32_t lock11 : 1; // 11 LOCK11
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uint32_t lock12 : 1; // 12 LOCK12
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uint32_t lock13 : 1; // 13 LOCK13
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uint32_t lock14 : 1; // 14 LOCK14
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uint32_t lock15 : 1; // 15 LOCK15
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_gpdma_rcfglockr_t;
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typedef struct {
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uint32_t mis0 : 1; // 0 MIS0
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uint32_t mis1 : 1; // 1 MIS1
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uint32_t mis2 : 1; // 2 MIS2
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uint32_t mis3 : 1; // 3 MIS3
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uint32_t mis4 : 1; // 4 MIS4
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uint32_t mis5 : 1; // 5 MIS5
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uint32_t mis6 : 1; // 6 MIS6
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uint32_t mis7 : 1; // 7 MIS7
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uint32_t mis8 : 1; // 8 MIS8
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uint32_t mis9 : 1; // 9 MIS9
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uint32_t mis10 : 1; // 10 MIS10
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uint32_t mis11 : 1; // 11 MIS11
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uint32_t mis12 : 1; // 12 MIS12
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uint32_t mis13 : 1; // 13 MIS13
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uint32_t mis14 : 1; // 14 MIS14
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uint32_t mis15 : 1; // 15 MIS15
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_gpdma_misr_t;
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typedef struct {
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uint32_t mis0 : 1; // 0 MIS0
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uint32_t mis1 : 1; // 1 MIS1
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uint32_t mis2 : 1; // 2 MIS2
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uint32_t mis3 : 1; // 3 MIS3
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uint32_t mis4 : 1; // 4 MIS4
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uint32_t mis5 : 1; // 5 MIS5
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uint32_t mis6 : 1; // 6 MIS6
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uint32_t mis7 : 1; // 7 MIS7
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uint32_t mis8 : 1; // 8 MIS8
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uint32_t mis9 : 1; // 9 MIS9
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uint32_t mis10 : 1; // 10 MIS10
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uint32_t mis11 : 1; // 11 MIS11
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uint32_t mis12 : 1; // 12 MIS12
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uint32_t mis13 : 1; // 13 MIS13
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uint32_t mis14 : 1; // 14 MIS14
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uint32_t mis15 : 1; // 15 MIS15
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_gpdma_smisr_t;
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typedef struct {
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uint32_t reserve0 : 16; // 0 Reserve
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uint32_t lba : 16; // 16 linked-list base address of GPDMA channel x
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} reg_gpdma_lbar_t;
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typedef struct {
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uint32_t reserve0 : 8; // 0 Reserve
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uint32_t tcf : 1; // 8 transfer complete flag clear
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uint32_t htf : 1; // 9 half transfer flag clear
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uint32_t dtef : 1; // 10 data transfer error flag clear
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uint32_t ulef : 1; // 11 update link transfer error flag clear
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uint32_t usef : 1; // 12 user setting error flag clear
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uint32_t suspf : 1; // 13 completed suspension flag clear
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uint32_t tof : 1; // 14 trigger overrun flag clear
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uint32_t reserve1 : 17; // 15 Reserve
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} reg_gpdma_fcr_t;
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typedef struct {
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uint32_t idlef : 1; // 0 idle flag This idle flag is de-asserted by hardware when the channel is enabled (GPDMA_CxCR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state).
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uint32_t reserve0 : 7; // 1 Reserve
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uint32_t tcf : 1; // 8 transfer complete flag A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (GPDMA_CxTR2.TCEM[1:0]).
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uint32_t htf : 1; // 9 half transfer flag An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (GPDMA_CxTR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2)) has been transferred to the destination.
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uint32_t dtef : 1; // 10 data transfer error flag
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uint32_t ulef : 1; // 11 update link transfer error flag
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uint32_t usef : 1; // 12 user setting error flag
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uint32_t suspf : 1; // 13 completed suspension flag
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uint32_t tof : 1; // 14 trigger overrun flag
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uint32_t reserve1 : 1; // 15 Reserve
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uint32_t fifol : 8; // 16 monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (see GPDMA_CxTR1.DDW_LOG2[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (GPDMA_CxSR.SUSPF = 1).
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uint32_t reserve2 : 8; // 24 Reserve
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} reg_gpdma_sr_t;
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typedef struct {
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uint32_t en : 1; // 0 enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.
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uint32_t reset : 1; // 1 reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (GPDMA_CxSR.SUSPF = 1 and GPDMA_CxSR.IDLEF = GPDMA_CxCR.EN = 1) - channel in disabled state (GPDMA_CxSR.IDLEF = 1 and GPDMA_CxCR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR) before enabling again the channel (see the programming sequence in ).
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uint32_t susp : 1; // 2 suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in .
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uint32_t reserve0 : 5; // 3 Reserve
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uint32_t tcie : 1; // 8 transfer complete interrupt enable
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uint32_t htie : 1; // 9 half transfer complete interrupt enable
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uint32_t dteie : 1; // 10 data transfer error interrupt enable
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uint32_t uleie : 1; // 11 update link transfer error interrupt enable
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uint32_t useie : 1; // 12 user setting error interrupt enable
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uint32_t suspie : 1; // 13 completed suspension interrupt enable
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uint32_t toie : 1; // 14 trigger overrun interrupt enable
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uint32_t reserve1 : 1; // 15 Reserve
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uint32_t lsm : 1; // 16 Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until GPDMA_CxBR1.BNDT[15:0] = 0 and GPDMA_CxBR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1.
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uint32_t lap : 1; // 17 linked-list allocated port This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1.
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uint32_t reserve2 : 4; // 18 Reserve
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uint32_t prio : 2; // 22 priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
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uint32_t reserve3 : 8; // 24 Reserve
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} reg_gpdma_cr_t;
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typedef struct {
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uint32_t sdw_log2 : 2; // 0 binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (GPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address GPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.
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uint32_t reserve0 : 1; // 2 Reserve
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uint32_t sinc : 1; // 3 source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.
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uint32_t sbl_1 : 6; // 4 source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed.
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uint32_t reserve1 : 1; // 10 Reserve
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uint32_t pam : 2; // 11 padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer - Case 2: If destination data width < source data width 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination Note:
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uint32_t sbx : 1; // 13 source byte exchange within the unaligned half-word of each source word If the source data width is shorter than a word, this bit is ignored. If the source data width is a word:
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uint32_t sap : 1; // 14 source allocated port This bit is used to allocate the master port for the source transfer Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
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uint32_t ssec : 1; // 15 security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx =1 . A secure write is ignored when GPDMA_SECCFGR.SECx = 0. When GPDMA_SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure.
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uint32_t ddw_log2 : 2; // 16 binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0], versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and no transfer is issued.
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uint32_t reserve2 : 1; // 18 Reserve
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uint32_t dinc : 1; // 19 destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.
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uint32_t dbl_1 : 6; // 20 destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed.
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uint32_t dbx : 1; // 26 destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte:
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uint32_t dhx : 1; // 27 destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word:
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uint32_t reserve3 : 2; // 28 Reserve
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uint32_t dap : 1; // 30 destination allocated port This bit is used to allocate the master port for the destination transfer Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
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uint32_t dsec : 1; // 31 security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx = 1. A secure write is ignored when GPDMA_SECCFGR.SECx = 0. When GPDMA_SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure.
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} reg_gpdma_tr1_t;
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typedef struct {
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uint32_t reqsel : 7; // 0 GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active GPDMA channels (GPDMA_CxCR.EN = 1 and GPDMA_CxTR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting.
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uint32_t reserve0 : 2; // 7 Reserve
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uint32_t swreq : 1; // 9 software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted.
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uint32_t dreq : 1; // 10 destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note:
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uint32_t breq : 1; // 11 Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:
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uint32_t reserve1 : 2; // 12 Reserve
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uint32_t trigm : 2; // 14 trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (GPDMA_CxCR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a GPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The GPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (GPDMA_CxSR.TOF =1 ), and an interrupt is generated if enabled (GPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger.
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uint32_t trigsel : 6; // 16 trigger event input selection These bits select the trigger event input of the GPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00.
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uint32_t reserve2 : 2; // 22 Reserve
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uint32_t trigpol : 2; // 24 trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].
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uint32_t reserve3 : 4; // 26 Reserve
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uint32_t tcem : 2; // 30 transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1.
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} reg_gpdma_tr2_t;
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typedef struct {
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uint32_t bndt : 16; // 0 block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if GPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if GPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value. - if all GPDMA_CxLLR.Uxx = 0 and if GPDMA_CxLLR.LA[15:0] = 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if GPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (GPDMA_CxTR1.PAM[1] = 1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued.
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_gpdma_br1_t;
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typedef struct {
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uint32_t sa : 32; // 0 source address This field is the pointer to the address from which the next data is read. During the channel activity, depending on the source addressing mode (GPDMA_CxTR1.SINC), this field is kept fixed or incremented by the data width (GPDMA_CxTR1.SDW_LOG2[1:0]) after each single source data, reflecting the next address from which data is read. During the channel activity, this address is updated after each completed source burst, consequently to: the programmed source burst; either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (GPDMA_CxTR1.SINC = 1), then the additional address offset value is the programmed burst size, as defined by GPDMA_CxTR1.SBL_1[5:0] and GPDMA_CxTR1.SDW_LOG2[21:0] the additional source incremented/decremented offset value as programmed by GPDMA_CxBR1.SDEC and GPDMA_CxTR3.SAO[12:0] once/if completed source block transfer, for a channel x with 2D addressing capability (x = 12 to 15). additional block repeat source incremented/decremented offset value as programmed by GPDMA_CxBR1.BRSDEC and GPDMA_CxBR2.BRSAO[15:0] In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by GPDMA from the memory, provided the LLI is set with GPDMA_CxLLR.USA = 1. Note: A source address must be aligned with the programmed data width of a source single (SA[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued. When the source block size is not a multiple of the source burst size and is a multiple of the source data width, the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied.
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} reg_gpdma_sar_t;
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typedef struct {
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uint32_t da : 32; // 0 destination address This field is the pointer to the address from which the next data is written. During the channel activity, depending on the destination addressing mode (GPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (GPDMA_CxTR1.DDW_LOG2[21:0]) after each single destination data, reflecting the next address from which data is written. During the channel activity, this address is updated after each completed destination burst, consequently to: the programmed destination burst; either in fixed addressing mode or in contiguous-data incremented mode. If contiguously incremented (GPDMA_CxTR1.DINC = 1), then the additional address offset value is the programmed burst size, as defined by GPDMA_CxTR1.DBL_1[5:0] and GPDMA_CxTR1.DDW_LOG2[1:0] the additional destination incremented/decremented offset value as programmed by GPDMA_CxBR1.DDEC and GPDMA_CxTR3.DAO[12:0] once/if completed destination block transfer, for a channel x with 2D addressing capability (x = 12 to 15), the additional block repeat destination incremented/decremented offset value as programmed by GPDMA_CxBR1.BRDDEC and GPDMA_CxBR2.BRDAO[15:0] In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by the GPDMA from the memory, provided the LLI is set with GPDMA_CxLLR.UDA = 1. Note: A destination address must be aligned with the programmed data width of a destination burst (DA[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
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} reg_gpdma_dar_t;
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typedef struct {
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uint32_t reserve0 : 2; // 0 Reserve
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uint32_t la : 14; // 2 pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.
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uint32_t ull : 1; // 16 Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer.
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uint32_t reserve1 : 10; // 17 Reserve
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uint32_t uda : 1; // 27 Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer.
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uint32_t usa : 1; // 28 update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer.
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uint32_t ub1 : 1; // 29 Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during the link transfer. If UB1 = 0 and if GPDMA_CxLLR ≠ 0, the linked-list is not completed. GPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer.
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uint32_t ut2 : 1; // 30 Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer.
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uint32_t ut1 : 1; // 31 Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer.
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} reg_gpdma_llr_t;
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typedef struct {
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volatile reg_gpdma_lbar_t lbar;
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volatile uint32_t reserve1[2];
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volatile reg_gpdma_fcr_t fcr;
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volatile reg_gpdma_sr_t sr;
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volatile reg_gpdma_cr_t cr;
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volatile uint32_t reserve2[10];
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volatile reg_gpdma_tr1_t tr1;
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volatile reg_gpdma_tr2_t tr2;
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volatile reg_gpdma_br1_t br1;
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volatile reg_gpdma_sar_t sar;
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volatile reg_gpdma_dar_t dar;
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volatile uint32_t reserve3[10];
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volatile reg_gpdma_llr_t llr;
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} reg_gpdma_ch_t;
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typedef struct {
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volatile reg_gpdma_seccfgr_t seccfgr;
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volatile reg_gpdma_privcfgr_t privcfgr;
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volatile reg_gpdma_rcfglockr_t rcfglockr;
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volatile reg_gpdma_misr_t misr;
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volatile reg_gpdma_smisr_t smisr;
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} reg_gpdma_t;
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