79 lines
3.1 KiB
C
Executable File
79 lines
3.1 KiB
C
Executable File
#ifndef LL_RCC_H
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#define LL_RCC_H
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#include <stm32u5xx.h>
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/// @brief enable clock for the given timer
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/// @param[in] tim: timer instance
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static inline void rcc_enable_timer_clock(TIM_TypeDef *tim) {
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if (tim == TIM1) SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);
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else if (tim == TIM2) SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN);
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else if (tim == TIM3) SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN);
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}
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/// @brief enable clock for the given uart
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/// @param[in] uart: uart instance
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static inline void rcc_enable_uart_clock(USART_TypeDef *uart) {
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if (uart == USART1) SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);
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else if (uart == USART2) SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN);
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else if (uart == USART3) SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN);
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else if (uart == UART4) SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN);
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else if (uart == UART5) SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN);
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}
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static inline void rcc_enable_adc_clock(ADC_TypeDef *adc) {
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if (adc == ADC1) RCC->AHB2ENR1 |= RCC_AHB2ENR1_ADC12EN;
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}
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typedef enum {
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PCLK1, ///< Peripheral clock 1 (APB1)
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SYSCLK, ///< System clock
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HSI16, ///< Internal 16 MHz RC oscillator
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MSIK, ///< Internal MSI clock
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} I2C_CLOCKS; ///< I2C clock sources source
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/// @brief enable and select clock for I2C module
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/// @param[in] i2c: I2C module - I2C1, I2C2, I2C3
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/// @param[in] clock: clock source: PCLK1, SYSCLK, HSI16, MSIK
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static inline void rcc_enable_i2c_clock(I2C_TypeDef *i2c,
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I2C_CLOCKS clock) {
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if (i2c == I2C1) {
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SET_BIT(RCC->CCIPR1, clock << RCC_CCIPR1_I2C1SEL_Pos);
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SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN);
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} else if (i2c == I2C2) {
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SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN);
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SET_BIT(RCC->CCIPR1, clock << RCC_CCIPR1_I2C2SEL_Pos);
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} else if (i2c == I2C3) {
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SET_BIT(RCC->CCIPR3, clock << RCC_CCIPR3_I2C3SEL_Pos);
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SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN);
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}
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}
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/// @brief enable dma clock
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/// @param[in] dma: dma instance
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static inline void rcc_enable_dma_clock(DMA_TypeDef *dma) {
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if (dma == GPDMA1) SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN);
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}
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/// @brief enable clock for the given dcmi
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/// @param[in] dcmi: dcmi instance
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static inline void rcc_enable_dcmi_clock(DCMI_TypeDef *dcmi) {
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if (dcmi == DCMI) SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN);
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}
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/// @brief enable clock for the given port
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/// @param[in] gpio: port instance
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static inline void rcc_enable_gpio_clock(GPIO_TypeDef *gpio) {
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if (gpio == GPIOA) SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN);
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else if (gpio == GPIOB) SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN);
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else if (gpio == GPIOC) SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN);
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else if (gpio == GPIOD) SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN);
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else if (gpio == GPIOE) SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN);
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else if (gpio == GPIOF) SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN);
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else if (gpio == GPIOG) {
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SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN);
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SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
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}
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}
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#endif //LL_RCC_H
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