111 lines
3.7 KiB
C
Executable File
111 lines
3.7 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t syscfgsec : 1; // 0 SYSCFG clock control security
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uint32_t classbsec : 1; // 1 CLASSBSEC
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uint32_t reserve0 : 1; // 2 Reserve
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uint32_t fpusec : 1; // 3 FPUSEC
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uint32_t reserve1 : 28; // 4 Reserve
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} reg_syscfg_seccfgr_t;
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typedef struct {
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uint32_t reserve0 : 8; // 0 Reserve
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uint32_t boosten : 1; // 8 I/O analog switch voltage booster enable
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uint32_t anaswvdd : 1; // 9 GPIO analog switch control voltage selection
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uint32_t reserve1 : 6; // 10 Reserve
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uint32_t pb6_fmp : 1; // 16 PB6_FMP
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uint32_t pb7_fmp : 1; // 17 PB7_FMP
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uint32_t pb8_fmp : 1; // 18 PB8_FMP
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uint32_t pb9_fmp : 1; // 19 PB9_FMP
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uint32_t reserve2 : 12; // 20 Reserve
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} reg_syscfg_cfgr1_t;
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typedef struct {
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uint32_t fpu_ie : 6; // 0 Floating point unit interrupts enable bits
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uint32_t reserve0 : 26; // 6 Reserve
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} reg_syscfg_fpuimr_t;
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typedef struct {
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uint32_t locknsvtor: 1; // 0 VTOR_NS register lock
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uint32_t locknsmpu : 1; // 1 Non-secure MPU registers lock
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uint32_t reserve0 : 30; // 2 Reserve
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} reg_syscfg_cnslckr_t;
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typedef struct {
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uint32_t locksvtaircr: 1; // 0 LOCKSVTAIRCR
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uint32_t locksmpu : 1; // 1 LOCKSMPU
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uint32_t locksau : 1; // 2 LOCKSAU
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uint32_t reserve0 : 29; // 3 Reserve
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} reg_syscfg_cslockr_t;
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typedef struct {
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uint32_t cll : 1; // 0 LOCKUP (hardfault) output enable bit
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uint32_t spl : 1; // 1 SRAM ECC lock bit
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uint32_t pvdl : 1; // 2 PVD lock enable bit
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uint32_t eccl : 1; // 3 ECC Lock
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uint32_t reserve0 : 28; // 4 Reserve
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} reg_syscfg_cfgr2_t;
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typedef struct {
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uint32_t mclr : 1; // 0 MCLR
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uint32_t reserve0 : 15; // 1 Reserve
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uint32_t ipmee : 1; // 16 IPMEE
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uint32_t reserve1 : 15; // 17 Reserve
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} reg_syscfg_mesr_t;
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typedef struct {
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uint32_t en1 : 1; // 0 EN1
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uint32_t cs1 : 1; // 1 CS1
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uint32_t en2 : 1; // 2 EN2
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uint32_t cs2 : 1; // 3 CS2
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uint32_t reserve0 : 4; // 4 Reserve
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uint32_t rdy1 : 1; // 8 RDY1
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uint32_t rdy2 : 1; // 9 RDY2
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uint32_t reserve1 : 22; // 10 Reserve
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} reg_syscfg_cccsr_t;
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typedef struct {
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uint32_t ncv1 : 4; // 0 NCV1
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uint32_t pcv1 : 4; // 4 PCV1
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uint32_t ncv2 : 4; // 8 NCV2
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uint32_t pcv2 : 4; // 12 PCV2
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_syscfg_ccvr_t;
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typedef struct {
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uint32_t ncc1 : 4; // 0 NCC1
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uint32_t pcc1 : 4; // 4 PCC1
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uint32_t ncc2 : 4; // 8 NCC2
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uint32_t pcc2 : 4; // 12 PCC2
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_syscfg_cccr_t;
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typedef struct {
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uint32_t rsscmd : 16; // 0 RSS commands
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_syscfg_rsscmdr_t;
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typedef struct {
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uint32_t cc1enrxfilter: 1; // 0 CC1ENRXFILTER
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uint32_t cc2enrxfilter: 1; // 1 CC2ENRXFILTER
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uint32_t reserve0 : 30; // 2 Reserve
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} reg_syscfg_ucpdr_t;
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typedef struct {
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volatile reg_syscfg_seccfgr_t seccfgr;
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volatile reg_syscfg_cfgr1_t cfgr1;
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volatile reg_syscfg_fpuimr_t fpuimr;
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volatile reg_syscfg_cnslckr_t cnslckr;
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volatile reg_syscfg_cslockr_t cslockr;
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volatile reg_syscfg_cfgr2_t cfgr2;
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volatile reg_syscfg_mesr_t mesr;
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volatile reg_syscfg_cccsr_t cccsr;
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volatile reg_syscfg_ccvr_t ccvr;
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volatile reg_syscfg_cccr_t cccr;
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volatile uint32_t reserve0[1];
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volatile reg_syscfg_rsscmdr_t rsscmdr;
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volatile uint32_t reserve1[16];
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volatile reg_syscfg_ucpdr_t ucpdr;
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} reg_syscfg_t;
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