271 lines
14 KiB
C
Executable File
271 lines
14 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t mbken : 1; // 0 Memory bank enable bit
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uint32_t muxen : 1; // 1 Address/data multiplexing enable bit
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uint32_t mtyp : 2; // 2 Memory type
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uint32_t mwid : 2; // 4 Memory data bus width
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uint32_t faccen : 1; // 6 Flash access enable
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uint32_t reserve0 : 1; // 7 Reserve
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uint32_t bursten : 1; // 8 Burst enable bit
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uint32_t waitpol : 1; // 9 Wait signal polarity bit
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uint32_t reserve1 : 1; // 10 Reserve
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uint32_t waitcfg : 1; // 11 Wait timing configuration
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uint32_t wren : 1; // 12 Write enable bit
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uint32_t waiten : 1; // 13 Wait enable bit
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uint32_t extmod : 1; // 14 Extended mode enable
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uint32_t asyncwait : 1; // 15 Wait signal during asynchronous transfers
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uint32_t cpsize : 3; // 16 CRAM Page Size
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uint32_t cburstrw : 1; // 19 Write burst enable
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uint32_t cclken : 1; // 20 Continuous clock enable
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uint32_t wfdis : 1; // 21 Write FIFO disable
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uint32_t nblset : 2; // 22 Byte lane (NBL) setup
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uint32_t reserve2 : 7; // 24 Reserve
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uint32_t fmcen : 1; // 31 FMC controller enable
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} reg_sec_fmc_bcr1_t;
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typedef struct {
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uint32_t mbken : 1; // 0 Memory bank enable bit
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uint32_t muxen : 1; // 1 Address/data multiplexing enable bit
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uint32_t mtyp : 2; // 2 Memory type
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uint32_t mwid : 2; // 4 Memory data bus width
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uint32_t faccen : 1; // 6 Flash access enable
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uint32_t reserve0 : 1; // 7 Reserve
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uint32_t bursten : 1; // 8 Burst enable bit
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uint32_t waitpol : 1; // 9 Wait signal polarity bit
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uint32_t reserve1 : 1; // 10 Reserve
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uint32_t waitcfg : 1; // 11 Wait timing configuration
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uint32_t wren : 1; // 12 Write enable bit
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uint32_t waiten : 1; // 13 Wait enable bit
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uint32_t extmod : 1; // 14 Extended mode enable
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uint32_t asyncwait : 1; // 15 Wait signal during asynchronous transfers
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uint32_t cpsize : 3; // 16 CRAM Page Size
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uint32_t cburstrw : 1; // 19 Write burst enable
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uint32_t cclken : 1; // 20 Continuous clock enable
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uint32_t wfdis : 1; // 21 Write FIFO disable
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uint32_t nblset : 2; // 22 Byte lane (NBL) setup
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uint32_t reserve2 : 7; // 24 Reserve
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uint32_t fmcen : 1; // 31 FMC controller enable
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} reg_sec_fmc_bcr2_t;
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typedef struct {
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uint32_t mbken : 1; // 0 Memory bank enable bit
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uint32_t muxen : 1; // 1 Address/data multiplexing enable bit
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uint32_t mtyp : 2; // 2 Memory type
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uint32_t mwid : 2; // 4 Memory data bus width
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uint32_t faccen : 1; // 6 Flash access enable
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uint32_t reserve0 : 1; // 7 Reserve
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uint32_t bursten : 1; // 8 Burst enable bit
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uint32_t waitpol : 1; // 9 Wait signal polarity bit
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uint32_t reserve1 : 1; // 10 Reserve
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uint32_t waitcfg : 1; // 11 Wait timing configuration
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uint32_t wren : 1; // 12 Write enable bit
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uint32_t waiten : 1; // 13 Wait enable bit
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uint32_t extmod : 1; // 14 Extended mode enable
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uint32_t asyncwait : 1; // 15 Wait signal during asynchronous transfers
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uint32_t cpsize : 3; // 16 CRAM Page Size
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uint32_t cburstrw : 1; // 19 Write burst enable
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uint32_t cclken : 1; // 20 Continuous clock enable
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uint32_t wfdis : 1; // 21 Write FIFO disable
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uint32_t nblset : 2; // 22 Byte lane (NBL) setup
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uint32_t reserve2 : 7; // 24 Reserve
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uint32_t fmcen : 1; // 31 FMC controller enable
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} reg_sec_fmc_bcr3_t;
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typedef struct {
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uint32_t mbken : 1; // 0 Memory bank enable bit
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uint32_t muxen : 1; // 1 Address/data multiplexing enable bit
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uint32_t mtyp : 2; // 2 Memory type
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uint32_t mwid : 2; // 4 Memory data bus width
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uint32_t faccen : 1; // 6 Flash access enable
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uint32_t reserve0 : 1; // 7 Reserve
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uint32_t bursten : 1; // 8 Burst enable bit
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uint32_t waitpol : 1; // 9 Wait signal polarity bit
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uint32_t reserve1 : 1; // 10 Reserve
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uint32_t waitcfg : 1; // 11 Wait timing configuration
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uint32_t wren : 1; // 12 Write enable bit
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uint32_t waiten : 1; // 13 Wait enable bit
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uint32_t extmod : 1; // 14 Extended mode enable
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uint32_t asyncwait : 1; // 15 Wait signal during asynchronous transfers
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uint32_t cpsize : 3; // 16 CRAM Page Size
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uint32_t cburstrw : 1; // 19 Write burst enable
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uint32_t cclken : 1; // 20 Continuous clock enable
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uint32_t wfdis : 1; // 21 Write FIFO disable
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uint32_t nblset : 2; // 22 Byte lane (NBL) setup
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uint32_t reserve2 : 7; // 24 Reserve
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uint32_t fmcen : 1; // 31 FMC controller enable
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} reg_sec_fmc_bcr4_t;
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typedef struct {
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uint32_t addset : 4; // 0 Address setup phase duration
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uint32_t addhld : 4; // 4 Address-hold phase duration
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uint32_t datast : 8; // 8 Data-phase duration
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uint32_t busturn : 4; // 16 Bus turnaround phase duration
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uint32_t clkdiv : 4; // 20 Clock divide ratio (for FMC_CLK signal)
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uint32_t datlat : 4; // 24 Data latency for synchronous memory
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uint32_t accmod : 2; // 28 Access mode
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uint32_t datahld : 2; // 30 Data hold phase duration
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} reg_sec_fmc_btr1_t;
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typedef struct {
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uint32_t addset : 4; // 0 Address setup phase duration
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uint32_t addhld : 4; // 4 Address-hold phase duration
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uint32_t datast : 8; // 8 Data-phase duration
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uint32_t busturn : 4; // 16 Bus turnaround phase duration
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uint32_t clkdiv : 4; // 20 Clock divide ratio (for FMC_CLK signal)
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uint32_t datlat : 4; // 24 Data latency for synchronous memory
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uint32_t accmod : 2; // 28 Access mode
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uint32_t datahld : 2; // 30 Data hold phase duration
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} reg_sec_fmc_btr2_t;
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typedef struct {
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uint32_t addset : 4; // 0 Address setup phase duration
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uint32_t addhld : 4; // 4 Address-hold phase duration
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uint32_t datast : 8; // 8 Data-phase duration
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uint32_t busturn : 4; // 16 Bus turnaround phase duration
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uint32_t clkdiv : 4; // 20 Clock divide ratio (for FMC_CLK signal)
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uint32_t datlat : 4; // 24 Data latency for synchronous memory
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uint32_t accmod : 2; // 28 Access mode
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uint32_t datahld : 2; // 30 Data hold phase duration
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} reg_sec_fmc_btr3_t;
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typedef struct {
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uint32_t addset : 4; // 0 Address setup phase duration
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uint32_t addhld : 4; // 4 Address-hold phase duration
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uint32_t datast : 8; // 8 Data-phase duration
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uint32_t busturn : 4; // 16 Bus turnaround phase duration
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uint32_t clkdiv : 4; // 20 Clock divide ratio (for FMC_CLK signal)
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uint32_t datlat : 4; // 24 Data latency for synchronous memory
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uint32_t accmod : 2; // 28 Access mode
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uint32_t datahld : 2; // 30 Data hold phase duration
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} reg_sec_fmc_btr4_t;
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typedef struct {
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uint32_t addset : 4; // 0 Address setup phase duration
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uint32_t addhld : 4; // 4 Address-hold phase duration
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uint32_t datast : 8; // 8 Data-phase duration
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uint32_t busturn : 4; // 16 Bus turnaround phase duration
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uint32_t reserve0 : 8; // 20 Reserve
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uint32_t accmod : 2; // 28 Access mode
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uint32_t datahld : 2; // 30 Data hold phase duration
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} reg_sec_fmc_bwtr1_t;
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typedef struct {
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uint32_t addset : 4; // 0 Address setup phase duration
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uint32_t addhld : 4; // 4 Address-hold phase duration
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uint32_t datast : 8; // 8 Data-phase duration
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uint32_t busturn : 4; // 16 Bus turnaround phase duration
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uint32_t reserve0 : 8; // 20 Reserve
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uint32_t accmod : 2; // 28 Access mode
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uint32_t datahld : 2; // 30 Data hold phase duration
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} reg_sec_fmc_bwtr2_t;
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typedef struct {
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uint32_t addset : 4; // 0 Address setup phase duration
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uint32_t addhld : 4; // 4 Address-hold phase duration
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uint32_t datast : 8; // 8 Data-phase duration
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uint32_t busturn : 4; // 16 Bus turnaround phase duration
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uint32_t reserve0 : 8; // 20 Reserve
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uint32_t accmod : 2; // 28 Access mode
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uint32_t datahld : 2; // 30 Data hold phase duration
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} reg_sec_fmc_bwtr3_t;
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typedef struct {
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uint32_t addset : 4; // 0 Address setup phase duration
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uint32_t addhld : 4; // 4 Address-hold phase duration
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uint32_t datast : 8; // 8 Data-phase duration
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uint32_t busturn : 4; // 16 Bus turnaround phase duration
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uint32_t reserve0 : 8; // 20 Reserve
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uint32_t accmod : 2; // 28 Access mode
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uint32_t datahld : 2; // 30 Data hold phase duration
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} reg_sec_fmc_bwtr4_t;
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typedef struct {
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uint32_t cscount : 16; // 0 Chip select counter
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uint32_t cntb1en : 1; // 16 Counter Bank 1 enable
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uint32_t cntb2en : 1; // 17 Counter Bank 2 enable
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uint32_t cntb3en : 1; // 18 Counter Bank 3 enable
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uint32_t cntb4en : 1; // 19 Counter Bank 4 enable
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uint32_t reserve0 : 12; // 20 Reserve
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} reg_sec_fmc_pcscntr_t;
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typedef struct {
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uint32_t reserve0 : 1; // 0 Reserve
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uint32_t pwaiten : 1; // 1 Wait feature enable bit
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uint32_t pbken : 1; // 2 NAND Flash memory bank enable bit
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uint32_t ptyp : 1; // 3 Memory type
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uint32_t pwid : 2; // 4 Data bus width
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uint32_t eccen : 1; // 6 ECC computation logic enable bit
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uint32_t reserve1 : 2; // 7 Reserve
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uint32_t tclr : 4; // 9 CLE to RE delay
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uint32_t tar : 3; // 13 ALE to RE delay
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uint32_t reserve2 : 1; // 16 Reserve
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uint32_t eccps : 3; // 17 ECC page size
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uint32_t reserve3 : 12; // 20 Reserve
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} reg_sec_fmc_pcr_t;
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typedef struct {
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uint32_t irs : 1; // 0 Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set.
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uint32_t ils : 1; // 1 Interrupt high-level status The flag is set by hardware and reset by software.
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uint32_t ifs : 1; // 2 Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set.
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uint32_t iren : 1; // 3 Interrupt rising edge detection enable bit
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uint32_t ilen : 1; // 4 Interrupt high-level detection enable bit
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uint32_t ifen : 1; // 5 Interrupt falling edge detection enable bit
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uint32_t fempt : 1; // 6 FIFO empty. Read-only bit that provides the status of the FIFO
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uint32_t reserve0 : 25; // 7 Reserve
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} reg_sec_fmc_sr_t;
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typedef struct {
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uint32_t memset : 8; // 0 Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space:
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uint32_t memwait : 8; // 8 Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:
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uint32_t memhold : 8; // 16 Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space:
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uint32_t memhiz : 8; // 24 Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions:
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} reg_sec_fmc_pmem_t;
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typedef struct {
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uint32_t attset : 8; // 0 Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:
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uint32_t attwait : 8; // 8 Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:
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uint32_t atthold : 8; // 16 Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:
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uint32_t atthiz : 8; // 24 Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction:
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} reg_sec_fmc_patt_t;
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typedef struct {
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uint32_t ecc : 32; // 0 ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields.
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} reg_sec_fmc_eccr_t;
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typedef struct {
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volatile reg_sec_fmc_bcr1_t bcr1;
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volatile uint32_t reserve0[1];
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volatile reg_sec_fmc_bcr2_t bcr2;
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volatile uint32_t reserve1[1];
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volatile reg_sec_fmc_bcr3_t bcr3;
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volatile uint32_t reserve2[1];
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volatile reg_sec_fmc_bcr4_t bcr4;
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volatile uint32_t reserve3[-6];
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volatile reg_sec_fmc_btr1_t btr1;
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volatile uint32_t reserve4[1];
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volatile reg_sec_fmc_btr2_t btr2;
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volatile uint32_t reserve5[1];
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volatile reg_sec_fmc_btr3_t btr3;
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volatile uint32_t reserve6[1];
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volatile reg_sec_fmc_btr4_t btr4;
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volatile uint32_t reserve7[57];
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volatile reg_sec_fmc_bwtr1_t bwtr1;
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volatile uint32_t reserve8[1];
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volatile reg_sec_fmc_bwtr2_t bwtr2;
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volatile uint32_t reserve9[1];
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volatile reg_sec_fmc_bwtr3_t bwtr3;
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volatile uint32_t reserve10[1];
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volatile reg_sec_fmc_bwtr4_t bwtr4;
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volatile uint32_t reserve11[-64];
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volatile reg_sec_fmc_pcscntr_t pcscntr;
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volatile uint32_t reserve12[23];
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volatile reg_sec_fmc_pcr_t pcr;
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volatile reg_sec_fmc_sr_t sr;
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volatile reg_sec_fmc_pmem_t pmem;
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volatile reg_sec_fmc_patt_t patt;
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volatile uint32_t reserve13[1];
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volatile reg_sec_fmc_eccr_t eccr;
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} reg_sec_fmc_t;
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