223 lines
8.2 KiB
C
Executable File
223 lines
8.2 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t start : 1; // 0 Start
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uint32_t susp : 1; // 1 Suspend
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uint32_t abort : 1; // 2 Abort
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uint32_t reserve0 : 3; // 3 Reserve
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uint32_t lom : 1; // 6 Line Offset Mode
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uint32_t reserve1 : 1; // 7 Reserve
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uint32_t teie : 1; // 8 Transfer error interrupt enable
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uint32_t tcie : 1; // 9 Transfer complete interrupt enable
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uint32_t twie : 1; // 10 Transfer watermark interrupt enable
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uint32_t caeie : 1; // 11 CLUT access error interrupt enable
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uint32_t ctcie : 1; // 12 CLUT transfer complete interrupt enable
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uint32_t ceie : 1; // 13 Configuration Error Interrupt Enable
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uint32_t reserve2 : 2; // 14 Reserve
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uint32_t mode : 2; // 16 DMA2D mode
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uint32_t reserve3 : 14; // 18 Reserve
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} reg_sec_dma2d_cr_t;
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typedef struct {
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uint32_t teif : 1; // 0 Transfer error interrupt flag
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uint32_t tcif : 1; // 1 Transfer complete interrupt flag
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uint32_t twif : 1; // 2 Transfer watermark interrupt flag
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uint32_t caeif : 1; // 3 CLUT access error interrupt flag
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uint32_t ctcif : 1; // 4 CLUT transfer complete interrupt flag
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uint32_t ceif : 1; // 5 Configuration error interrupt flag
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uint32_t reserve0 : 26; // 6 Reserve
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} reg_sec_dma2d_isr_t;
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typedef struct {
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uint32_t cteif : 1; // 0 Clear Transfer error interrupt flag
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uint32_t ctcif : 1; // 1 Clear transfer complete interrupt flag
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uint32_t ctwif : 1; // 2 Clear transfer watermark interrupt flag
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uint32_t caecif : 1; // 3 Clear CLUT access error interrupt flag
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uint32_t cctcif : 1; // 4 Clear CLUT transfer complete interrupt flag
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uint32_t cceif : 1; // 5 Clear configuration error interrupt flag
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uint32_t reserve0 : 26; // 6 Reserve
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} reg_sec_dma2d_ifcr_t;
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typedef struct {
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uint32_t ma : 32; // 0 Memory address
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} reg_sec_dma2d_fgmar_t;
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typedef struct {
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uint32_t lo : 16; // 0 Line offset
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_sec_dma2d_fgor_t;
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typedef struct {
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uint32_t ma : 32; // 0 Memory address
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} reg_sec_dma2d_bgmar_t;
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typedef struct {
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uint32_t lo : 16; // 0 Line offset
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_sec_dma2d_bgor_t;
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typedef struct {
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uint32_t cm : 4; // 0 Color mode
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uint32_t ccm : 1; // 4 CLUT color mode
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uint32_t start : 1; // 5 Start
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uint32_t reserve0 : 2; // 6 Reserve
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uint32_t cs : 8; // 8 CLUT size
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uint32_t am : 2; // 16 Alpha mode
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uint32_t reserve1 : 2; // 18 Reserve
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uint32_t ai : 1; // 20 Alpha Inverted
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uint32_t rbs : 1; // 21 Red Blue Swap
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uint32_t reserve2 : 2; // 22 Reserve
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uint32_t alpha : 8; // 24 Alpha value
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} reg_sec_dma2d_fgpfccr_t;
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typedef struct {
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uint32_t blue : 8; // 0 Blue Value
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uint32_t green : 8; // 8 Green Value
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uint32_t red : 8; // 16 Red Value
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uint32_t reserve0 : 8; // 24 Reserve
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} reg_sec_dma2d_fgcolr_t;
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typedef struct {
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uint32_t cm : 4; // 0 Color mode
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uint32_t ccm : 1; // 4 CLUT Color mode
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uint32_t start : 1; // 5 Start
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uint32_t reserve0 : 2; // 6 Reserve
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uint32_t cs : 8; // 8 CLUT size
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uint32_t am : 2; // 16 Alpha mode
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uint32_t reserve1 : 2; // 18 Reserve
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uint32_t ai : 1; // 20 Alpha Inverted
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uint32_t rbs : 1; // 21 Red Blue Swap
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uint32_t reserve2 : 2; // 22 Reserve
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uint32_t alpha : 8; // 24 Alpha value
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} reg_sec_dma2d_bgpfccr_t;
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typedef struct {
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uint32_t blue : 8; // 0 Blue Value
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uint32_t green : 8; // 8 Green Value
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uint32_t red : 8; // 16 Red Value
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uint32_t reserve0 : 8; // 24 Reserve
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} reg_sec_dma2d_bgcolr_t;
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typedef struct {
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uint32_t ma : 32; // 0 Memory Address
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} reg_sec_dma2d_fgcmar_t;
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typedef struct {
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uint32_t ma : 32; // 0 Memory address
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} reg_sec_dma2d_bgcmar_t;
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typedef struct {
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uint32_t cm : 3; // 0 Color mode
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uint32_t reserve0 : 6; // 3 Reserve
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uint32_t sb : 1; // 9 Swap Bytes
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uint32_t reserve1 : 10; // 10 Reserve
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uint32_t ai : 1; // 20 Alpha Inverted
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uint32_t rbs : 1; // 21 Red Blue Swap
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uint32_t reserve2 : 10; // 22 Reserve
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} reg_sec_dma2d_opfccr_t;
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typedef struct {
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uint32_t blue : 8; // 0 Blue Value
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uint32_t green : 8; // 8 Green Value
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uint32_t red : 8; // 16 Red Value
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uint32_t aplha : 8; // 24 Alpha Channel Value
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} reg_sec_dma2d_ocolr_rgb888_t;
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typedef struct {
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uint32_t blue : 5; // 0 Blue value in RGB565 mode
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uint32_t green : 6; // 5 Green value in RGB565 mode
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uint32_t red : 5; // 11 Red value in RGB565 mode
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_sec_dma2d_ocolr_rgb565_t;
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typedef struct {
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uint32_t blue : 5; // 0 Blue value in ARGB1555 mode
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uint32_t green : 5; // 5 Green value in ARGB1555 mode
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uint32_t red : 5; // 10 Red value in ARGB1555 mode
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uint32_t a : 1; // 15 Alpha channel value in ARGB1555 mode
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_sec_dma2d_ocolr_argb1555_t;
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typedef struct {
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uint32_t blue : 4; // 0 Blue value in ARGB4444 mode
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uint32_t green : 4; // 4 Green value in ARGB4444 mode
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uint32_t red : 4; // 8 Red value in ARGB4444 mode
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uint32_t alpha : 4; // 12 Alpha channel value in ARGB4444
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_sec_dma2d_ocolr_argb4444_t;
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typedef struct {
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uint32_t ma : 32; // 0 Memory Address
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} reg_sec_dma2d_omar_t;
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typedef struct {
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uint32_t lo : 16; // 0 Line Offset
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_sec_dma2d_oor_t;
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typedef struct {
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uint32_t nl : 16; // 0 Number of lines
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uint32_t pl : 14; // 16 Pixel per lines
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uint32_t reserve0 : 2; // 30 Reserve
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} reg_sec_dma2d_nlr_t;
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typedef struct {
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uint32_t lw : 16; // 0 Line watermark
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_sec_dma2d_lwr_t;
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typedef struct {
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uint32_t en : 1; // 0 Enable
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uint32_t reserve0 : 7; // 1 Reserve
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uint32_t dt : 8; // 8 Dead Time
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uint32_t reserve1 : 16; // 16 Reserve
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} reg_sec_dma2d_amtcr_t;
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typedef struct {
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uint32_t blue : 8; // 0 BLUE
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uint32_t green : 8; // 8 GREEN
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uint32_t red : 8; // 16 RED
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uint32_t aplha : 8; // 24 APLHA
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} reg_sec_dma2d_fgclut_t;
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typedef struct {
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uint32_t blue : 8; // 0 BLUE
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uint32_t green : 8; // 8 GREEN
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uint32_t red : 8; // 16 RED
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uint32_t aplha : 8; // 24 APLHA
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} reg_sec_dma2d_bgclut_t;
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typedef struct {
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volatile reg_sec_dma2d_cr_t cr;
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volatile reg_sec_dma2d_isr_t isr;
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volatile reg_sec_dma2d_ifcr_t ifcr;
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volatile reg_sec_dma2d_fgmar_t fgmar;
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volatile reg_sec_dma2d_fgor_t fgor;
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volatile reg_sec_dma2d_bgmar_t bgmar;
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volatile reg_sec_dma2d_bgor_t bgor;
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volatile reg_sec_dma2d_fgpfccr_t fgpfccr;
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volatile reg_sec_dma2d_fgcolr_t fgcolr;
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volatile reg_sec_dma2d_bgpfccr_t bgpfccr;
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volatile reg_sec_dma2d_bgcolr_t bgcolr;
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volatile reg_sec_dma2d_fgcmar_t fgcmar;
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volatile reg_sec_dma2d_bgcmar_t bgcmar;
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volatile reg_sec_dma2d_opfccr_t opfccr;
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volatile reg_sec_dma2d_ocolr_rgb888_t ocolr_rgb888;
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volatile uint32_t reserve0[-1];
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volatile reg_sec_dma2d_ocolr_rgb565_t ocolr_rgb565;
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volatile uint32_t reserve1[-1];
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volatile reg_sec_dma2d_ocolr_argb1555_t ocolr_argb1555;
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volatile uint32_t reserve2[-1];
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volatile reg_sec_dma2d_ocolr_argb4444_t ocolr_argb4444;
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volatile reg_sec_dma2d_omar_t omar;
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volatile reg_sec_dma2d_oor_t oor;
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volatile reg_sec_dma2d_nlr_t nlr;
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volatile reg_sec_dma2d_lwr_t lwr;
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volatile reg_sec_dma2d_amtcr_t amtcr;
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volatile uint32_t reserve3[236];
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volatile reg_sec_dma2d_fgclut_t fgclut;
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volatile uint32_t reserve4[255];
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volatile reg_sec_dma2d_bgclut_t bgclut;
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} reg_sec_dma2d_t;
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