260 lines
11 KiB
C
Executable File
260 lines
11 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t syncin : 2; // 0 Synchronization inputs
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uint32_t reserve0 : 2; // 2 Reserve
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uint32_t syncout : 2; // 4 Synchronization outputs
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uint32_t reserve1 : 26; // 6 Reserve
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} reg_sai_gcr_t;
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typedef struct {
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uint32_t mode : 2; // 0 Audio block mode
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uint32_t prtcfg : 2; // 2 Protocol configuration
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uint32_t reserve0 : 1; // 4 Reserve
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uint32_t ds : 3; // 5 Data size
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uint32_t lsbfirst : 1; // 8 Least significant bit first
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uint32_t ckstr : 1; // 9 Clock strobing edge
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uint32_t syncen : 2; // 10 Synchronization enable
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uint32_t mono : 1; // 12 Mono mode
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uint32_t outdriv : 1; // 13 Output drive
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uint32_t reserve1 : 2; // 14 Reserve
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uint32_t saiaen : 1; // 16 Audio block A enable
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uint32_t dmaen : 1; // 17 DMA enable
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uint32_t reserve2 : 1; // 18 Reserve
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uint32_t nodiv : 1; // 19 No divider
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uint32_t mckdiv : 6; // 20 Master clock divider
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uint32_t osr : 1; // 26 OSR
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uint32_t mcken : 1; // 27 MCKEN
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uint32_t reserve3 : 4; // 28 Reserve
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} reg_sai_acr1_t;
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typedef struct {
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uint32_t mode : 2; // 0 Audio block mode
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uint32_t prtcfg : 2; // 2 Protocol configuration
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uint32_t reserve0 : 1; // 4 Reserve
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uint32_t ds : 3; // 5 Data size
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uint32_t lsbfirst : 1; // 8 Least significant bit first
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uint32_t ckstr : 1; // 9 Clock strobing edge
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uint32_t syncen : 2; // 10 Synchronization enable
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uint32_t mono : 1; // 12 Mono mode
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uint32_t outdriv : 1; // 13 Output drive
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uint32_t reserve1 : 2; // 14 Reserve
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uint32_t saiaen : 1; // 16 Audio block A enable
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uint32_t dmaen : 1; // 17 DMA enable
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uint32_t reserve2 : 1; // 18 Reserve
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uint32_t nodiv : 1; // 19 No divider
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uint32_t mckdiv : 6; // 20 Master clock divider
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uint32_t osr : 1; // 26 OSR
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uint32_t mcken : 1; // 27 MCKEN
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uint32_t reserve3 : 4; // 28 Reserve
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} reg_sai_bcr1_t;
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typedef struct {
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uint32_t fth : 3; // 0 FIFO threshold
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uint32_t fflush : 1; // 3 FIFO flush
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uint32_t tris : 1; // 4 Tristate management on data line
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uint32_t mute : 1; // 5 Mute
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uint32_t muteval : 1; // 6 Mute value
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uint32_t mutecn : 6; // 7 Mute counter
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uint32_t cpl : 1; // 13 Complement bit
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uint32_t comp : 2; // 14 Companding mode
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_sai_acr2_t;
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typedef struct {
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uint32_t fth : 3; // 0 FIFO threshold
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uint32_t fflush : 1; // 3 FIFO flush
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uint32_t tris : 1; // 4 Tristate management on data line
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uint32_t mute : 1; // 5 Mute
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uint32_t muteval : 1; // 6 Mute value
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uint32_t mutecn : 6; // 7 Mute counter
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uint32_t cpl : 1; // 13 Complement bit
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uint32_t comp : 2; // 14 Companding mode
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_sai_bcr2_t;
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typedef struct {
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uint32_t frl : 8; // 0 Frame length
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uint32_t fsall : 7; // 8 Frame synchronization active level length
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uint32_t reserve0 : 1; // 15 Reserve
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uint32_t fsdef : 1; // 16 Frame synchronization definition
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uint32_t fspol : 1; // 17 Frame synchronization polarity
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uint32_t fsoff : 1; // 18 Frame synchronization offset
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uint32_t reserve1 : 13; // 19 Reserve
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} reg_sai_afrcr_t;
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typedef struct {
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uint32_t frl : 8; // 0 Frame length
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uint32_t fsall : 7; // 8 Frame synchronization active level length
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uint32_t reserve0 : 1; // 15 Reserve
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uint32_t fsdef : 1; // 16 Frame synchronization definition
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uint32_t fspol : 1; // 17 Frame synchronization polarity
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uint32_t fsoff : 1; // 18 Frame synchronization offset
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uint32_t reserve1 : 13; // 19 Reserve
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} reg_sai_bfrcr_t;
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typedef struct {
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uint32_t fboff : 5; // 0 First bit offset
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uint32_t reserve0 : 1; // 5 Reserve
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uint32_t slotsz : 2; // 6 Slot size
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uint32_t nbslot : 4; // 8 Number of slots in an audio frame
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uint32_t reserve1 : 4; // 12 Reserve
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uint32_t sloten : 16; // 16 Slot enable
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} reg_sai_aslotr_t;
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typedef struct {
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uint32_t fboff : 5; // 0 First bit offset
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uint32_t reserve0 : 1; // 5 Reserve
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uint32_t slotsz : 2; // 6 Slot size
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uint32_t nbslot : 4; // 8 Number of slots in an audio frame
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uint32_t reserve1 : 4; // 12 Reserve
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uint32_t sloten : 16; // 16 Slot enable
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} reg_sai_bslotr_t;
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typedef struct {
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uint32_t ovrudrie : 1; // 0 Overrun/underrun interrupt enable
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uint32_t mutedetie : 1; // 1 Mute detection interrupt enable
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uint32_t wckcfgie : 1; // 2 Wrong clock configuration interrupt enable
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uint32_t freqie : 1; // 3 FIFO request interrupt enable
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uint32_t cnrdyie : 1; // 4 Codec not ready interrupt enable
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uint32_t afsdetie : 1; // 5 Anticipated frame synchronization detection interrupt enable
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uint32_t lfsdetie : 1; // 6 Late frame synchronization detection interrupt enable
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uint32_t reserve0 : 25; // 7 Reserve
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} reg_sai_aim_t;
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typedef struct {
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uint32_t ovrudrie : 1; // 0 Overrun/underrun interrupt enable
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uint32_t mutedetie : 1; // 1 Mute detection interrupt enable
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uint32_t wckcfgie : 1; // 2 Wrong clock configuration interrupt enable
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uint32_t freqie : 1; // 3 FIFO request interrupt enable
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uint32_t cnrdyie : 1; // 4 Codec not ready interrupt enable
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uint32_t afsdetie : 1; // 5 Anticipated frame synchronization detection interrupt enable
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uint32_t lfsdetie : 1; // 6 Late frame synchronization detection interrupt enable
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uint32_t reserve0 : 25; // 7 Reserve
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} reg_sai_bim_t;
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typedef struct {
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uint32_t ovrudr : 1; // 0 Overrun / underrun
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uint32_t mutedet : 1; // 1 Mute detection
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uint32_t wckcfg : 1; // 2 Wrong clock configuration flag. This bit is read only
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uint32_t freq : 1; // 3 FIFO request
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uint32_t cnrdy : 1; // 4 Codec not ready
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uint32_t afsdet : 1; // 5 Anticipated frame synchronization detection
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uint32_t lfsdet : 1; // 6 Late frame synchronization detection
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uint32_t reserve0 : 9; // 7 Reserve
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uint32_t flvl : 3; // 16 FIFO level threshold
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uint32_t reserve1 : 13; // 19 Reserve
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} reg_sai_asr_t;
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typedef struct {
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uint32_t ovrudr : 1; // 0 Overrun / underrun
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uint32_t mutedet : 1; // 1 Mute detection
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uint32_t wckcfg : 1; // 2 Wrong clock configuration flag
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uint32_t freq : 1; // 3 FIFO request
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uint32_t cnrdy : 1; // 4 Codec not ready
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uint32_t afsdet : 1; // 5 Anticipated frame synchronization detection
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uint32_t lfsdet : 1; // 6 Late frame synchronization detection
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uint32_t reserve0 : 9; // 7 Reserve
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uint32_t flvl : 3; // 16 FIFO level threshold
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uint32_t reserve1 : 13; // 19 Reserve
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} reg_sai_bsr_t;
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typedef struct {
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uint32_t covrudr : 1; // 0 Clear overrun / underrun
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uint32_t cmutedet : 1; // 1 Mute detection flag
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uint32_t cwckcfg : 1; // 2 Clear wrong clock configuration flag
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t ccnrdy : 1; // 4 Clear codec not ready flag
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uint32_t cafsdet : 1; // 5 Clear anticipated frame synchronization detection flag
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uint32_t clfsdet : 1; // 6 Clear late frame synchronization detection flag
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uint32_t reserve1 : 25; // 7 Reserve
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} reg_sai_aclrfr_t;
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typedef struct {
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uint32_t covrudr : 1; // 0 Clear overrun / underrun
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uint32_t cmutedet : 1; // 1 Mute detection flag
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uint32_t cwckcfg : 1; // 2 Clear wrong clock configuration flag
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t ccnrdy : 1; // 4 Clear codec not ready flag
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uint32_t cafsdet : 1; // 5 Clear anticipated frame synchronization detection flag
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uint32_t clfsdet : 1; // 6 Clear late frame synchronization detection flag
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uint32_t reserve1 : 25; // 7 Reserve
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} reg_sai_bclrfr_t;
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typedef struct {
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uint32_t data : 32; // 0 Data
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} reg_sai_adr_t;
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typedef struct {
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uint32_t data : 32; // 0 Data
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} reg_sai_bdr_t;
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typedef struct {
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uint32_t pdmen : 1; // 0 PDM enable
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uint32_t reserve0 : 3; // 1 Reserve
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uint32_t micnbr : 2; // 4 MICNBR
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uint32_t reserve1 : 2; // 6 Reserve
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uint32_t cken1 : 1; // 8 Clock enable of bitstream clock number 1
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uint32_t cken2 : 1; // 9 CKEN2
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uint32_t cken3 : 1; // 10 CKEN3
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uint32_t cken4 : 1; // 11 CKEN4
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uint32_t reserve2 : 20; // 12 Reserve
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} reg_sai_pdmcr_t;
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typedef struct {
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uint32_t dlym1l : 3; // 0 Delay line adjust for first microphone of pair 1
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t dlym1r : 3; // 4 Delay line adjust for second microphone of pair 1
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uint32_t reserve1 : 1; // 7 Reserve
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uint32_t dlym2l : 3; // 8 Delay line for first microphone of pair 2
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uint32_t reserve2 : 1; // 11 Reserve
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uint32_t dlym2r : 3; // 12 Delay line for second microphone of pair 2
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uint32_t reserve3 : 1; // 15 Reserve
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uint32_t dlym3l : 3; // 16 DLYM3L
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uint32_t reserve4 : 1; // 19 Reserve
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uint32_t dlym3r : 3; // 20 DLYM3R
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uint32_t reserve5 : 1; // 23 Reserve
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uint32_t dlym4l : 3; // 24 DLYM4L
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uint32_t reserve6 : 1; // 27 Reserve
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uint32_t dlym4r : 3; // 28 DLYM4R
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uint32_t reserve7 : 1; // 31 Reserve
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} reg_sai_pdmdly_t;
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typedef struct {
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volatile reg_sai_gcr_t gcr;
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volatile reg_sai_acr1_t acr1;
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volatile uint32_t reserve0[7];
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volatile reg_sai_bcr1_t bcr1;
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volatile uint32_t reserve1[-8];
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volatile reg_sai_acr2_t acr2;
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volatile uint32_t reserve2[7];
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volatile reg_sai_bcr2_t bcr2;
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volatile uint32_t reserve3[-8];
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volatile reg_sai_afrcr_t afrcr;
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volatile uint32_t reserve4[7];
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volatile reg_sai_bfrcr_t bfrcr;
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volatile uint32_t reserve5[-8];
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volatile reg_sai_aslotr_t aslotr;
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volatile uint32_t reserve6[7];
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volatile reg_sai_bslotr_t bslotr;
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volatile uint32_t reserve7[-8];
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volatile reg_sai_aim_t aim;
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volatile uint32_t reserve8[7];
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volatile reg_sai_bim_t bim;
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volatile uint32_t reserve9[-8];
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volatile reg_sai_asr_t asr;
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volatile uint32_t reserve10[7];
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volatile reg_sai_bsr_t bsr;
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volatile uint32_t reserve11[-8];
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volatile reg_sai_aclrfr_t aclrfr;
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volatile uint32_t reserve12[7];
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volatile reg_sai_bclrfr_t bclrfr;
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volatile uint32_t reserve13[-8];
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volatile reg_sai_adr_t adr;
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volatile uint32_t reserve14[7];
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volatile reg_sai_bdr_t bdr;
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volatile reg_sai_pdmcr_t pdmcr;
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volatile reg_sai_pdmdly_t pdmdly;
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} reg_sai_t;
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