164 lines
6.4 KiB
C
Executable File
164 lines
6.4 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t ue : 1; // 0 USART enable
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uint32_t uesm : 1; // 1 USART enable in Stop mode
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uint32_t re : 1; // 2 Receiver enable
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uint32_t te : 1; // 3 Transmitter enable
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uint32_t idleie : 1; // 4 IDLE interrupt enable
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uint32_t rxfneie : 1; // 5 RXFNEIE
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uint32_t tcie : 1; // 6 Transmission complete interrupt enable
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uint32_t txfnfie : 1; // 7 TXFIFO not full interrupt enable
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uint32_t peie : 1; // 8 PE interrupt enable
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uint32_t ps : 1; // 9 Parity selection
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uint32_t pce : 1; // 10 Parity control enable
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uint32_t wake : 1; // 11 Receiver wakeup method
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uint32_t m0 : 1; // 12 Word length
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uint32_t mme : 1; // 13 Mute mode enable
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uint32_t cmie : 1; // 14 Character match interrupt enable
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uint32_t reserve0 : 1; // 15 Reserve
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uint32_t dedt : 5; // 16 DEDT
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uint32_t deat : 5; // 21 DEAT
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uint32_t reserve1 : 2; // 26 Reserve
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uint32_t m1 : 1; // 28 Word length
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uint32_t fifoen : 1; // 29 FIFOEN
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uint32_t txfeie : 1; // 30 TXFEIE
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uint32_t rxffie : 1; // 31 RXFFIE
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} reg_lpuart_cr1_t;
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typedef struct {
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uint32_t reserve0 : 4; // 0 Reserve
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uint32_t addm7 : 1; // 4 7-bit Address Detection/4-bit Address Detection
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uint32_t reserve1 : 7; // 5 Reserve
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uint32_t stop : 2; // 12 STOP bits
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uint32_t reserve2 : 1; // 14 Reserve
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uint32_t swap : 1; // 15 Swap TX/RX pins
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uint32_t rxinv : 1; // 16 RX pin active level inversion
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uint32_t txinv : 1; // 17 TX pin active level inversion
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uint32_t datainv : 1; // 18 Binary data inversion
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uint32_t msbfirst : 1; // 19 Most significant bit first
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uint32_t reserve3 : 4; // 20 Reserve
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uint32_t add : 8; // 24 Address of the LPUART node
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} reg_lpuart_cr2_t;
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typedef struct {
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uint32_t eie : 1; // 0 Error interrupt enable
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uint32_t reserve0 : 2; // 1 Reserve
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uint32_t hdsel : 1; // 3 Half-duplex selection
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uint32_t reserve1 : 2; // 4 Reserve
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uint32_t dmar : 1; // 6 DMA enable receiver
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uint32_t dmat : 1; // 7 DMA enable transmitter
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uint32_t rtse : 1; // 8 RTS enable
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uint32_t ctse : 1; // 9 CTS enable
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uint32_t ctsie : 1; // 10 CTS interrupt enable
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uint32_t reserve2 : 1; // 11 Reserve
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uint32_t ovrdis : 1; // 12 Overrun Disable
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uint32_t ddre : 1; // 13 DMA Disable on Reception Error
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uint32_t dem : 1; // 14 Driver enable mode
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uint32_t dep : 1; // 15 Driver enable polarity selection
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uint32_t reserve3 : 7; // 16 Reserve
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uint32_t txftie : 1; // 23 TXFTIE
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uint32_t reserve4 : 1; // 24 Reserve
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uint32_t rxftcfg : 3; // 25 RXFTCFG
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uint32_t rxftie : 1; // 28 RXFTIE
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uint32_t txftcfg : 3; // 29 TXFTCFG
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} reg_lpuart_cr3_t;
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typedef struct {
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uint32_t brr : 20; // 0 BRR
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uint32_t reserve0 : 12; // 20 Reserve
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} reg_lpuart_brr_t;
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typedef struct {
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uint32_t reserve0 : 1; // 0 Reserve
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uint32_t sbkrq : 1; // 1 Send break request
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uint32_t mmrq : 1; // 2 Mute mode request
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uint32_t rxfrq : 1; // 3 Receive data flush request
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uint32_t txfrq : 1; // 4 TXFRQ
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uint32_t reserve1 : 27; // 5 Reserve
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} reg_lpuart_rqr_t;
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typedef struct {
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uint32_t pe : 1; // 0 PE
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uint32_t fe : 1; // 1 FE
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uint32_t ne : 1; // 2 NE
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uint32_t ore : 1; // 3 ORE
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uint32_t idle : 1; // 4 IDLE
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uint32_t rxfne : 1; // 5 RXFNE
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uint32_t tc : 1; // 6 TC
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uint32_t txfnf : 1; // 7 TXFNF
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uint32_t reserve0 : 1; // 8 Reserve
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uint32_t ctsif : 1; // 9 CTSIF
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uint32_t cts : 1; // 10 CTS
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uint32_t reserve1 : 5; // 11 Reserve
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uint32_t busy : 1; // 16 BUSY
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uint32_t cmf : 1; // 17 CMF
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uint32_t sbkf : 1; // 18 SBKF
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uint32_t rwu : 1; // 19 RWU
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uint32_t reserve2 : 1; // 20 Reserve
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uint32_t teack : 1; // 21 TEACK
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uint32_t reack : 1; // 22 REACK
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uint32_t txfe : 1; // 23 TXFE
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uint32_t rxff : 1; // 24 RXFF
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uint32_t reserve3 : 1; // 25 Reserve
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uint32_t rxft : 1; // 26 RXFT
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uint32_t txft : 1; // 27 TXFT
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uint32_t reserve4 : 4; // 28 Reserve
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} reg_lpuart_isr_t;
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typedef struct {
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uint32_t pecf : 1; // 0 Parity error clear flag
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uint32_t fecf : 1; // 1 Framing error clear flag
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uint32_t necf : 1; // 2 Noise detected clear flag
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uint32_t orecf : 1; // 3 Overrun error clear flag
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uint32_t idlecf : 1; // 4 Idle line detected clear flag
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uint32_t reserve0 : 1; // 5 Reserve
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uint32_t tccf : 1; // 6 Transmission complete clear flag
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uint32_t reserve1 : 2; // 7 Reserve
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uint32_t ctscf : 1; // 9 CTS clear flag
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uint32_t reserve2 : 7; // 10 Reserve
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uint32_t cmcf : 1; // 17 Character match clear flag
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uint32_t reserve3 : 14; // 18 Reserve
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} reg_lpuart_icr_t;
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typedef struct {
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uint32_t rdr : 9; // 0 Receive data value
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uint32_t reserve0 : 23; // 9 Reserve
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} reg_lpuart_rdr_t;
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typedef struct {
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uint32_t tdr : 9; // 0 Transmit data value
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uint32_t reserve0 : 23; // 9 Reserve
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} reg_lpuart_tdr_t;
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typedef struct {
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uint32_t prescaler : 4; // 0 PRESCALER
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uint32_t reserve0 : 28; // 4 Reserve
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} reg_lpuart_presc_t;
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typedef struct {
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uint32_t tdn : 16; // 0 TDN
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uint32_t trigpol : 1; // 16 TRIGPOL
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uint32_t trigen : 1; // 17 TRIGEN
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uint32_t idledis : 1; // 18 IDLEDIS
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uint32_t trigsel : 4; // 19 TRIGSEL
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uint32_t reserve0 : 8; // 23 Reserve
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uint32_t teclren : 1; // 31 TECLREN
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} reg_lpuart_autocr_t;
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typedef struct {
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volatile reg_lpuart_cr1_t cr1;
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volatile reg_lpuart_cr2_t cr2;
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volatile reg_lpuart_cr3_t cr3;
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volatile reg_lpuart_brr_t brr;
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volatile uint32_t reserve0[2];
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volatile reg_lpuart_rqr_t rqr;
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volatile reg_lpuart_isr_t isr;
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volatile reg_lpuart_icr_t icr;
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volatile reg_lpuart_rdr_t rdr;
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volatile reg_lpuart_tdr_t tdr;
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volatile reg_lpuart_presc_t presc;
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volatile reg_lpuart_autocr_t autocr;
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} reg_lpuart_t;
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