160 lines
7.0 KiB
C
Executable File
160 lines
7.0 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t pe : 1; // 0 Peripheral enable
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uint32_t txie : 1; // 1 TX Interrupt enable
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uint32_t rxie : 1; // 2 RX Interrupt enable
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uint32_t addrie : 1; // 3 Address match interrupt enable (slave only)
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uint32_t nackie : 1; // 4 Not acknowledge received interrupt enable
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uint32_t stopie : 1; // 5 STOP detection Interrupt enable
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uint32_t tcie : 1; // 6 Transfer Complete interrupt enable
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uint32_t errie : 1; // 7 Error interrupts enable
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uint32_t dnf : 4; // 8 Digital noise filter
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uint32_t anfoff : 1; // 12 Analog noise filter OFF
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uint32_t reserve0 : 1; // 13 Reserve
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uint32_t txdmaen : 1; // 14 DMA transmission requests enable
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uint32_t rxdmaen : 1; // 15 DMA reception requests enable
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uint32_t sbc : 1; // 16 Slave byte control
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uint32_t nostretch : 1; // 17 Clock stretching disable
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uint32_t wupen : 1; // 18 Wakeup from STOP enable
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uint32_t gcen : 1; // 19 General call enable
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uint32_t smbhen : 1; // 20 SMBus Host address enable
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uint32_t smbden : 1; // 21 SMBus Device Default address enable
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uint32_t alerten : 1; // 22 SMBUS alert enable
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uint32_t pecen : 1; // 23 PEC enable
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uint32_t fmp : 1; // 24 Fast-mode Plus 20 mA drive enable
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uint32_t reserve1 : 5; // 25 Reserve
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uint32_t addraclr : 1; // 30 Address match flag (ADDR) automatic clear
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uint32_t stopfaclr : 1; // 31 STOP detection flag (STOPF) automatic clear
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} reg_i2c_cr1_t;
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typedef struct {
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uint32_t sadd : 10; // 0 Slave address bit (master mode)
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uint32_t rd_wrn : 1; // 10 Transfer direction (master mode)
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uint32_t add10 : 1; // 11 10-bit addressing mode (master mode)
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uint32_t head10r : 1; // 12 10-bit address header only read direction (master receiver mode)
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uint32_t start : 1; // 13 Start generation
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uint32_t stop : 1; // 14 Stop generation (master mode)
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uint32_t nack : 1; // 15 NACK generation (slave mode)
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uint32_t nbytes : 8; // 16 Number of bytes
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uint32_t reload : 1; // 24 NBYTES reload mode
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uint32_t autoend : 1; // 25 Automatic end mode (master mode)
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uint32_t pecbyte : 1; // 26 Packet error checking byte
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uint32_t reserve0 : 5; // 27 Reserve
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} reg_i2c_cr2_t;
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typedef struct {
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uint32_t oa1 : 10; // 0 Interface address
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uint32_t oa1mode : 1; // 10 Own Address 1 10-bit mode
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uint32_t reserve0 : 4; // 11 Reserve
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uint32_t oa1en : 1; // 15 Own Address 1 enable
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uint32_t reserve1 : 16; // 16 Reserve
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} reg_i2c_oar1_t;
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typedef struct {
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uint32_t reserve0 : 1; // 0 Reserve
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uint32_t oa2 : 7; // 1 Interface address
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uint32_t oa2msk : 3; // 8 Own Address 2 masks
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uint32_t reserve1 : 4; // 11 Reserve
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uint32_t oa2en : 1; // 15 Own Address 2 enable
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uint32_t reserve2 : 16; // 16 Reserve
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} reg_i2c_oar2_t;
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typedef struct {
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uint32_t scll : 8; // 0 SCL low period (master mode)
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uint32_t sclh : 8; // 8 SCL high period (master mode)
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uint32_t sdadel : 4; // 16 Data hold time
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uint32_t scldel : 4; // 20 Data setup time
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uint32_t reserve0 : 4; // 24 Reserve
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uint32_t presc : 4; // 28 Timing prescaler
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} reg_i2c_timingr_t;
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typedef struct {
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uint32_t timeouta : 12; // 0 Bus timeout A
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uint32_t tidle : 1; // 12 Idle clock timeout detection
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uint32_t reserve0 : 2; // 13 Reserve
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uint32_t timouten : 1; // 15 Clock timeout enable
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uint32_t timeoutb : 12; // 16 Bus timeout B
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uint32_t reserve1 : 3; // 28 Reserve
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uint32_t texten : 1; // 31 Extended clock timeout enable
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} reg_i2c_timeoutr_t;
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typedef struct {
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uint32_t txe : 1; // 0 Transmit data register empty (transmitters)
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uint32_t txis : 1; // 1 Transmit interrupt status (transmitters)
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uint32_t rxne : 1; // 2 Receive data register not empty (receivers)
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uint32_t addr : 1; // 3 Address matched (slave mode)
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uint32_t nackf : 1; // 4 Not acknowledge received flag
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uint32_t stopf : 1; // 5 Stop detection flag
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uint32_t tc : 1; // 6 Transfer Complete (master mode)
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uint32_t tcr : 1; // 7 Transfer Complete Reload
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uint32_t berr : 1; // 8 Bus error
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uint32_t arlo : 1; // 9 Arbitration lost
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uint32_t ovr : 1; // 10 Overrun/Underrun (slave mode)
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uint32_t pecerr : 1; // 11 PEC Error in reception
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uint32_t timeout : 1; // 12 Timeout or t_low detection flag
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uint32_t alert : 1; // 13 SMBus alert
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uint32_t reserve0 : 1; // 14 Reserve
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uint32_t busy : 1; // 15 Bus busy
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uint32_t dir : 1; // 16 Transfer direction (Slave mode)
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uint32_t addcode : 7; // 17 Address match code (Slave mode)
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uint32_t reserve1 : 8; // 24 Reserve
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} reg_i2c_isr_t;
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typedef struct {
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uint32_t reserve0 : 3; // 0 Reserve
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uint32_t addrcf : 1; // 3 Address Matched flag clear
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uint32_t nackcf : 1; // 4 Not Acknowledge flag clear
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uint32_t stopcf : 1; // 5 Stop detection flag clear
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uint32_t reserve1 : 2; // 6 Reserve
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uint32_t berrcf : 1; // 8 Bus error flag clear
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uint32_t arlocf : 1; // 9 Arbitration lost flag clear
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uint32_t ovrcf : 1; // 10 Overrun/Underrun flag clear
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uint32_t peccf : 1; // 11 PEC Error flag clear
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uint32_t timoutcf : 1; // 12 Timeout detection flag clear
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uint32_t alertcf : 1; // 13 Alert flag clear
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uint32_t reserve2 : 18; // 14 Reserve
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} reg_i2c_icr_t;
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typedef struct {
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uint32_t pec : 8; // 0 Packet error checking register
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uint32_t reserve0 : 24; // 8 Reserve
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} reg_i2c_pecr_t;
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typedef struct {
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uint32_t rxdata : 8; // 0 8-bit receive data
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uint32_t reserve0 : 24; // 8 Reserve
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} reg_i2c_rxdr_t;
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typedef struct {
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uint32_t txdata : 8; // 0 8-bit transmit data
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uint32_t reserve0 : 24; // 8 Reserve
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} reg_i2c_txdr_t;
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typedef struct {
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uint32_t reserve0 : 6; // 0 Reserve
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uint32_t tcdmaen : 1; // 6 DMA request enable on Transfer Complete event
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uint32_t tcrdmaen : 1; // 7 DMA request enable on Transfer Complete Reload event
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uint32_t reserve1 : 8; // 8 Reserve
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uint32_t trigsel : 4; // 16 Trigger selection
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uint32_t trigpol : 1; // 20 Trigger polarity
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uint32_t trigen : 1; // 21 Trigger enable
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uint32_t reserve2 : 10; // 22 Reserve
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} reg_i2c_autocr_t;
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typedef struct {
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volatile reg_i2c_cr1_t cr1;
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volatile reg_i2c_cr2_t cr2;
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volatile reg_i2c_oar1_t oar1;
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volatile reg_i2c_oar2_t oar2;
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volatile reg_i2c_timingr_t timingr;
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volatile reg_i2c_timeoutr_t timeoutr;
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volatile reg_i2c_isr_t isr;
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volatile reg_i2c_icr_t icr;
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volatile reg_i2c_pecr_t pecr;
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volatile reg_i2c_rxdr_t rxdr;
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volatile reg_i2c_txdr_t txdr;
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volatile reg_i2c_autocr_t autocr;
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} reg_i2c_t;
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