259 lines
11 KiB
C
Executable File
259 lines
11 KiB
C
Executable File
#include <stdint.h>
|
|
|
|
typedef struct {
|
|
uint32_t ue : 1; // 0 USART enable
|
|
uint32_t uesm : 1; // 1 USART enable in Stop mode
|
|
uint32_t re : 1; // 2 Receiver enable
|
|
uint32_t te : 1; // 3 Transmitter enable
|
|
uint32_t idleie : 1; // 4 IDLE interrupt enable
|
|
uint32_t rxfneie : 1; // 5 RXFIFO not empty interrupt enable
|
|
uint32_t tcie : 1; // 6 Transmission complete interrupt enable
|
|
uint32_t txfnfie : 1; // 7 TXFIFO not full interrupt enable
|
|
uint32_t peie : 1; // 8 PE interrupt enable
|
|
uint32_t ps : 1; // 9 Parity selection
|
|
uint32_t pce : 1; // 10 Parity control enable
|
|
uint32_t wake : 1; // 11 Receiver wakeup method
|
|
uint32_t m0 : 1; // 12 Word length
|
|
uint32_t mme : 1; // 13 Mute mode enable
|
|
uint32_t cmie : 1; // 14 Character match interrupt enable
|
|
uint32_t over8 : 1; // 15 Oversampling mode
|
|
uint32_t dedt : 5; // 16 DEDT
|
|
uint32_t deat : 5; // 21 DEAT
|
|
uint32_t rtoie : 1; // 26 Receiver timeout interrupt
|
|
uint32_t eobie : 1; // 27 End of Block interruptenable
|
|
uint32_t m1 : 1; // 28 Word length
|
|
uint32_t fifoen : 1; // 29 FIFOEN
|
|
uint32_t txfeie : 1; // 30 TXFEIE
|
|
uint32_t rxffie : 1; // 31 RXFFIE
|
|
} reg_usart_cr1_enabled_t;
|
|
|
|
typedef struct {
|
|
uint32_t ue : 1; // 0 USART enable
|
|
uint32_t uesm : 1; // 1 USART enable in Stop mode
|
|
uint32_t re : 1; // 2 Receiver enable
|
|
uint32_t te : 1; // 3 Transmitter enable
|
|
uint32_t idleie : 1; // 4 IDLE interrupt enable
|
|
uint32_t rxfneie : 1; // 5 RXFIFO not empty interrupt enable
|
|
uint32_t tcie : 1; // 6 Transmission complete interrupt enable
|
|
uint32_t txfnfie : 1; // 7 TXFIFO not full interrupt enable
|
|
uint32_t peie : 1; // 8 PE interrupt enable
|
|
uint32_t ps : 1; // 9 Parity selection
|
|
uint32_t pce : 1; // 10 Parity control enable
|
|
uint32_t wake : 1; // 11 Receiver wakeup method
|
|
uint32_t m0 : 1; // 12 Word length
|
|
uint32_t mme : 1; // 13 Mute mode enable
|
|
uint32_t cmie : 1; // 14 Character match interrupt enable
|
|
uint32_t over8 : 1; // 15 Oversampling mode
|
|
uint32_t dedt : 5; // 16 DEDT
|
|
uint32_t deat : 5; // 21 DEAT
|
|
uint32_t rtoie : 1; // 26 Receiver timeout interrupt enable
|
|
uint32_t eobie : 1; // 27 End of Block interrupt enable
|
|
uint32_t m1 : 1; // 28 Word length
|
|
uint32_t fifoen : 1; // 29 FIFOEN
|
|
uint32_t reserve0 : 2; // 30 Reserve
|
|
} reg_usart_cr1_disabled_t;
|
|
|
|
typedef struct {
|
|
uint32_t slven : 1; // 0 SLVEN
|
|
uint32_t reserve0 : 2; // 1 Reserve
|
|
uint32_t dis_nss : 1; // 3 DIS_NSS
|
|
uint32_t addm7 : 1; // 4 7-bit Address Detection/4-bit Address Detection
|
|
uint32_t lbdl : 1; // 5 LIN break detection length
|
|
uint32_t lbdie : 1; // 6 LIN break detection interrupt enable
|
|
uint32_t reserve1 : 1; // 7 Reserve
|
|
uint32_t lbcl : 1; // 8 Last bit clock pulse
|
|
uint32_t cpha : 1; // 9 Clock phase
|
|
uint32_t cpol : 1; // 10 Clock polarity
|
|
uint32_t clken : 1; // 11 Clock enable
|
|
uint32_t stop : 2; // 12 STOP bits
|
|
uint32_t linen : 1; // 14 LIN mode enable
|
|
uint32_t swap : 1; // 15 Swap TX/RX pins
|
|
uint32_t rxinv : 1; // 16 RX pin active level inversion
|
|
uint32_t txinv : 1; // 17 TX pin active level inversion
|
|
uint32_t datainv : 1; // 18 Binary data inversion
|
|
uint32_t msbfirst : 1; // 19 Most significant bit first
|
|
uint32_t abren : 1; // 20 Auto baud rate enable
|
|
uint32_t abrmod : 2; // 21 Auto baud rate mode
|
|
uint32_t rtoen : 1; // 23 Receiver timeout enable
|
|
uint32_t add : 8; // 24 Address of the USART node
|
|
} reg_usart_cr2_t;
|
|
|
|
typedef struct {
|
|
uint32_t eie : 1; // 0 Error interrupt enable
|
|
uint32_t iren : 1; // 1 Ir mode enable
|
|
uint32_t irlp : 1; // 2 Ir low-power
|
|
uint32_t hdsel : 1; // 3 Half-duplex selection
|
|
uint32_t nack : 1; // 4 Smartcard NACK enable
|
|
uint32_t scen : 1; // 5 Smartcard mode enable
|
|
uint32_t dmar : 1; // 6 DMA enable receiver
|
|
uint32_t dmat : 1; // 7 DMA enable transmitter
|
|
uint32_t rtse : 1; // 8 RTS enable
|
|
uint32_t ctse : 1; // 9 CTS enable
|
|
uint32_t ctsie : 1; // 10 CTS interrupt enable
|
|
uint32_t onebit : 1; // 11 One sample bit method enable
|
|
uint32_t ovrdis : 1; // 12 Overrun Disable
|
|
uint32_t ddre : 1; // 13 DMA Disable on Reception Error
|
|
uint32_t dem : 1; // 14 Driver enable mode
|
|
uint32_t dep : 1; // 15 Driver enable polarity selection
|
|
uint32_t reserve0 : 1; // 16 Reserve
|
|
uint32_t scarcnt : 3; // 17 Smartcard auto-retry count
|
|
uint32_t reserve1 : 3; // 20 Reserve
|
|
uint32_t txftie : 1; // 23 TXFTIE
|
|
uint32_t tcbgtie : 1; // 24 TCBGTIE
|
|
uint32_t rxftcfg : 3; // 25 RXFTCFG
|
|
uint32_t rxftie : 1; // 28 RXFTIE
|
|
uint32_t txftcfg : 3; // 29 TXFTCFG
|
|
} reg_usart_cr3_t;
|
|
|
|
typedef struct {
|
|
uint32_t brr : 16; // 0 BRR
|
|
uint32_t reserve0 : 16; // 16 Reserve
|
|
} reg_usart_brr_t;
|
|
|
|
typedef struct {
|
|
uint32_t psc : 8; // 0 Prescaler value
|
|
uint32_t gt : 8; // 8 Guard time value
|
|
uint32_t reserve0 : 16; // 16 Reserve
|
|
} reg_usart_gtpr_t;
|
|
|
|
typedef struct {
|
|
uint32_t rto : 24; // 0 Receiver timeout value
|
|
uint32_t blen : 8; // 24 Block Length
|
|
} reg_usart_rtor_t;
|
|
|
|
typedef struct {
|
|
uint32_t abrrq : 1; // 0 Auto baud rate request
|
|
uint32_t sbkrq : 1; // 1 Send break request
|
|
uint32_t mmrq : 1; // 2 Mute mode request
|
|
uint32_t rxfrq : 1; // 3 Receive data flush request
|
|
uint32_t txfrq : 1; // 4 Transmit data flush request
|
|
uint32_t reserve0 : 27; // 5 Reserve
|
|
} reg_usart_rqr_t;
|
|
|
|
typedef struct {
|
|
uint32_t pe : 1; // 0 PE
|
|
uint32_t fe : 1; // 1 FE
|
|
uint32_t ne : 1; // 2 NE
|
|
uint32_t ore : 1; // 3 ORE
|
|
uint32_t idle : 1; // 4 IDLE
|
|
uint32_t rxfne : 1; // 5 RXFNE
|
|
uint32_t tc : 1; // 6 TC
|
|
uint32_t txfnf : 1; // 7 TXFNF
|
|
uint32_t lbdf : 1; // 8 LBDF
|
|
uint32_t ctsif : 1; // 9 CTSIF
|
|
uint32_t cts : 1; // 10 CTS
|
|
uint32_t rtof : 1; // 11 RTOF
|
|
uint32_t eobf : 1; // 12 EOBF
|
|
uint32_t reserve0 : 1; // 13 Reserve
|
|
uint32_t abre : 1; // 14 ABRE
|
|
uint32_t abrf : 1; // 15 ABRF
|
|
uint32_t busy : 1; // 16 BUSY
|
|
uint32_t cmf : 1; // 17 CMF
|
|
uint32_t sbkf : 1; // 18 SBKF
|
|
uint32_t rwu : 1; // 19 RWU
|
|
uint32_t reserve1 : 1; // 20 Reserve
|
|
uint32_t teack : 1; // 21 TEACK
|
|
uint32_t reack : 1; // 22 REACK
|
|
uint32_t txfe : 1; // 23 TXFE
|
|
uint32_t rxff : 1; // 24 RXFF
|
|
uint32_t tcbgt : 1; // 25 TCBGT
|
|
uint32_t rxft : 1; // 26 RXFT
|
|
uint32_t txft : 1; // 27 TXFT
|
|
uint32_t reserve2 : 4; // 28 Reserve
|
|
} reg_usart_isr_enabled_t;
|
|
|
|
typedef struct {
|
|
uint32_t pe : 1; // 0 PE
|
|
uint32_t fe : 1; // 1 FE
|
|
uint32_t ne : 1; // 2 NE
|
|
uint32_t ore : 1; // 3 ORE
|
|
uint32_t idle : 1; // 4 IDLE
|
|
uint32_t rxfne : 1; // 5 RXFNE
|
|
uint32_t tc : 1; // 6 TC
|
|
uint32_t txfnf : 1; // 7 TXFNF
|
|
uint32_t lbdf : 1; // 8 LBDF
|
|
uint32_t ctsif : 1; // 9 CTSIF
|
|
uint32_t cts : 1; // 10 CTS
|
|
uint32_t rtof : 1; // 11 RTOF
|
|
uint32_t eobf : 1; // 12 EOBF
|
|
uint32_t udr : 1; // 13 UDR
|
|
uint32_t abre : 1; // 14 ABRE
|
|
uint32_t abrf : 1; // 15 ABRF
|
|
uint32_t busy : 1; // 16 BUSY
|
|
uint32_t cmf : 1; // 17 CMF
|
|
uint32_t sbkf : 1; // 18 SBKF
|
|
uint32_t rwu : 1; // 19 RWU
|
|
uint32_t reserve0 : 1; // 20 Reserve
|
|
uint32_t teack : 1; // 21 TEACK
|
|
uint32_t reack : 1; // 22 REACK
|
|
uint32_t reserve1 : 2; // 23 Reserve
|
|
uint32_t tcbgt : 1; // 25 TCBGT
|
|
uint32_t reserve2 : 6; // 26 Reserve
|
|
} reg_usart_isr_disabled_t;
|
|
|
|
typedef struct {
|
|
uint32_t pecf : 1; // 0 Parity error clear flag
|
|
uint32_t fecf : 1; // 1 Framing error clear flag
|
|
uint32_t necf : 1; // 2 Noise detected clear flag
|
|
uint32_t orecf : 1; // 3 Overrun error clear flag
|
|
uint32_t idlecf : 1; // 4 Idle line detected clear flag
|
|
uint32_t txfecf : 1; // 5 TXFECF
|
|
uint32_t tccf : 1; // 6 Transmission complete clear flag
|
|
uint32_t tcbgtcf : 1; // 7 TCBGTCF
|
|
uint32_t lbdcf : 1; // 8 LIN break detection clear flag
|
|
uint32_t ctscf : 1; // 9 CTS clear flag
|
|
uint32_t reserve0 : 1; // 10 Reserve
|
|
uint32_t rtocf : 1; // 11 Receiver timeout clear flag
|
|
uint32_t eobcf : 1; // 12 End of block clear flag
|
|
uint32_t udrcf : 1; // 13 UDRCF
|
|
uint32_t reserve1 : 3; // 14 Reserve
|
|
uint32_t cmcf : 1; // 17 Character match clear flag
|
|
uint32_t reserve2 : 14; // 18 Reserve
|
|
} reg_usart_icr_t;
|
|
|
|
typedef struct {
|
|
uint32_t rdr : 9; // 0 Receive data value
|
|
uint32_t reserve0 : 23; // 9 Reserve
|
|
} reg_usart_rdr_t;
|
|
|
|
typedef struct {
|
|
uint32_t tdr : 9; // 0 Transmit data value
|
|
uint32_t reserve0 : 23; // 9 Reserve
|
|
} reg_usart_tdr_t;
|
|
|
|
typedef struct {
|
|
uint32_t prescaler : 4; // 0 PRESCALER
|
|
uint32_t reserve0 : 28; // 4 Reserve
|
|
} reg_usart_presc_t;
|
|
|
|
typedef struct {
|
|
uint32_t tdn : 16; // 0 TDN
|
|
uint32_t trigpol : 1; // 16 TRIPOL
|
|
uint32_t trigen : 1; // 17 TRIGEN
|
|
uint32_t idledis : 1; // 18 IDLEDIS
|
|
uint32_t trigsel : 4; // 19 TRIGSEL
|
|
uint32_t reserve0 : 8; // 23 Reserve
|
|
uint32_t teclren : 1; // 31 TECLREN
|
|
} reg_usart_autocr_t;
|
|
|
|
typedef struct {
|
|
volatile reg_usart_cr1_enabled_t cr1_enabled;
|
|
volatile uint32_t reserve0[-1];
|
|
volatile reg_usart_cr1_disabled_t cr1_disabled;
|
|
volatile reg_usart_cr2_t cr2;
|
|
volatile reg_usart_cr3_t cr3;
|
|
volatile reg_usart_brr_t brr;
|
|
volatile reg_usart_gtpr_t gtpr;
|
|
volatile reg_usart_rtor_t rtor;
|
|
volatile reg_usart_rqr_t rqr;
|
|
volatile reg_usart_isr_enabled_t isr_enabled;
|
|
volatile uint32_t reserve1[-1];
|
|
volatile reg_usart_isr_disabled_t isr_disabled;
|
|
volatile reg_usart_icr_t icr;
|
|
volatile reg_usart_rdr_t rdr;
|
|
volatile reg_usart_tdr_t tdr;
|
|
volatile reg_usart_presc_t presc;
|
|
volatile reg_usart_autocr_t autocr;
|
|
} reg_usart_t;
|
|
|