94 lines
3.1 KiB
C
Executable File
94 lines
3.1 KiB
C
Executable File
#ifndef REG_DCMI_H
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#define REG_DCMI_H
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#include <stm32u5xx.h>
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typedef struct {
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uint32_t capture: 1; // capture enable
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uint32_t cm: 1; // capture mode
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uint32_t crop: 1; // crop enable
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uint32_t jpeg: 1; // jpeg enable
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uint32_t ess: 1; // embedded synchronization select
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uint32_t pckpol: 1; // pixel clock polarity
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uint32_t hspol: 1; // horizontal synchronization polarity
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uint32_t vspol: 1; // vertical synchronization polarity
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uint32_t fcrc: 2; // frame capture rate control
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uint32_t edm: 2; // extended data mode
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uint32_t resv: 2; // reserved
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uint32_t enable: 1; // DCMI enable
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uint32_t resv2: 1;
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uint32_t bsm: 2; // byte select mode
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uint32_t oebs: 1; // odd/even byte select
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uint32_t lsm: 1; // line select mode
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uint32_t oels: 1; // odd/even line select
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uint32_t resv3: 11;
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} reg_dcmi_cr_t;
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typedef struct {
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uint32_t hsync: 1; // horizontal synchronization
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uint32_t vsync: 1; // vertical synchronization
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uint32_t fne: 1; // frame end
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uint32_t resv: 29;
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} reg_dcmi_sr_t;
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typedef struct {
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uint32_t frame_ris: 1; // frame capture complete raw interrupt status
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uint32_t ovr_ris: 1; // overrun raw interrupt status
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uint32_t err_ris: 1; // synchronization error raw interrupt status
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uint32_t vsync_ris: 1; // vsync raw interrupt status
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uint32_t line_ris: 1; // line raw interrupt status
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uint32_t resv: 27;
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} reg_dcmi_ris_t; // raw interrupt status register
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typedef struct {
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uint32_t frame_ie: 1; // frame capture complete interrupt enable
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uint32_t ovr_ie: 1; // overrun interrupt enable
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uint32_t err_ie: 1; // synchronization error interrupt enable
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uint32_t vsync_ie: 1; // vsync interrupt enable
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uint32_t line_ie: 1; // line interrupt enable
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uint32_t resv: 27;
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} reg_dcmi_ier_t; // interrupt enable register
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typedef struct {
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uint32_t frame_mis: 1; // frame capture complete masked interrupt status
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uint32_t ovr_mis: 1; // overrun masked interrupt status
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uint32_t err_mis: 1; // synchronization error masked interrupt status
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uint32_t vsync_mis: 1; // vsync masked interrupt status
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uint32_t line_mis: 1; // line masked interrupt status
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uint32_t resv: 27;
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} reg_dcmi_misr_t; // masked interrupt status register
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// icr
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typedef struct {
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uint32_t frame_isc: 1; // frame capture complete interrupt status clear
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uint32_t ovr_isc: 1; // overrun interrupt status clear
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uint32_t err_isc: 1; // synchronization error interrupt status clear
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uint32_t vsync_isc: 1; // vsync interrupt status clear
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uint32_t line_isc: 1; // line interrupt status clear
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uint32_t resv: 27;
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} reg_dcmi_icr_t; // interrupt clear register
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typedef struct {
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uint32_t byte0: 8;
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uint32_t byte1: 8;
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uint32_t byte2: 8;
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uint32_t byte3: 8;
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} reg_dcmi_dr_t; // data register
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typedef struct {
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reg_dcmi_cr_t cr;
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reg_dcmi_sr_t sr;
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reg_dcmi_ris_t risr;
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reg_dcmi_ier_t ier;
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reg_dcmi_misr_t misr;
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reg_dcmi_icr_t icr;
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uint32_t escr;
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uint32_t esur;
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uint32_t cwstrtr;
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uint32_t cwsizer;
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reg_dcmi_dr_t dr;
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} reg_dcmi_s;
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#endif
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