295 lines
14 KiB
C
Executable File
295 lines
14 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t lck : 1; // 0 lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx registers until next reset
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uint32_t reserve0 : 31; // 1 Reserve
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} reg_gtzc1_tzsc_tzsc_cr_t;
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typedef struct {
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uint32_t tim2sec : 1; // 0 secure access mode for TIM2
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uint32_t tim3sec : 1; // 1 secure access mode for TIM3
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uint32_t tim4sec : 1; // 2 secure access mode for TIM4
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uint32_t tim5sec : 1; // 3 secure access mode for TIM5
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uint32_t tim6sec : 1; // 4 secure access mode for TIM6
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uint32_t tim7sec : 1; // 5 secure access mode for TIM7
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uint32_t wwdgsec : 1; // 6 secure access mode for WWDG
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uint32_t iwdgsec : 1; // 7 secure access mode for IWDG
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uint32_t spi2sec : 1; // 8 secure access mode for SPI2
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uint32_t usart2sec : 1; // 9 secure access mode for USART2
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uint32_t usart3sec : 1; // 10 secure access mode for USART3
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uint32_t uart4sec : 1; // 11 secure access mode for UART4
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uint32_t uart5sec : 1; // 12 secure access mode for UART5
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uint32_t i2c1sec : 1; // 13 secure access mode for I2C1
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uint32_t i2c2sec : 1; // 14 secure access mode for I2C2
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uint32_t crssec : 1; // 15 secure access mode for CRS
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uint32_t i2c4sec : 1; // 16 secure access mode for I2C4
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uint32_t lptim2sec : 1; // 17 secure access mode for LPTIM2
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uint32_t fdcan1sec : 1; // 18 secure access mode for FDCAN1
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uint32_t ucpd1sec : 1; // 19 secure access mode for UCPD1
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uint32_t reserve0 : 12; // 20 Reserve
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} reg_gtzc1_tzsc_tzsc_seccfgr1_t;
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typedef struct {
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uint32_t tim1sec : 1; // 0 secure access mode for TIM1
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uint32_t spi1sec : 1; // 1 secure access mode for SPI1
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uint32_t tim8sec : 1; // 2 secure access mode for TIM8
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uint32_t usart1sec : 1; // 3 secure access mode for USART1
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uint32_t tim15sec : 1; // 4 secure access mode for TIM5
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uint32_t tim16sec : 1; // 5 secure access mode for TIM6
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uint32_t tim17sec : 1; // 6 secure access mode for TIM7
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uint32_t sai1sec : 1; // 7 secure access mode for SAI1
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uint32_t sai2sec : 1; // 8 secure access mode for SAI2
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uint32_t reserve0 : 23; // 9 Reserve
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} reg_gtzc1_tzsc_tzsc_seccfgr2_t;
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typedef struct {
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uint32_t mdf1sec : 1; // 0 secure access mode for MDF1
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uint32_t cordicsec : 1; // 1 secure access mode for CORDIC
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uint32_t fmacsec : 1; // 2 secure access mode for FMAC
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uint32_t crcsec : 1; // 3 secure access mode for CRC
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uint32_t tscsec : 1; // 4 secure access mode for TSC
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uint32_t dma2dsec : 1; // 5 secure access mode for register of DMA2D
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uint32_t icache_regsec: 1; // 6 secure access mode for ICACHE registers
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uint32_t dcache_regsec: 1; // 7 secure access mode for DCACHE registers
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uint32_t adc1sec : 1; // 8 secure access mode for ADC1
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uint32_t dcmisec : 1; // 9 secure access mode for DCMI
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uint32_t otgfssec : 1; // 10 secure access mode for OTG_FS
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uint32_t aessec : 1; // 11 secure access mode for AES
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uint32_t hashsec : 1; // 12 secure access mode for HASH
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uint32_t rngsec : 1; // 13 secure access mode for RNG
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uint32_t pkasec : 1; // 14 secure access mode for PKA
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uint32_t saessec : 1; // 15 secure access mode for SAES
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uint32_t octospimsec: 1; // 16 secure access mode for OCTOSPIM
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uint32_t sdmmc1sec : 1; // 17 secure access mode for SDMMC2
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uint32_t sdmmc2sec : 1; // 18 secure access mode for SDMMC1
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uint32_t fsmc_regsec: 1; // 19 secure access mode for FSMC registers
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uint32_t octospi1_regsec: 1; // 20 secure access mode for OCTOSPI1 registers
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uint32_t octospi2_regsec: 1; // 21 secure access mode for OCTOSPI2 registers
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uint32_t ramcfgsec : 1; // 22 secure access mode for RAMCFG
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uint32_t reserve0 : 9; // 23 Reserve
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} reg_gtzc1_tzsc_tzsc_seccfgr3_t;
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typedef struct {
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uint32_t tim2priv : 1; // 0 privileged access mode for TIM2
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uint32_t tim3priv : 1; // 1 privileged access mode for TIM3
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uint32_t tim4priv : 1; // 2 privileged access mode for TIM4
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uint32_t tim5priv : 1; // 3 privileged access mode for TIM5
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uint32_t tim6priv : 1; // 4 privileged access mode for TIM6
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uint32_t tim7priv : 1; // 5 privileged access mode for TIM7
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uint32_t wwdgpriv : 1; // 6 privileged access mode for WWDG
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uint32_t iwdgpriv : 1; // 7 privileged access mode for IWDG
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uint32_t spi2priv : 1; // 8 privileged access mode for SPI2
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uint32_t usart2priv: 1; // 9 privileged access mode for USART2
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uint32_t usart3priv: 1; // 10 privileged access mode for USART3
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uint32_t uart4priv : 1; // 11 privileged access mode for UART4
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uint32_t uart5priv : 1; // 12 privileged access mode for UART5
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uint32_t i2c1priv : 1; // 13 privileged access mode for I2C1
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uint32_t i2c2priv : 1; // 14 privileged access mode for I2C2
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uint32_t crspriv : 1; // 15 privileged access mode for CRS
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uint32_t i2c4priv : 1; // 16 privileged access mode for I2C4
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uint32_t lptim2priv: 1; // 17 privileged access mode for LPTIM2
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uint32_t fdcan1priv: 1; // 18 privileged access mode for FDCAN1
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uint32_t ucpd1priv : 1; // 19 privileged access mode for UCPD1
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uint32_t reserve0 : 12; // 20 Reserve
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} reg_gtzc1_tzsc_tzsc_privcfgr1_t;
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typedef struct {
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uint32_t tim1priv : 1; // 0 privileged access mode for TIM1
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uint32_t spi1priv : 1; // 1 privileged access mode for SPI1PRIV
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uint32_t tim8priv : 1; // 2 privileged access mode for TIM8
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uint32_t usart1priv: 1; // 3 privileged access mode for USART1
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uint32_t tim15priv : 1; // 4 privileged access mode for TIM15
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uint32_t tim16priv : 1; // 5 privileged access mode for TIM16
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uint32_t tim17priv : 1; // 6 privileged access mode for TIM17
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uint32_t sai1priv : 1; // 7 privileged access mode for SAI1
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uint32_t sai2priv : 1; // 8 privileged access mode for SAI2
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uint32_t reserve0 : 23; // 9 Reserve
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} reg_gtzc1_tzsc_tzsc_privcfgr2_t;
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typedef struct {
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uint32_t mdf1priv : 1; // 0 privileged access mode for MDF1
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uint32_t cordicpriv: 1; // 1 privileged access mode for CORDIC
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uint32_t fmacpriv : 1; // 2 privileged access mode for FMAC
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uint32_t crcpriv : 1; // 3 privileged access mode for CRC
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uint32_t tscpriv : 1; // 4 privileged access mode for TSC
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uint32_t dma2dpriv : 1; // 5 privileged access mode for register of DMA2D
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uint32_t icache_regpriv: 1; // 6 privileged access mode for ICACHE registers
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uint32_t dcache_regpriv: 1; // 7 privileged access mode for DCACHE registers
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uint32_t adc1priv : 1; // 8 privileged access mode for ADC1
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uint32_t dcmipriv : 1; // 9 privileged access mode for DCMI
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uint32_t otgfspriv : 1; // 10 privileged access mode for OTG_FS
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uint32_t aespriv : 1; // 11 privileged access mode for AES
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uint32_t hashpriv : 1; // 12 privileged access mode for HASH
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uint32_t rngpriv : 1; // 13 privileged access mode for RNG
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uint32_t pkapriv : 1; // 14 privileged access mode for PKA
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uint32_t saespriv : 1; // 15 privileged access mode for SAES
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uint32_t octospimpriv: 1; // 16 privileged access mode for OCTOSPIM
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uint32_t sdmmc1priv: 1; // 17 privileged access mode for SDMMC2
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uint32_t sdmmc2priv: 1; // 18 privileged access mode for SDMMC1
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uint32_t fsmc_regpriv: 1; // 19 privileged access mode for FSMC registers
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uint32_t octospi1_regpriv: 1; // 20 privileged access mode for OCTOSPI1
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uint32_t octospi2_regpriv: 1; // 21 privileged access mode for OCTOSPI2
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uint32_t ramcfgpriv: 1; // 22 privileged access mode for RAMCFG
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uint32_t reserve0 : 9; // 23 Reserve
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} reg_gtzc1_tzsc_tzsc_privcfgr3_t;
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typedef struct {
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uint32_t sren : 1; // 0 Sub-region enable
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uint32_t srlock : 1; // 1 Sub-region lock
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uint32_t reserve0 : 6; // 2 Reserve
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uint32_t sec : 1; // 8 Secure sub-region
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uint32_t priv : 1; // 9 Privileged sub-region
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uint32_t reserve1 : 22; // 10 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm1acfgr_t;
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typedef struct {
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uint32_t suba_start: 11; // 0 Start of sub-region A
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uint32_t reserve0 : 5; // 11 Reserve
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uint32_t suba_length: 12; // 16 Length of sub-region A
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uint32_t reserve1 : 4; // 28 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm1ar_t;
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typedef struct {
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uint32_t sren : 1; // 0 Sub-region enable
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uint32_t srlock : 1; // 1 Sub-region lock
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uint32_t reserve0 : 6; // 2 Reserve
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uint32_t sec : 1; // 8 Secure sub-region
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uint32_t priv : 1; // 9 Privileged sub-region
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uint32_t reserve1 : 22; // 10 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm1bcfgr_t;
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typedef struct {
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uint32_t subb_start: 11; // 0 Start of sub-region A
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uint32_t reserve0 : 5; // 11 Reserve
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uint32_t subb_length: 12; // 16 Length of sub-region A
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uint32_t reserve1 : 4; // 28 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm1br_t;
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typedef struct {
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uint32_t sren : 1; // 0 Sub-region enable
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uint32_t srlock : 1; // 1 Sub-region lock
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uint32_t reserve0 : 6; // 2 Reserve
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uint32_t sec : 1; // 8 Secure sub-region
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uint32_t priv : 1; // 9 Privileged sub-region
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uint32_t reserve1 : 22; // 10 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm2acfgr_t;
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typedef struct {
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uint32_t suba_start: 11; // 0 Start of sub-region A
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uint32_t reserve0 : 5; // 11 Reserve
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uint32_t suba_length: 12; // 16 Length of sub-region A
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uint32_t reserve1 : 4; // 28 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm2ar_t;
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typedef struct {
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uint32_t sren : 1; // 0 Sub-region enable
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uint32_t srlock : 1; // 1 Sub-region lock
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uint32_t reserve0 : 6; // 2 Reserve
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uint32_t sec : 1; // 8 Secure sub-region
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uint32_t priv : 1; // 9 Privileged sub-region
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uint32_t reserve1 : 22; // 10 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm2bcfgr_t;
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typedef struct {
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uint32_t subb_start: 11; // 0 Start of sub-region A
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uint32_t reserve0 : 5; // 11 Reserve
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uint32_t subb_length: 12; // 16 Length of sub-region A
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uint32_t reserve1 : 4; // 28 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm2br_t;
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typedef struct {
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uint32_t sren : 1; // 0 Sub-region enable
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uint32_t srlock : 1; // 1 Sub-region lock
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uint32_t reserve0 : 6; // 2 Reserve
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uint32_t sec : 1; // 8 Secure sub-region
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uint32_t priv : 1; // 9 Privileged sub-region
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uint32_t reserve1 : 22; // 10 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm3acfgr_t;
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typedef struct {
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uint32_t suba_start: 11; // 0 Start of sub-region A
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uint32_t reserve0 : 5; // 11 Reserve
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uint32_t suba_length: 12; // 16 Length of sub-region A
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uint32_t reserve1 : 4; // 28 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm3ar_t;
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typedef struct {
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uint32_t sren : 1; // 0 Sub-region enable
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uint32_t srlock : 1; // 1 Sub-region lock
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uint32_t reserve0 : 6; // 2 Reserve
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uint32_t sec : 1; // 8 Secure sub-region
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uint32_t priv : 1; // 9 Privileged sub-region
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uint32_t reserve1 : 22; // 10 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm4acfgr_t;
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typedef struct {
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uint32_t suba_start: 11; // 0 Start of sub-region A
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uint32_t reserve0 : 5; // 11 Reserve
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uint32_t suba_length: 12; // 16 Length of sub-region A
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uint32_t reserve1 : 4; // 28 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm4ar_t;
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typedef struct {
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uint32_t sren : 1; // 0 Sub-region enable
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uint32_t srlock : 1; // 1 Sub-region lock
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uint32_t reserve0 : 6; // 2 Reserve
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uint32_t sec : 1; // 8 Secure sub-region
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uint32_t priv : 1; // 9 Privileged sub-region
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uint32_t reserve1 : 22; // 10 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm5acfgr_t;
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typedef struct {
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uint32_t suba_start: 11; // 0 Start of sub-region A
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uint32_t reserve0 : 5; // 11 Reserve
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uint32_t suba_length: 12; // 16 Length of sub-region A
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uint32_t reserve1 : 4; // 28 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm5ar_t;
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typedef struct {
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uint32_t sren : 1; // 0 Sub-region enable
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uint32_t srlock : 1; // 1 Sub-region lock
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uint32_t reserve0 : 6; // 2 Reserve
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uint32_t sec : 1; // 8 Secure sub-region
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uint32_t priv : 1; // 9 Privileged sub-region
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uint32_t reserve1 : 22; // 10 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm5bcfgr_t;
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typedef struct {
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uint32_t subb_start: 11; // 0 Start of sub-region A
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uint32_t reserve0 : 5; // 11 Reserve
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uint32_t subb_length: 12; // 16 Length of sub-region A
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uint32_t reserve1 : 4; // 28 Reserve
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} reg_gtzc1_tzsc_tzsc_mpcwm5br_t;
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typedef struct {
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volatile reg_gtzc1_tzsc_tzsc_cr_t tzsc_cr;
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volatile uint32_t reserve0[3];
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volatile reg_gtzc1_tzsc_tzsc_seccfgr1_t tzsc_seccfgr1;
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volatile reg_gtzc1_tzsc_tzsc_seccfgr2_t tzsc_seccfgr2;
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volatile reg_gtzc1_tzsc_tzsc_seccfgr3_t tzsc_seccfgr3;
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volatile uint32_t reserve1[1];
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volatile reg_gtzc1_tzsc_tzsc_privcfgr1_t tzsc_privcfgr1;
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volatile reg_gtzc1_tzsc_tzsc_privcfgr2_t tzsc_privcfgr2;
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volatile reg_gtzc1_tzsc_tzsc_privcfgr3_t tzsc_privcfgr3;
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volatile uint32_t reserve2[5];
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volatile reg_gtzc1_tzsc_tzsc_mpcwm1acfgr_t tzsc_mpcwm1acfgr;
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volatile reg_gtzc1_tzsc_tzsc_mpcwm1ar_t tzsc_mpcwm1ar;
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volatile reg_gtzc1_tzsc_tzsc_mpcwm1bcfgr_t tzsc_mpcwm1bcfgr;
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volatile reg_gtzc1_tzsc_tzsc_mpcwm1br_t tzsc_mpcwm1br;
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volatile reg_gtzc1_tzsc_tzsc_mpcwm2acfgr_t tzsc_mpcwm2acfgr;
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volatile reg_gtzc1_tzsc_tzsc_mpcwm2ar_t tzsc_mpcwm2ar;
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volatile reg_gtzc1_tzsc_tzsc_mpcwm2bcfgr_t tzsc_mpcwm2bcfgr;
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volatile reg_gtzc1_tzsc_tzsc_mpcwm2br_t tzsc_mpcwm2br;
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volatile reg_gtzc1_tzsc_tzsc_mpcwm3acfgr_t tzsc_mpcwm3acfgr;
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volatile reg_gtzc1_tzsc_tzsc_mpcwm3ar_t tzsc_mpcwm3ar;
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volatile uint32_t reserve3[2];
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volatile reg_gtzc1_tzsc_tzsc_mpcwm4acfgr_t tzsc_mpcwm4acfgr;
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volatile reg_gtzc1_tzsc_tzsc_mpcwm4ar_t tzsc_mpcwm4ar;
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volatile uint32_t reserve4[2];
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volatile reg_gtzc1_tzsc_tzsc_mpcwm5acfgr_t tzsc_mpcwm5acfgr;
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volatile reg_gtzc1_tzsc_tzsc_mpcwm5ar_t tzsc_mpcwm5ar;
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volatile reg_gtzc1_tzsc_tzsc_mpcwm5bcfgr_t tzsc_mpcwm5bcfgr;
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volatile reg_gtzc1_tzsc_tzsc_mpcwm5br_t tzsc_mpcwm5br;
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} reg_gtzc1_tzsc_t;
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