411 lines
56 KiB
C
Executable File
411 lines
56 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t cen : 1; // 0 Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
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uint32_t udis : 1; // 1 Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
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uint32_t urs : 1; // 2 Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
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uint32_t opm : 1; // 3 One pulse mode
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uint32_t dir : 1; // 4 Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
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uint32_t cms : 2; // 5 Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)
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uint32_t arpe : 1; // 7 Auto-reload preload enable
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uint32_t ckd : 2; // 8 Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (tim_etr_in, tim_tix),
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uint32_t reserve0 : 1; // 10 Reserve
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uint32_t uifremap : 1; // 11 UIF status bit remapping
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uint32_t dithen : 1; // 12 Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset.
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uint32_t reserve1 : 3; // 13 Reserve
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} reg_tim__cr1_t;
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typedef struct {
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uint32_t ccpc : 1; // 0 Capture/compare preloaded control
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uint32_t reserve0 : 1; // 1 Reserve
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uint32_t ccus : 1; // 2 Capture/compare control update selection
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uint32_t ccds : 1; // 3 Capture/compare DMA selection
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uint32_t mms0_2 : 3; // 4 Master mode selection
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uint32_t ti1s : 1; // 7 TI1 selection
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uint32_t ois1 : 1; // 8 Output Idle state 1
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uint32_t ois1n : 1; // 9 Output Idle state 1
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uint32_t ois2 : 1; // 10 Output Idle state 2
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uint32_t ois2n : 1; // 11 Output Idle state 2
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uint32_t ois3 : 1; // 12 Output Idle state 3
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uint32_t ois3n : 1; // 13 Output Idle state 3
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uint32_t ois4 : 1; // 14 Output Idle state 4
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uint32_t ois4n : 1; // 15 Output Idle state 4 (OC5 output)
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uint32_t ois5 : 1; // 16 Output Idle state 5
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uint32_t reserve1 : 1; // 17 Reserve
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uint32_t ois6 : 1; // 18 Output Idle state 6
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uint32_t reserve2 : 1; // 19 Reserve
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uint32_t mms2 : 4; // 20 Master mode selection 2
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uint32_t reserve3 : 1; // 24 Reserve
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uint32_t mms_3 : 1; // 25 Master mode selection 2
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uint32_t reserve4 : 6; // 26 Reserve
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} reg_tim__cr2_t;
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typedef struct {
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uint32_t sms1 : 3; // 0 Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo or the tim_trgo2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
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uint32_t occs : 1; // 3 OCREF clear selection This bit is used to select the OCREF clear source.
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uint32_t ts1 : 3; // 4 Trigger selection - bit 4:3 Refer to TS[2:0] description - bits 6:4 null Trigger selection This bitfield is combined with TS[4:3] bits. This bit-field selects the trigger input to be used to synchronize the counter. others: Reserved See for more details on tim_itrx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
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uint32_t msm : 1; // 7 Master/slave mode
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uint32_t etf : 4; // 8 External trigger filter This bit-field then defines the frequency used to sample tim_etrp signal and the length of the digital filter applied to tim_etrp. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
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uint32_t etps : 2; // 12 External trigger prescaler External trigger signal tim_etrp frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce tim_etrp frequency. It is useful when inputting fast external clocks on tim_etr_in.
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uint32_t ece : 1; // 14 External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with tim_trgi connected to tim_etrf (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, tim_trgi must not be connected to tim_etrf in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is tim_etrf.
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uint32_t etp : 1; // 15 External trigger polarity This bit selects whether tim_etr_in or tim_etr_in is used for trigger operations
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uint32_t sms2 : 1; // 16 Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the tim_trgo or the tim_trgo2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
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uint32_t reserve0 : 3; // 17 Reserve
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uint32_t ts2 : 2; // 20 Trigger selection - bit 4:3 Refer to TS[2:0] description - bits 6:4 null Trigger selection This bitfield is combined with TS[4:3] bits. This bit-field selects the trigger input to be used to synchronize the counter. others: Reserved See for more details on tim_itrx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
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uint32_t reserve1 : 2; // 22 Reserve
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uint32_t smspe : 1; // 24 SMS preload enable This bit selects whether the SMS[3:0] bitfield is preloaded
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uint32_t smsps : 1; // 25 SMS preload source This bit selects whether the events that triggers the SMS[3:0] bitfield transfer from preload to active
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uint32_t reserve2 : 6; // 26 Reserve
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} reg_tim__smcr_t;
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typedef struct {
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uint32_t uie : 1; // 0 Update interrupt enable
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uint32_t cc1ie : 1; // 1 Capture/compare 1 interrupt enable
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uint32_t cc2ie : 1; // 2 Capture/compare 2 interrupt enable
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uint32_t cc3ie : 1; // 3 Capture/compare 3 interrupt enable
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uint32_t cc4ie : 1; // 4 Capture/compare 4 interrupt enable
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uint32_t comie : 1; // 5 COM interrupt enable
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uint32_t tie : 1; // 6 Trigger interrupt enable
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uint32_t bie : 1; // 7 Break interrupt enable
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uint32_t ude : 1; // 8 Update DMA request enable
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uint32_t cc1de : 1; // 9 Capture/compare 1 DMA request enable
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uint32_t cc2de : 1; // 10 Capture/compare 2 DMA request enable
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uint32_t cc3de : 1; // 11 Capture/compare 3 DMA request enable
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uint32_t cc4de : 1; // 12 Capture/compare 4 DMA request enable
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uint32_t comde : 1; // 13 COM DMA request enable
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uint32_t tde : 1; // 14 Trigger DMA request enable
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uint32_t reserve0 : 5; // 15 Reserve
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uint32_t idxie : 1; // 20 Index interrupt enable
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uint32_t dirie : 1; // 21 Direction change interrupt enable
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uint32_t ierrie : 1; // 22 Index error interrupt enable
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uint32_t terrie : 1; // 23 Transition error interrupt enable
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uint32_t reserve1 : 8; // 24 Reserve
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} reg_tim__dier_t;
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typedef struct {
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uint32_t uif : 1; // 0 Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIMx_SMCR)(x = 1, 8)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
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uint32_t cc1if : 1; // 1 Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in downcounting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
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uint32_t cc2if : 1; // 2 Capture/compare 2 interrupt flag Refer to CC1IF description
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uint32_t cc3if : 1; // 3 Capture/compare 3 interrupt flag Refer to CC1IF description
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uint32_t cc4if : 1; // 4 Capture/compare 4 interrupt flag Refer to CC1IF description
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uint32_t comif : 1; // 5 COM interrupt flag This flag is set by hardware on COM event (when capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software.
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uint32_t tif : 1; // 6 Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on tim_trgi input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
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uint32_t bif : 1; // 7 Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
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uint32_t b2if : 1; // 8 Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active.
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uint32_t cc1of : 1; // 9 Capture/compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â.
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uint32_t cc2of : 1; // 10 Capture/compare 2 overcapture flag Refer to CC1OF description
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uint32_t cc3of : 1; // 11 Capture/compare 3 overcapture flag Refer to CC1OF description
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uint32_t cc4of : 1; // 12 Capture/compare 4 overcapture flag Refer to CC1OF description
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uint32_t sbif : 1; // 13 System break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation.
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uint32_t reserve0 : 2; // 14 Reserve
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uint32_t cc5if : 1; // 16 Compare 5 interrupt flag Refer to CC1IF description Note: Channel 5 can only be configured as output.
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uint32_t cc6if : 1; // 17 Compare 6 interrupt flag Refer to CC1IF description Note: Channel 6 can only be configured as output.
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uint32_t reserve1 : 2; // 18 Reserve
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uint32_t idxf : 1; // 20 Index interrupt flag This flag is set by hardware when an index event is detected. It is cleared by software by writing it to '0â.
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uint32_t dirf : 1; // 21 Direction change interrupt flag This flag is set by hardware when the direction changes in encoder mode (DIR bit value in TIMx_CR is changing). It is cleared by software by writing it to '0â.
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uint32_t ierrf : 1; // 22 Index error interrupt flag This flag is set by hardware when an index error is detected. It is cleared by software by writing it to '0â.
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uint32_t terrf : 1; // 23 Transition error interrupt flag This flag is set by hardware when a transition error is detected in encoder mode. It is cleared by software by writing it to '0â.
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uint32_t reserve2 : 8; // 24 Reserve
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} reg_tim__sr_t;
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typedef struct {
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uint32_t ug : 1; // 0 Update generation This bit can be set by software, it is automatically cleared by hardware.
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uint32_t cc1g : 1; // 1 Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
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uint32_t cc2g : 1; // 2 Capture/compare 2 generation Refer to CC1G description
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uint32_t cc3g : 1; // 3 Capture/compare 3 generation Refer to CC1G description
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uint32_t cc4g : 1; // 4 Capture/compare 4 generation Refer to CC1G description
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uint32_t comg : 1; // 5 Capture/compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output.
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uint32_t tg : 1; // 6 Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
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uint32_t bg : 1; // 7 Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
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uint32_t b2g : 1; // 8 Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
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uint32_t reserve0 : 7; // 9 Reserve
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} reg_tim__egr_t;
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typedef struct {
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uint32_t cc1s : 2; // 0 Capture/Compare 1 selection
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uint32_t oc1fe : 1; // 2 Output Compare 1 fast enable
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uint32_t oc1pe : 1; // 3 Output Compare 1 preload enable
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uint32_t oc1m : 3; // 4 Output Compare 1 mode
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uint32_t oc1ce : 1; // 7 Output Compare 1 clear enable
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uint32_t cc2s : 2; // 8 Capture/Compare 2 selection
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uint32_t oc2fe : 1; // 10 Output Compare 2 fast enable
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uint32_t oc2pe : 1; // 11 Output Compare 2 preload enable
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uint32_t oc2m : 3; // 12 Output Compare 2 mode
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uint32_t oc2ce : 1; // 15 Output Compare 2 clear enable
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uint32_t oc1m_bit3 : 1; // 16 Output Compare 1 mode - bit 3
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uint32_t reserve0 : 7; // 17 Reserve
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uint32_t oc2m_bit3 : 1; // 24 Output Compare 2 mode - bit 3
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uint32_t reserve1 : 7; // 25 Reserve
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} reg_tim__ccmr1_output_t;
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typedef struct {
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uint32_t cc1s : 2; // 0 Capture/compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER).
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uint32_t ic1psc : 2; // 2 Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (tim_ic1). The prescaler is reset as soon as CC1E=â0â (TIMx_CCER register).
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uint32_t ic1f : 4; // 4 Input capture 1 filter This bit-field defines the frequency used to sample tim_ti1 input and the length of the digital filter applied to tim_ti1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
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uint32_t cc2s : 2; // 8 Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â in TIMx_CCER).
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uint32_t ic2psc : 2; // 10 Input capture 2 prescaler
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uint32_t ic2f : 4; // 12 Input capture 2 filter
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_tim__ccmr1_input_t;
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typedef struct {
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uint32_t cc3s_1_0 : 2; // 0 Capture/Compare 3 selection
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uint32_t oc3fe : 1; // 2 Output compare 3 fast enable
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uint32_t oc3pe : 1; // 3 Output compare 3 preload enable
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uint32_t oc3m_2_0 : 3; // 4 Output compare 3 mode
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uint32_t oc3ce : 1; // 7 Output compare 3 clear enable
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uint32_t cc4s_1_0 : 2; // 8 Capture/Compare 4 selection
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uint32_t oc4fe : 1; // 10 Output compare 4 fast enable
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uint32_t oc4pe : 1; // 11 Output compare 4 preload enable
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uint32_t oc4m_3_0 : 3; // 12 Output compare 4 mode
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uint32_t oc4ce : 1; // 15 Output compare 4 clear enable
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uint32_t oc3m_3 : 1; // 16 Output compare 3 mode
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uint32_t reserve0 : 7; // 17 Reserve
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uint32_t oc4m_bit3 : 1; // 24 Output Compare 4 mode - bit 3
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uint32_t reserve1 : 7; // 25 Reserve
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} reg_tim__ccmr2_output_t;
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typedef struct {
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uint32_t cc3s : 2; // 0 Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0â in TIMx_CCER).
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uint32_t ic3psc : 2; // 2 Input capture 3 prescaler
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uint32_t ic3f : 4; // 4 Input capture 3 filter
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uint32_t cc4s : 2; // 8 Capture/compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0â in TIMx_CCER).
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uint32_t ic4psc : 2; // 10 Input capture 4 prescaler
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uint32_t ic4f : 4; // 12 Input capture 4 filter
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_tim__ccmr2_input_t;
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typedef struct {
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uint32_t cc1e : 1; // 0 Capture/compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated.
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uint32_t cc1p : 1; // 1 Capture/compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: the configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.
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uint32_t cc1ne : 1; // 2 Capture/compare 1 complementary output enable Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated.
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uint32_t cc1np : 1; // 3 Capture/compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of tim_ti1fp1 and tim_ti2fp1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (channel configured as output). Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated.
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uint32_t cc2e : 1; // 4 Capture/compare 2 output enable Refer to CC1E description
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uint32_t cc2p : 1; // 5 Capture/compare 2 output polarity Refer to CC1P description
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uint32_t cc2ne : 1; // 6 Capture/compare 2 complementary output enable Refer to CC1NE description
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uint32_t cc2np : 1; // 7 Capture/compare 2 complementary output polarity Refer to CC1NP description
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uint32_t cc3e : 1; // 8 Capture/compare 3 output enable Refer to CC1E description
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uint32_t cc3p : 1; // 9 Capture/compare 3 output polarity Refer to CC1P description
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uint32_t cc3ne : 1; // 10 Capture/compare 3 complementary output enable Refer to CC1NE description
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uint32_t cc3np : 1; // 11 Capture/compare 3 complementary output polarity Refer to CC1NP description
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uint32_t cc4e : 1; // 12 Capture/compare 4 output enable Refer to CC1E description
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uint32_t cc4p : 1; // 13 Capture/compare 4 output polarity Refer to CC1P description
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uint32_t cc4ne : 1; // 14 Capture/compare 4 complementary output enable Refer to CC1NE description
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uint32_t cc4np : 1; // 15 Capture/compare 4 complementary output polarity Refer to CC1NP description
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uint32_t cc5e : 1; // 16 Capture/compare 5 output enable Refer to CC1E description
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uint32_t cc5p : 1; // 17 Capture/compare 5 output polarity Refer to CC1P description
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uint32_t reserve0 : 2; // 18 Reserve
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uint32_t cc6e : 1; // 20 Capture/compare 6 output enable Refer to CC1E description
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uint32_t cc6p : 1; // 21 Capture/compare 6 output polarity Refer to CC1P description
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uint32_t reserve1 : 10; // 22 Reserve
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} reg_tim__ccer_t;
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typedef struct {
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uint32_t cnt : 16; // 0 Counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register only holds the non-dithered part in CNT[15:0]. The fractional part is not available.
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uint32_t reserve0 : 15; // 16 Reserve
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uint32_t uifcpy : 1; // 31 UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.
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} reg_tim__cnt_t;
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typedef struct {
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uint32_t psc : 16; // 0 Prescaler value The counter clock frequency (ftim_cnt_ck) is equal to ftim_psc_ck / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in âreset modeâ).
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} reg_tim__psc_t;
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typedef struct {
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uint32_t arr : 20; // 0 Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part.
|
||
uint32_t reserve0 : 12; // 20 Reserve
|
||
} reg_tim__arr_t;
|
||
|
||
typedef struct {
|
||
uint32_t rep : 16; // 0 Repetition counter reload value This bitfield defines the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable. It also defines the update interrupt generation rate, if this interrupt is enable. When the repetition down-counter reaches zero, an update event is generated and it restarts counting from REP value. As the repetition counter is reloaded with REP value only at the repetition update event UEV, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode.
|
||
} reg_tim__rcr_t;
|
||
|
||
typedef struct {
|
||
uint32_t ccr1 : 20; // 0 Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on tim_oc1 output. Non-dithering mode (DITHEN = 0) The register holds the compare value in CCR1[15:0]. The CCR1[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the integer part in CCR1[19:4]. The CCR1[3:0] bitfield contains the dithered part. If channel CC1 is configured as input: CR1 is the counter value transferred by the last input capture 1 event (tim_ic1). The TIMx_CCR1 register is read-only and cannot be programmed. Non-dithering mode (DITHEN = 0) The register holds the capture value in CCR1[15:0]. The CCR1[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the capture in CCR1[19:4]. The CCR1[3:0] bits are reset.
|
||
uint32_t reserve0 : 12; // 20 Reserve
|
||
} reg_tim__ccr1_t;
|
||
|
||
typedef struct {
|
||
uint32_t ccr2 : 20; // 0 Capture/compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on tim_oc2 output. Non-dithering mode (DITHEN = 0) The register holds the compare value in CCR2[15:0]. The CCR2[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the integer part in CCR2[19:4]. The CCR2[3:0] bitfield contains the dithered part. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (tim_ic2). The TIMx_CCR2 register is read-only and cannot be programmed. Non-dithering mode (DITHEN = 0) The register holds the capture value in CCR2[15:0]. The CCR2[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the capture in CCR2[19:4]. The CCR2[3:0] bits are reset.
|
||
uint32_t reserve0 : 12; // 20 Reserve
|
||
} reg_tim__ccr2_t;
|
||
|
||
typedef struct {
|
||
uint32_t ccr3 : 20; // 0 Capture/compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on tim_oc3 output. Non-dithering mode (DITHEN = 0) The register holds the compare value in CCR3[15:0]. The CCR3[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the integer part in CCR3[19:4]. The CCR3[3:0] bitfield contains the dithered part. If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (tim_ic3). The TIMx_CCR3 register is read-only and cannot be programmed. Non-dithering mode (DITHEN = 0) The register holds the capture value in CCR3[15:0]. The CCR3[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the capture in CCR3[19:4]. The CCR3[3:0] bits are reset.
|
||
uint32_t reserve0 : 12; // 20 Reserve
|
||
} reg_tim__ccr3_t;
|
||
|
||
typedef struct {
|
||
uint32_t ccr4 : 20; // 0 Capture/compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on tim_oc4 output. Non-dithering mode (DITHEN = 0) The register holds the compare value in CCR4[15:0]. The CCR4[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the integer part in CCR4[19:4]. The CCR4[3:0] bitfield contains the dithered part. If channel CC4 is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (tim_ic4). The TIMx_CCR4 register is read-only and cannot be programmed. Non-dithering mode (DITHEN = 0) The register holds the capture value in CCR4[15:0]. The CCR4[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the capture in CCR4[19:4]. The CCR4[3:0] bits are reset.
|
||
uint32_t reserve0 : 12; // 20 Reserve
|
||
} reg_tim__ccr4_t;
|
||
|
||
typedef struct {
|
||
uint32_t dtg : 8; // 0 Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS. DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS. DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS. DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS. Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t lock : 2; // 8 Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
|
||
uint32_t ossi : 1; // 10 Off-state selection for idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIMx_CCER)(x = 1, 8)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t ossr : 1; // 11 Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIMx_CCER)(x = 1, 8)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bke : 1; // 12 Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
|
||
uint32_t bkp : 1; // 13 Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
|
||
uint32_t aoe : 1; // 14 Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t moe : 1; // 15 Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (tim_brk or tim_brk2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. enable register (TIMx_CCER)(x = 1, 8)).
|
||
uint32_t bkf : 4; // 16 Break filter This bit-field defines the frequency used to sample tim_brk input and the length of the digital filter applied to tim_brk. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bk2f : 4; // 20 Break 2 filter This bit-field defines the frequency used to sample tim_brk2 input and the length of the digital filter applied to tim_brk2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bk2e : 1; // 24 Break 2 enable This bit enables the complete break 2 protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: The BRKIN2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
|
||
uint32_t bk2p : 1; // 25 Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
|
||
uint32_t bkdsrm : 1; // 26 Break disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
|
||
uint32_t bk2dsrm : 1; // 27 Break2 disarm Refer to BKDSRM description
|
||
uint32_t bkbid : 1; // 28 Break bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
|
||
uint32_t bk2bid : 1; // 29 Break2 bidirectional Refer to BKBID description
|
||
uint32_t reserve0 : 2; // 30 Reserve
|
||
} reg_tim__bdtr_t;
|
||
|
||
typedef struct {
|
||
uint32_t ccr5 : 20; // 0 Capture/compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on tim_oc5 output. Non-dithering mode (DITHEN = 0) The register holds the compare value in CCR5[15:0]. The CCR5[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the integer part in CCR5[19:4]. The CCR5[3:0] bitfield contains the dithered part.
|
||
uint32_t reserve0 : 9; // 20 Reserve
|
||
uint32_t gc5c1 : 1; // 29 Group channel 5 and channel 1 Distortion on channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals.
|
||
uint32_t gc5c2 : 1; // 30 Group channel 5 and channel 2 Distortion on channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals.
|
||
uint32_t gc5c3 : 1; // 31 Group channel 5 and channel 3 Distortion on channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals.
|
||
} reg_tim__ccr5_t;
|
||
|
||
typedef struct {
|
||
uint32_t ccr6 : 20; // 0 Capture/compare 6 value CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on tim_oc6 output. Non-dithering mode (DITHEN = 0) The register holds the compare value in CCR6[15:0]. The CCR6[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the integer part in CCR6[19:4]. The CCR6[3:0] bitfield contains the dithered part.
|
||
uint32_t reserve0 : 12; // 20 Reserve
|
||
} reg_tim__ccr6_t;
|
||
|
||
typedef struct {
|
||
uint32_t reserve0 : 2; // 0 Reserve
|
||
uint32_t oc5fe : 1; // 2 Output compare 5 fast enable
|
||
uint32_t oc5pe : 1; // 3 Output compare 5 preload enable
|
||
uint32_t oc5m1 : 3; // 4 Output compare 5 mode
|
||
uint32_t oc5ce : 1; // 7 Output compare 5 clear enable
|
||
uint32_t reserve1 : 2; // 8 Reserve
|
||
uint32_t oc6fe : 1; // 10 Output compare 6 fast enable
|
||
uint32_t oc6pe : 1; // 11 Output compare 6 preload enable
|
||
uint32_t oc6m1 : 3; // 12 Output compare 6 mode
|
||
uint32_t oc6ce : 1; // 15 Output compare 6 clear enable
|
||
uint32_t oc5m2 : 1; // 16 Output compare 5 mode
|
||
uint32_t reserve2 : 7; // 17 Reserve
|
||
uint32_t oc6m2 : 1; // 24 Output compare 6 mode
|
||
uint32_t reserve3 : 7; // 25 Reserve
|
||
} reg_tim__ccmr3_t;
|
||
|
||
typedef struct {
|
||
uint32_t dtgf : 8; // 0 Dead-time falling edge generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs, on the falling edge. DTGF[7:5]=0xx => DTF=DTGF[7:0]x tdtg with tdtg=tDTS. DTGF[7:5]=10x => DTF=(64+DTGF[5:0])xtdtg with Tdtg=2xtDTS. DTGF[7:5]=110 => DTF=(32+DTGF[4:0])xtdtg with Tdtg=8xtDTS. DTGF[7:5]=111 => DTF=(32+DTGF[4:0])xtdtg with Tdtg=16xtDTS. Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t reserve0 : 8; // 8 Reserve
|
||
uint32_t dtae : 1; // 16 Deadtime asymmetric enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t dtpe : 1; // 17 Deadtime preload enable Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t reserve1 : 14; // 18 Reserve
|
||
} reg_tim__dtr2_t;
|
||
|
||
typedef struct {
|
||
uint32_t ie : 1; // 0 Index enable This bit indicates if the Index event resets the counter.
|
||
uint32_t idir : 2; // 1 Index direction This bit indicates in which direction the Index event resets the counter. Note: The IDR[1:0] bitfield must be written when IE bit is reset (index disabled).
|
||
uint32_t iblk : 2; // 3 Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input
|
||
uint32_t fidx : 1; // 5 First index This bit indicates if the first index only is taken into account
|
||
uint32_t ipos : 2; // 6 Index positioning In quadrature encoder mode (SMS[3:0] = 0001, 0010, 0011, 1110, 1111), this bit indicates in which AB input configuration the Index event resets the counter. In directional clock mode or clock plus direction mode (SMS[3:0] = 1010, 1011, 1100, 1101), these bits indicates on which level the Index event resets the counter. In bidirectional clock mode, this applies for both clock inputs. x0: Index resets the counter when clock is 0 x1: Index resets the counter when clock is 1 Note: IPOS[1]âbit is not significant
|
||
uint32_t reserve0 : 8; // 8 Reserve
|
||
uint32_t pw : 8; // 16 Pulse width This bitfield defines the pulse duration, as following: tPW = PW[7:0] x tPWG
|
||
uint32_t pwprsc : 3; // 24 Pulse width prescaler This bitfield sets the clock prescaler for the pulse generator, as following: tPWG = (2(PWPRSC[2:0])) x ttim_ker_ck
|
||
uint32_t reserve1 : 5; // 27 Reserve
|
||
} reg_tim__ecr_t;
|
||
|
||
typedef struct {
|
||
uint32_t ti1sel : 4; // 0 Selects tim_ti1[0..15] input ... Refer to for interconnects list.
|
||
uint32_t reserve0 : 4; // 4 Reserve
|
||
uint32_t ti2sel : 4; // 8 Selects tim_ti2[0..15] input ... Refer to for interconnects list.
|
||
uint32_t reserve1 : 4; // 12 Reserve
|
||
uint32_t ti3sel : 4; // 16 Selects tim_ti3[0..15] input ... Refer to for interconnects list.
|
||
uint32_t reserve2 : 4; // 20 Reserve
|
||
uint32_t ti4sel : 4; // 24 Selects tim_ti4[0..15] input ... Refer to for interconnects list.
|
||
uint32_t reserve3 : 4; // 28 Reserve
|
||
} reg_tim__tisel_t;
|
||
|
||
typedef struct {
|
||
uint32_t bkine : 1; // 0 TIMx_BKIN input enable This bit enables the TIMx_BKIN alternate function input for the timerâs tim_brk input. TIMx_BKIN input is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bkcmp1e : 1; // 1 tim_brk_cmp1 enable This bit enables the tim_brk_cmp1 for the timerâs tim_brk input. tim_brk_cmp1 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bkcmp2e : 1; // 2 tim_brk_cmp2 enable This bit enables the tim_brk_cmp2 for the timerâs tim_brk input. tim_brk_cmp2 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bkcmp3e : 1; // 3 tim_brk_cmp3 enable This bit enables the tim_brk_cmp3 for the timerâs tim_brk input. tim_brk_cmp3 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bkcmp4e : 1; // 4 tim_brk_cmp4 enable This bit enables the tim_brk_cmp4 for the timerâs tim_brk input. tim_brk_cmp4 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bkcmp5e : 1; // 5 tim_brk_cmp5 enable This bit enables the tim_brk_cmp5 for the timerâs tim_brk input. tim_brk_cmp5 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bkcmp6e : 1; // 6 tim_brk_cmp6 enable This bit enables the tim_brk_cmp6 for the timerâs tim_brk input. tim_brk_cmp6 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bkcmp7e : 1; // 7 tim_brk_cmp7 enable This bit enables the tim_brk_cmp7 for the timerâs tim_brk input. tim_brk_cmp7 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bkcmp8e : 1; // 8 tim_brk_cmp8 enable This bit enables the tim_brk_cmp8 for the timerâs tim_brk input. tim_brk_cmp8 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bkinp : 1; // 9 TIMx_BKIN input polarity This bit selects the TIMx_BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bkcmp1p : 1; // 10 tim_brk_cmp1 input polarity This bit selects the tim_brk_cmp1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bkcmp2p : 1; // 11 tim_brk_cmp2 input polarity This bit selects the tim_brk_cmp2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bkcmp3p : 1; // 12 tim_brk_cmp3 input polarity This bit selects the tim_brk_cmp3 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bkcmp4p : 1; // 13 tim_brk_cmp4 input polarity This bit selects the tim_brk_cmp4 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t etrsel : 4; // 14 etr_in source selection These bits select the etr_in input source. ... Refer to for product specific implementation. Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t reserve0 : 14; // 18 Reserve
|
||
} reg_tim__af1_t;
|
||
|
||
typedef struct {
|
||
uint32_t bk2ine : 1; // 0 TIMx_BKIN2 input enable This bit enables the TIMx_BKIN2 alternate function input for the timerâs tim_brk2 input. TIMx_BKIN2 input is 'ORedâ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bk2cmp1e : 1; // 1 tim_brk2_cmp1 enable This bit enables the tim_brk2_cmp1 for the timerâs tim_brk2 input. tim_brk2_cmp1 output is 'ORedâ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bk2cmp2e : 1; // 2 tim_brk2_cmp2 enable This bit enables the tim_brk2_cmp2 for the timerâs tim_brk2 input. tim_brk2_cmp2 output is 'ORedâ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bk2cmp3e : 1; // 3 tim_brk2_cmp3 enable This bit enables the tim_brk2_cmp3 for the timerâs tim_brk2 input. tim_brk2_cmp3 output is 'ORedâ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bk2cmp4e : 1; // 4 tim_brk2_cmp4 enable This bit enables the tim_brk2_cmp4 for the timerâs tim_brk2 input. tim_brk2_cmp4 output is 'ORedâ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bk2cmp5e : 1; // 5 tim_brk2_cmp5 enable This bit enables the tim_brk2_cmp5 for the timerâs tim_brk2 input. tim_brk2_cmp5 output is 'ORedâ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
|
||
uint32_t bk2cmp6e : 1; // 6 tim_brk2_cmp6 enable This bit enables the tim_brk2_cmp6 for the timerâs tim_brk2 input. tim_brk2_cmp6 output is 'ORedâ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
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uint32_t bk2cmp7e : 1; // 7 tim_brk2_cmp7 enable This bit enables the tim_brk2_cmp7 for the timerâs tim_brk2 input. tim_brk2_cmp7 output is 'ORedâ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
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uint32_t bk2cmp8e : 1; // 8 tim_brk2_cmp8 enable This bit enables the tim_brk2_cmp8 for the timerâs tim_brk2 input. tim_brk2_cmp8 output is 'ORedâ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
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uint32_t bk2inp : 1; // 9 TIMx_BKIN2 input polarity This bit selects the TIMx_BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
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uint32_t bk2cmp1p : 1; // 10 tim_brk2_cmp1 input polarity This bit selects the tim_brk2_cmp1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
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uint32_t bk2cmp2p : 1; // 11 tim_brk2_cmp2 input polarity This bit selects the tim_brk2_cmp2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
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uint32_t bk2cmp3p : 1; // 12 tim_brk2_cmp3 input polarity This bit selects the tim_brk2_cmp3 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
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uint32_t bk2cmp4p : 1; // 13 tim_brk2_cmp4 input polarity This bit selects the tim_brk2_cmp4 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
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uint32_t reserve0 : 2; // 14 Reserve
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uint32_t ocrsel : 3; // 16 ocref_clr source selection These bits select the ocref_clr input source. ... Refer to for product specific information. Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
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uint32_t reserve1 : 13; // 19 Reserve
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} reg_tim__af2_t;
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typedef struct {
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uint32_t dba : 5; // 0 DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ...
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uint32_t reserve0 : 3; // 5 Reserve
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uint32_t dbl : 5; // 8 DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIM2_CR1. If DBL = 7 bytes and DBA = TIM2_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data are copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data are transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data are also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA.
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uint32_t reserve1 : 3; // 13 Reserve
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uint32_t dbss : 4; // 16 DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). Others: reserved
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uint32_t reserve2 : 12; // 20 Reserve
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} reg_tim__dcr_t;
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typedef struct {
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uint32_t dmab : 32; // 0 DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
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} reg_tim__dmar_t;
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typedef struct {
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volatile reg_tim__cr1_t _cr1;
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volatile reg_tim__cr2_t _cr2;
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volatile reg_tim__smcr_t _smcr;
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volatile reg_tim__dier_t _dier;
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volatile reg_tim__sr_t _sr;
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volatile reg_tim__egr_t _egr;
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volatile reg_tim__ccmr1_output_t _ccmr1_output;
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volatile uint32_t reserve0[-1];
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volatile reg_tim__ccmr1_input_t _ccmr1_input;
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volatile reg_tim__ccmr2_output_t _ccmr2_output;
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volatile uint32_t reserve1[-1];
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volatile reg_tim__ccmr2_input_t _ccmr2_input;
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volatile reg_tim__ccer_t _ccer;
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volatile reg_tim__cnt_t _cnt;
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volatile reg_tim__psc_t _psc;
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volatile reg_tim__arr_t _arr;
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volatile reg_tim__rcr_t _rcr;
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volatile reg_tim__ccr1_t _ccr1;
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volatile reg_tim__ccr2_t _ccr2;
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volatile reg_tim__ccr3_t _ccr3;
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volatile reg_tim__ccr4_t _ccr4;
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volatile reg_tim__bdtr_t _bdtr;
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volatile reg_tim__ccr5_t _ccr5;
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volatile reg_tim__ccr6_t _ccr6;
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volatile reg_tim__ccmr3_t _ccmr3;
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volatile reg_tim__dtr2_t _dtr2;
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volatile reg_tim__ecr_t _ecr;
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volatile reg_tim__tisel_t _tisel;
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volatile reg_tim__af1_t _af1;
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volatile reg_tim__af2_t _af2;
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volatile uint32_t reserve2[221];
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volatile reg_tim__dcr_t _dcr;
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volatile reg_tim__dmar_t _dmar;
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} reg_tim_t;
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