257 lines
11 KiB
C
Executable File
257 lines
11 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t cen : 1; // 0 Counter enable
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uint32_t udis : 1; // 1 Update disable
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uint32_t urs : 1; // 2 Update request source
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uint32_t opm : 1; // 3 One-pulse mode
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uint32_t reserve0 : 3; // 4 Reserve
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uint32_t arpe : 1; // 7 Auto-reload preload enable
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uint32_t ckd : 2; // 8 Clock division
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uint32_t reserve1 : 1; // 10 Reserve
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uint32_t uifremap : 1; // 11 UIF status bit remapping
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uint32_t dithen : 1; // 12 Dithering enable
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uint32_t reserve2 : 19; // 13 Reserve
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} reg_tim1_cr1_t;
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typedef struct {
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uint32_t ccpc : 1; // 0 Capture/compare preloaded control
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uint32_t reserve0 : 1; // 1 Reserve
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uint32_t ccus : 1; // 2 Capture/compare control update selection
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uint32_t ccds : 1; // 3 Capture/compare DMA selection
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uint32_t mms : 2; // 4 Master mode selection
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uint32_t reserve1 : 1; // 6 Reserve
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uint32_t ti1s : 1; // 7 TI1 selection
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uint32_t ois1 : 1; // 8 Output Idle state 1
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uint32_t ois1n : 1; // 9 Output Idle state 1
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uint32_t ois2 : 1; // 10 Output idle state 2 (OC2 output)
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uint32_t reserve2 : 21; // 11 Reserve
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} reg_tim1_cr2_t;
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typedef struct {
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uint32_t sms : 3; // 0 Slave mode selection
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t ts_2_0 : 3; // 4 Trigger selection
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uint32_t msm : 1; // 7 Master/slave mode
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uint32_t reserve1 : 1; // 8 Reserve
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uint32_t cc1de : 1; // 9 Capture/Compare 1 DMA request enable
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uint32_t reserve2 : 6; // 10 Reserve
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uint32_t sms_3 : 1; // 16 Slave mode selection
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uint32_t reserve3 : 3; // 17 Reserve
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uint32_t ts_4_3 : 2; // 20 Trigger selection
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uint32_t reserve4 : 10; // 22 Reserve
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} reg_tim1_smcr_t;
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typedef struct {
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uint32_t uie : 1; // 0 Update interrupt enable
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uint32_t cc1ie : 1; // 1 Capture/Compare 1 interrupt enable
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uint32_t cc2ie : 1; // 2 Capture/Compare 2 interrupt enable
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uint32_t reserve0 : 2; // 3 Reserve
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uint32_t comie : 1; // 5 COM interrupt enable
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uint32_t tie : 1; // 6 Trigger interrupt enable
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uint32_t bie : 1; // 7 Break interrupt enable
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uint32_t ude : 1; // 8 Update DMA request enable
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uint32_t cc1de : 1; // 9 Capture/Compare 1 DMA request enable
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uint32_t cc2de : 1; // 10 Capture/Compare 2 DMA request enable
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uint32_t reserve1 : 2; // 11 Reserve
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uint32_t comde : 1; // 13 COM DMA request enable
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uint32_t tde : 1; // 14 Trigger DMA request enable
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uint32_t reserve2 : 17; // 15 Reserve
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} reg_tim1_dier_t;
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typedef struct {
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uint32_t uif : 1; // 0 Update interrupt flag
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uint32_t cc1if : 1; // 1 Capture/compare 1 interrupt flag
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uint32_t cc2if : 1; // 2 Capture/Compare 2 interrupt flag
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uint32_t reserve0 : 2; // 3 Reserve
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uint32_t comif : 1; // 5 COM interrupt flag
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uint32_t tif : 1; // 6 Trigger interrupt flag
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uint32_t bif : 1; // 7 Break interrupt flag
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uint32_t reserve1 : 1; // 8 Reserve
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uint32_t cc1of : 1; // 9 Capture/Compare 1 overcapture flag
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uint32_t cc2of : 1; // 10 Capture/Compare 2 overcapture flag
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uint32_t reserve2 : 21; // 11 Reserve
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} reg_tim1_sr_t;
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typedef struct {
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uint32_t ug : 1; // 0 Update generation
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uint32_t cc1g : 1; // 1 Capture/compare 1 generation
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uint32_t cc2g : 1; // 2 Capture/Compare 2 generation
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uint32_t reserve0 : 2; // 3 Reserve
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uint32_t comg : 1; // 5 Capture/Compare control update generation
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uint32_t tg : 1; // 6 Trigger generation
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uint32_t bg : 1; // 7 Break generation
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uint32_t reserve1 : 24; // 8 Reserve
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} reg_tim1_egr_t;
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typedef struct {
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uint32_t cc1s : 2; // 0 Capture/Compare 1 selection
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uint32_t oc1fe : 1; // 2 Output Compare 1 fast enable
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uint32_t oc1pe : 1; // 3 Output Compare 1 preload enable
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uint32_t oc1m : 3; // 4 Output Compare 1 mode
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uint32_t oc1ce : 1; // 7 Output compare 1 clear enable
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uint32_t cc2s : 2; // 8 Capture/Compare 2 selection
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uint32_t oc2fe : 1; // 10 Output compare 2 fast enable
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uint32_t oc2pe : 1; // 11 Output Compare 2 preload enable
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uint32_t oc2m : 3; // 12 Output Compare 2 mode
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uint32_t reserve0 : 1; // 15 Reserve
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uint32_t oc1m_bit3 : 1; // 16 Output Compare 1 mode
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uint32_t reserve1 : 7; // 17 Reserve
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uint32_t oc2m_bit3 : 1; // 24 Output Compare 2 mode - bit 3
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uint32_t reserve2 : 7; // 25 Reserve
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} reg_tim1_ccmr1_output_t;
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typedef struct {
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uint32_t cc1s : 2; // 0 Capture/Compare 1 selection
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uint32_t ic1psc : 2; // 2 Input capture 1 prescaler
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uint32_t ic1f : 4; // 4 Input capture 1 filter
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uint32_t cc2s : 2; // 8 Capture/Compare 2 selection
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uint32_t ic2psc : 2; // 10 Input capture 2 prescaler
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uint32_t ic2f : 4; // 12 Input capture 2 filter
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_tim1_ccmr1_input_t;
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typedef struct {
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uint32_t cc1e : 1; // 0 Capture/Compare 1 output enable
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uint32_t cc1p : 1; // 1 Capture/Compare 1 output Polarity
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uint32_t cc1ne : 1; // 2 Capture/Compare 1 complementary output enable
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uint32_t cc1np : 1; // 3 Capture/Compare 1 output Polarity
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uint32_t cc2e : 1; // 4 Capture/Compare 2 output enable
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uint32_t cc2p : 1; // 5 Capture/Compare 2 output polarity
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uint32_t reserve0 : 1; // 6 Reserve
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uint32_t cc2np : 1; // 7 Capture/Compare 2 complementary output polarity
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uint32_t reserve1 : 24; // 8 Reserve
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} reg_tim1_ccer_t;
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typedef struct {
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uint32_t cnt : 16; // 0 counter value
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uint32_t reserve0 : 15; // 16 Reserve
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uint32_t uifcpy : 1; // 31 UIF Copy
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} reg_tim1_cnt_t;
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typedef struct {
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uint32_t psc : 16; // 0 Prescaler value
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_tim1_psc_t;
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typedef struct {
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uint32_t arr : 20; // 0 Auto-reload value
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uint32_t reserve0 : 12; // 20 Reserve
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} reg_tim1_arr_t;
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typedef struct {
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uint32_t rep : 8; // 0 Repetition counter value
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uint32_t reserve0 : 24; // 8 Reserve
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} reg_tim1_rcr_t;
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typedef struct {
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uint32_t ccr1 : 20; // 0 Capture/Compare 1 value
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uint32_t reserve0 : 12; // 20 Reserve
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} reg_tim1_ccr1_t;
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typedef struct {
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uint32_t ccr1 : 20; // 0 Capture/Compare 1 value
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uint32_t reserve0 : 12; // 20 Reserve
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} reg_tim1_ccr2_t;
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typedef struct {
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uint32_t dtg : 8; // 0 Dead-time generator setup
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uint32_t lock : 2; // 8 Lock configuration
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uint32_t ossi : 1; // 10 Off-state selection for Idle mode
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uint32_t ossr : 1; // 11 Off-state selection for Run mode
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uint32_t bke : 1; // 12 Break enable
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uint32_t bkp : 1; // 13 Break polarity
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uint32_t aoe : 1; // 14 Automatic output enable
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uint32_t moe : 1; // 15 Main output enable
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uint32_t bkf : 4; // 16 Break filter
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uint32_t reserve0 : 6; // 20 Reserve
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uint32_t bkdsrm : 1; // 26 Break Disarm
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uint32_t reserve1 : 1; // 27 Reserve
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uint32_t bkbid : 1; // 28 Break Bidirectional
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uint32_t reserve2 : 3; // 29 Reserve
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} reg_tim1_bdtr_t;
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typedef struct {
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uint32_t dtgf : 8; // 0 Dead-time falling edge generator setup
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uint32_t reserve0 : 8; // 8 Reserve
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uint32_t dtae : 1; // 16 Deadtime asymmetric enable
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uint32_t dtpe : 1; // 17 Deadtime preload enable
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uint32_t reserve1 : 14; // 18 Reserve
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} reg_tim1_dtr2_t;
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typedef struct {
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uint32_t ti1sel : 4; // 0 selects tim_ti1_in[0..15] input
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uint32_t reserve0 : 4; // 4 Reserve
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uint32_t ti2sel : 4; // 8 selects tim_ti2_in[0..15] input
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uint32_t reserve1 : 20; // 12 Reserve
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} reg_tim1_tisel_t;
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typedef struct {
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uint32_t bkine : 1; // 0 TIMx_BKIN input enable
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uint32_t bkcmp1e : 1; // 1 tim_brk_cmp1 enable
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uint32_t bkcmp2e : 1; // 2 tim_brk_cmp2 enable
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uint32_t bkcmp3e : 1; // 3 tim_brk_cmp3 enable
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uint32_t bkcmp4e : 1; // 4 tim_brk_cmp4 enable
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uint32_t bkcmp5e : 1; // 5 tim_brk_cmp5 enable
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uint32_t bkcmp6e : 1; // 6 tim_brk_cmp6 enable
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uint32_t bkcmp7e : 1; // 7 tim_brk_cmp7 enable
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uint32_t reserve0 : 1; // 8 Reserve
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uint32_t bkinp : 1; // 9 TIMx_BKIN input polarity
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uint32_t bkcmp1p : 1; // 10 tim_brk_cmp1 input polarity
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uint32_t bkcmp2p : 1; // 11 tim_brk_cmp2 input polarity
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uint32_t bkcmp3p : 1; // 12 tim_brk_cmp3 input polarity
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uint32_t bkcmp4p : 1; // 13 tim_brk_cmp4 input polarity
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uint32_t reserve1 : 18; // 14 Reserve
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} reg_tim1_af1_t;
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typedef struct {
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uint32_t reserve0 : 16; // 0 Reserve
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uint32_t ocrsel : 3; // 16 ocref_clr source selection
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uint32_t reserve1 : 13; // 19 Reserve
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} reg_tim1_af2_t;
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typedef struct {
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uint32_t dba : 5; // 0 DMA base address
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uint32_t reserve0 : 3; // 5 Reserve
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uint32_t dbl : 5; // 8 DMA burst length
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uint32_t reserve1 : 3; // 13 Reserve
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uint32_t dbss : 4; // 16 DMA burst source selection
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uint32_t reserve2 : 12; // 20 Reserve
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} reg_tim1_dcr_t;
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typedef struct {
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uint32_t dmab : 32; // 0 DMA register for burst accesses
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} reg_tim1_dmar_t;
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typedef struct {
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volatile reg_tim1_cr1_t cr1;
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volatile reg_tim1_cr2_t cr2;
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volatile reg_tim1_smcr_t smcr;
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volatile reg_tim1_dier_t dier;
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volatile reg_tim1_sr_t sr;
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volatile reg_tim1_egr_t egr;
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volatile reg_tim1_ccmr1_output_t ccmr1_output;
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volatile uint32_t reserve0[-1];
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volatile reg_tim1_ccmr1_input_t ccmr1_input;
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volatile uint32_t reserve1[1];
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volatile reg_tim1_ccer_t ccer;
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volatile reg_tim1_cnt_t cnt;
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volatile reg_tim1_psc_t psc;
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volatile reg_tim1_arr_t arr;
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volatile reg_tim1_rcr_t rcr;
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volatile reg_tim1_ccr1_t ccr1;
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volatile reg_tim1_ccr2_t ccr2;
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volatile uint32_t reserve2[2];
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volatile reg_tim1_bdtr_t bdtr;
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volatile uint32_t reserve3[3];
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volatile reg_tim1_dtr2_t dtr2;
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volatile uint32_t reserve4[1];
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volatile reg_tim1_tisel_t tisel;
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volatile reg_tim1_af1_t af1;
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volatile reg_tim1_af2_t af2;
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volatile uint32_t reserve5[221];
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volatile reg_tim1_dcr_t dcr;
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volatile reg_tim1_dmar_t dmar;
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} reg_tim1_t;
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