870 lines
91 KiB
C
Executable File
870 lines
91 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t msison : 1; // 0 MSIS clock enable Set and cleared by software. Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator. Set by hardware when used directly or indirectly as system clock.
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uint32_t msikeron : 1; // 1 MSI enable for some peripheral kernels Set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI ON in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see autonomous mode for more details). The MSIKERON must be configured at 0 before entering Stop 3 mode.
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uint32_t msisrdy : 1; // 2 MSIS clock ready flag Set by hardware to indicate that the MSIS oscillator is stable. This bit is set only when MSIS is enabled by software by setting MSISON. Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles.
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uint32_t msipllen : 1; // 3 MSI clock PLL-mode enable Set and cleared by software to enable/disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR).
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uint32_t msikon : 1; // 4 MSIK clock enable Set and cleared by software. Cleared by hardware to stop the MSIK when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSIK oscillator ON when STOPWUCK = 0 or STOPKERWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator.
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uint32_t msikrdy : 1; // 5 MSIK clock ready flag Set by hardware to indicate that the MSIK is stable. This bit is set only when MSI kernel oscillator is enabled by software by setting MSIKON. Note: Once the MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles.
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uint32_t msipllsel : 1; // 6 MSI clock with PLL mode selection Set and cleared by software to select which MSI output clock uses the PLL mode. This bit can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0). Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to the both clocks outputs.
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uint32_t msipllfast: 1; // 7 MSI PLL mode fast startup Set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock source. This bit is used only if PLL mode is selected (MSIPLLEN = 1). The fast start-up feature is not active the first time the PLL mode is selected. The fast start-up is active when the MSI in PLL mode returns from switch off.
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uint32_t hsion : 1; // 8 HSI16 clock enable Set and cleared by software. Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the HSI16 oscillator ON when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI16 is used directly or indirectly as system clock.
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uint32_t hsikeron : 1; // 9 HSI16 enable for some peripheral kernels Set and cleared by software to force HSI16 ON even in Stop modes. Keeping the HSI16 ON in Stop mode allows the communication speed not to be reduced by the HSI16 startup time. This bit has no effect on HSION value. Refer to for more details. The HSIKERON must be configured at 0 before entering Stop 3 mode.
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uint32_t hsirdy : 1; // 10 HSI16 clock ready flag Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION. Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles.
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uint32_t reserve0 : 1; // 11 Reserve
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uint32_t hsi48on : 1; // 12 HSI48 clock enable Set and cleared by software. Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes.
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uint32_t hsi48rdy : 1; // 13 HSI48 clock ready flag Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON.
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uint32_t shsion : 1; // 14 SHSI clock enable Set and cleared by software. Cleared by hardware to stop the SHSI when entering in Stop, Standby or Shutdown modes.
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uint32_t shsirdy : 1; // 15 SHSI clock ready flag Set by hardware to indicate that the SHSI oscillator is stable. This bit is set only when SHSI is enabled by software by setting SHSION. Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles.
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uint32_t hseon : 1; // 16 HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
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uint32_t hserdy : 1; // 17 HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles.
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uint32_t hsebyp : 1; // 18 HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.
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uint32_t csson : 1; // 19 Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset.
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uint32_t hseext : 1; // 20 HSE external clock bypass mode Set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled.
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uint32_t reserve1 : 3; // 21 Reserve
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uint32_t pll1on : 1; // 24 PLL1 enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock.
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uint32_t pll1rdy : 1; // 25 PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked.
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uint32_t pll2on : 1; // 26 PLL2 enable Set and cleared by software to enable PLL2. Cleared by hardware when entering Stop, Standby or Shutdown mode.
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uint32_t pll2rdy : 1; // 27 PLL2 clock ready flag Set by hardware to indicate that the PLL2 is locked.
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uint32_t pll3on : 1; // 28 PLL3 enable Set and cleared by software to enable PLL3. Cleared by hardware when entering Stop, Standby or Shutdown mode.
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uint32_t pll3rdy : 1; // 29 PLL3 clock ready flag Set by hardware to indicate that the PLL3 is locked.
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uint32_t reserve2 : 2; // 30 Reserve
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} reg_sec_rcc_rcc_cr_t;
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typedef struct {
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uint32_t msical3 : 5; // 0 MSIRC3 clock calibration for MSI ranges 12 to 15 These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level.
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uint32_t msical2 : 5; // 5 MSIRC2 clock calibration for MSI ranges 8 to 11 These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level.
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uint32_t msical1 : 5; // 10 MSIRC1 clock calibration for MSI ranges 4 to 7 These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level.
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uint32_t msical0 : 5; // 15 MSIRC0 clock calibration for MSI ranges 0 to 3 These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0].
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uint32_t reserve0 : 2; // 20 Reserve
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uint32_t msibias : 1; // 22 MSI bias mode selection Set by software to select the MSI bias mode. By default, the MSI bias is in continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy.
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uint32_t msirgsel : 1; // 23 MSI clock range selection Set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect. After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR.
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uint32_t msikrange : 4; // 24 MSIK clock ranges These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSIKRANGE can be modified when MSIK is OFF (MSISON = 0) or when MSIK is ready (MSIKRDY = 1). MSIKRANGE must NOT be modified when MSIK is ON and NOT ready (MSIKON = 1 and MSIKRDY = 0) MSIKRANGE is kept when the device wakes up from Stop mode, except when the MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into Range 2 (24 MHz).
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uint32_t msisrange : 4; // 28 MSIS clock ranges These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSISRANGE can be modified when MSIS is OFF (MSISON = 0) or when MSIS is ready (MSISRDY = 1). MSISRANGE must NOT be modified when MSIS is ON and NOT ready (MSISON = 1 and MSISRDY = 0) MSISRANGE is kept when the device wakes up from Stop mode, except when the MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into Range 2 (24 MHz).
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} reg_sec_rcc_rcc_icscr1_t;
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typedef struct {
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uint32_t msitrim3 : 5; // 0 MSI clock trimming for ranges 12 to 15 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI.
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uint32_t msitrim2 : 5; // 5 MSI clock trimming for ranges 8 to 11 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI.
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uint32_t msitrim1 : 5; // 10 MSI clock trimming for ranges 4 to 7 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI.
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uint32_t msitrim0 : 5; // 15 MSI clock trimming for ranges 0 to 3 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI.
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uint32_t reserve0 : 12; // 20 Reserve
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} reg_sec_rcc_rcc_icscr2_t;
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typedef struct {
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uint32_t hsical : 12; // 0 HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value.
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uint32_t reserve0 : 4; // 12 Reserve
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uint32_t hsitrim : 5; // 16 HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI.
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uint32_t reserve1 : 11; // 21 Reserve
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} reg_sec_rcc_rcc_icscr3_t;
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typedef struct {
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uint32_t hsi48cal : 9; // 0 HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value.
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uint32_t reserve0 : 23; // 9 Reserve
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} reg_sec_rcc_rcc_crrcr_t;
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typedef struct {
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uint32_t sw : 2; // 0 system clock switch Set and cleared by software to select system clock source (SYSCLK). Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI16 oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value.
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uint32_t sws : 2; // 2 system clock switch status Set and cleared by hardware to indicate which clock source is used as system clock.
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uint32_t stopwuck : 1; // 4 wakeup from Stop and CSS backup clock selection Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the clock security system on HSE. Warning: STOPWUCK must not be modified when the CSS is enabled by HSECSSON bit in RCC_CR and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW = 10).
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uint32_t stopkerwuck: 1; // 5 wakeup from Stop kernel clock automatic enable selection Set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals.
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uint32_t reserve0 : 18; // 6 Reserve
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uint32_t mcosel : 4; // 24 microcontroller clock output Set and cleared by software. Others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.
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uint32_t mcopre : 3; // 28 microcontroller clock output prescaler Set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. Others: not allowed
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uint32_t reserve1 : 1; // 31 Reserve
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} reg_sec_rcc_rcc_cfgr1_t;
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typedef struct {
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uint32_t hpre : 4; // 0 AHB prescaler Set and cleared by software to control the division factor of the AHB clock (HCLK). Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xxx: SYSCLK not divided
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uint32_t ppre1 : 3; // 4 APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (PCLK1). 0xx: HCLK not divided
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uint32_t reserve0 : 1; // 7 Reserve
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uint32_t ppre2 : 3; // 8 APB2 prescaler Set and cleared by software to control the division factor of the APB2 clock (PCLK2). 0xx: HCLK not divided
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uint32_t reserve1 : 5; // 11 Reserve
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uint32_t ahb1dis : 1; // 16 AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1.
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uint32_t ahb2dis1 : 1; // 17 AHB2_1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3.
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uint32_t ahb2dis2 : 1; // 18 AHB2_2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2EBNR2 are off.
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uint32_t apb1dis : 1; // 19 APB1 clock disable This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG.
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uint32_t apb2dis : 1; // 20 APB2 clock disable This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off.
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uint32_t reserve2 : 11; // 21 Reserve
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} reg_sec_rcc_rcc_cfgr2_t;
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typedef struct {
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uint32_t reserve0 : 4; // 0 Reserve
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uint32_t ppre3 : 3; // 4 APB3 prescaler Set and cleared by software to control the division factor of the APB3 clock (PCLK3). 0xx: HCLK not divided
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uint32_t reserve1 : 9; // 7 Reserve
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uint32_t ahb3dis : 1; // 16 AHB3 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4.
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uint32_t apb3dis : 1; // 17 APB3 clock disable This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off.
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uint32_t reserve2 : 14; // 18 Reserve
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} reg_sec_rcc_rcc_cfgr3_t;
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typedef struct {
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uint32_t pll1src : 2; // 0 PLL1 entry clock source Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled. In order to save power, when no PLL1 is used, the value of PLL1SRC must be 0.
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uint32_t pll1rge : 2; // 2 PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz
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uint32_t pll1fracen: 1; // 4 PLL1 fractional latch enable Set and reset by software to latch the content of PLL1FRACN into the ΣΠmodulator. In order to latch the PLL1FRACN value into the ΣΠmodulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see for details).
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uint32_t reserve0 : 3; // 5 Reserve
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uint32_t pll1m : 4; // 8 Prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ...
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uint32_t pll1mboost: 4; // 12 Prescaler for EPOD booster input clock Set and cleared by software to configure the prescaler of the PLL1, used for the EPOD booster. The EPOD booster input frequency is PLL1 input clock frequency/PLL1MBOOST. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0) and EPOD Boost mode is disabled (see ). others: reserved
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uint32_t pll1pen : 1; // 16 PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1_p_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
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uint32_t pll1qen : 1; // 17 PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1_q_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
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uint32_t pll1ren : 1; // 18 PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1RENPLL2REN and PLL1R bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
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uint32_t reserve1 : 13; // 19 Reserve
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} reg_sec_rcc_rcc_pll1cfgr_t;
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typedef struct {
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uint32_t pll2src : 2; // 0 PLL2 entry clock source Set and cleared by software to select PLL2 clock source. These bits can be written only when the PLL2 is disabled. In order to save power, when no PLL2 is used, the value of PLL2SRC must be 0.
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uint32_t pll2rge : 2; // 2 PLL2 input frequency range Set and reset by software to select the proper reference frequency range used for PLL2. This bit must be written before enabling the PLL2. 00-01-10: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz
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uint32_t pll2fracen: 1; // 4 PLL2 fractional latch enable Set and reset by software to latch the content of PLL2FRACN into the ΣΠmodulator. In order to latch the PLL2FRACN value into the ΣΠmodulator, PLL2FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL2FRACN into the modulator (see for details).
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uint32_t reserve0 : 3; // 5 Reserve
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uint32_t pll2m : 4; // 8 Prescaler for PLL2 Set and cleared by software to configure the prescaler of the PLL2. The VCO2 input frequency is PLL2 input clock frequency/PLL2M. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ...
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uint32_t reserve1 : 4; // 12 Reserve
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uint32_t pll2pen : 1; // 16 PLL2 DIVP divider output enable Set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, PLL2PEN and PLL2P bits must be set to 0 when the pll2_p_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).
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uint32_t pll2qen : 1; // 17 PLL2 DIVQ divider output enable Set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, PLL2QEN and PLL2Q bits must be set to 0 when the pll2_q_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0.
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uint32_t pll2ren : 1; // 18 PLL2 DIVR divider output enable Set and reset by software to enable the pll2_r_ck output of the PLL2. To save power, PLL2REN and PLL2R bits must be set to 0 when the pll2_r_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).
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uint32_t reserve2 : 13; // 19 Reserve
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} reg_sec_rcc_rcc_pll2cfgr_t;
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typedef struct {
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uint32_t pll3src : 2; // 0 PLL3 entry clock source Set and cleared by software to select PLL3 clock source. These bits can be written only when the PLL3 is disabled. In order to save power, when no PLL3 is used, the value of PLL3SRC must be 00.
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uint32_t pll3rge : 2; // 2 PLL3 input frequency range Set and reset by software to select the proper reference frequency range used for PLL3. This bit must be written before enabling the PLL3. 00-01-10: PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz
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uint32_t pll3fracen: 1; // 4 PLL3 fractional latch enable Set and reset by software to latch the content of PLL3FRACN into the ΣΠmodulator. In order to latch the PLL3FRACN value into the ΣΠmodulator, PLL3FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL3FRACN into the modulator (see for details).
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uint32_t reserve0 : 3; // 5 Reserve
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uint32_t pll3m : 4; // 8 Prescaler for PLL3 Set and cleared by software to configure the prescaler of the PLL3. The VCO3 input frequency is PLL3 input clock frequency/PLL3M. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ...
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uint32_t reserve1 : 4; // 12 Reserve
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uint32_t pll3pen : 1; // 16 PLL3 DIVP divider output enable Set and reset by software to enable the pll3_p_ck output of the PLL3. To save power, PLL3PEN and PLL3P bits must be set to 0 when the pll3_p_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).
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uint32_t pll3qen : 1; // 17 PLL3 DIVQ divider output enable Set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, PLL3QEN and PLL3Q bits must be set to 0 when the pll3_q_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).
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uint32_t pll3ren : 1; // 18 PLL3 DIVR divider output enable Set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, PLL3REN and PLL3R bits must be set to 0 when the pll3_r_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).
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uint32_t reserve2 : 13; // 19 Reserve
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} reg_sec_rcc_rcc_pll3cfgr_t;
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typedef struct {
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uint32_t pll1n : 9; // 0 Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16 MHz
|
||
uint32_t pll1p : 7; // 9 PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ...
|
||
uint32_t pll1q : 7; // 16 PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ...
|
||
uint32_t reserve0 : 1; // 23 Reserve
|
||
uint32_t pll1r : 7; // 24 PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ...
|
||
uint32_t reserve1 : 1; // 31 Reserve
|
||
} reg_sec_rcc_rcc_pll1divr_t;
|
||
|
||
typedef struct {
|
||
uint32_t reserve0 : 3; // 0 Reserve
|
||
uint32_t pll1fracn : 13; // 3 Fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with: PLL1N must be between 4 and 512. PLL1FRACN can be between 0 and 213- 1. The input frequency Fref1_ck must be between 4 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACEN to 0. Write the new fractional value into PLL1FRACN. Set the bit PLL1FRACEN to 1.
|
||
uint32_t reserve1 : 16; // 16 Reserve
|
||
} reg_sec_rcc_rcc_pll1fracr_t;
|
||
|
||
typedef struct {
|
||
uint32_t pll2n : 9; // 0 Multiplication factor for PLL2 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0). ... ... Others: reserved VCO output frequency = Fref2_ck x PLL2N, when fractional value 0 has been loaded into PLL2FRACN, with: PLL2N between 4 and 512 input frequency Fref2_ck between 1MHz and 16MHz
|
||
uint32_t pll2p : 7; // 9 PLL2 DIVP division factor Set and reset by software to control the frequency of the pll2_p_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ...
|
||
uint32_t pll2q : 7; // 16 PLL2 DIVQ division factor Set and reset by software to control the frequency of the pll2_q_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ...
|
||
uint32_t reserve0 : 1; // 23 Reserve
|
||
uint32_t pll2r : 7; // 24 PLL2 DIVR division factor Set and reset by software to control the frequency of the pll2_r_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ...
|
||
uint32_t reserve1 : 1; // 31 Reserve
|
||
} reg_sec_rcc_rcc_pll2divr_t;
|
||
|
||
typedef struct {
|
||
uint32_t reserve0 : 3; // 0 Reserve
|
||
uint32_t pll2fracn : 13; // 3 Fractional part of the multiplication factor for PLL2 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO. VCO output frequency = Fref2_ck x (PLL2N + (PLL2FRACN / 213)), with PLL2N must be between 4 and 512. PLL2FRACN can be between 0 and 213 - 1. The input frequency Fref2_ck must be between 4 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL2FRACEN to 0. Write the new fractional value into PLL2FRACN. Set the bit PLL2FRACEN to 1.
|
||
uint32_t reserve1 : 16; // 16 Reserve
|
||
} reg_sec_rcc_rcc_pll2fracr_t;
|
||
|
||
typedef struct {
|
||
uint32_t pll3n : 9; // 0 Multiplication factor for PLL3 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0). ... ... Others: reserved VCO output frequency = Fref3_ck x PLL3N, when fractional value 0 has been loaded into PLL3FRACN, with: PLL3N between 4 and 512 input frequency Fref3_ck between 4 and 16MHz
|
||
uint32_t pll3p : 7; // 9 PLL3 DIVP division factor Set and reset by software to control the frequency of the pll3_p_ck clock. These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ...
|
||
uint32_t pll3q : 7; // 16 PLL3 DIVQ division factor Set and reset by software to control the frequency of the pll3_q_ck clock. These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ...
|
||
uint32_t reserve0 : 1; // 23 Reserve
|
||
uint32_t pll3r : 7; // 24 PLL3 DIVR division factor Set and reset by software to control the frequency of the pll3_r_ck clock. These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ...
|
||
uint32_t reserve1 : 1; // 31 Reserve
|
||
} reg_sec_rcc_rcc_pll3divr_t;
|
||
|
||
typedef struct {
|
||
uint32_t reserve0 : 3; // 0 Reserve
|
||
uint32_t pll3fracn : 13; // 3 Fractional part of the multiplication factor for PLL3 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO. VCO output frequency = Fref3_ck x (PLL3N + (PLL3FRACN / 213)), with: PLL3N must be between 4 and 512. PLL3FRACN can be between 0 and 213 - 1. The input frequency Fref3_ck must be between 4 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL3FRACEN to 0. Write the new fractional value into PLL3FRACN. Set the bit PLL3FRACEN to 1.
|
||
uint32_t reserve1 : 16; // 16 Reserve
|
||
} reg_sec_rcc_rcc_pll3fracr_t;
|
||
|
||
typedef struct {
|
||
uint32_t lsirdyie : 1; // 0 LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization.
|
||
uint32_t lserdyie : 1; // 1 LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.
|
||
uint32_t msisrdyie : 1; // 2 MSIS ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization.
|
||
uint32_t hsirdyie : 1; // 3 HSI16 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization.
|
||
uint32_t hserdyie : 1; // 4 HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization.
|
||
uint32_t hsi48rdyie: 1; // 5 HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization.
|
||
uint32_t pll1rdyie : 1; // 6 PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL1 lock.
|
||
uint32_t pll2rdyie : 1; // 7 PLL2 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL2 lock.
|
||
uint32_t pll3rdyie : 1; // 8 PLL3 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL3 lock.
|
||
uint32_t reserve0 : 2; // 9 Reserve
|
||
uint32_t msikrdyie : 1; // 11 MSIK ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization.
|
||
uint32_t shsirdyie : 1; // 12 SHSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization.
|
||
uint32_t reserve1 : 19; // 13 Reserve
|
||
} reg_sec_rcc_rcc_cier_t;
|
||
|
||
typedef struct {
|
||
uint32_t lsirdyf : 1; // 0 LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. Cleared by software setting the LSIRDYC bit.
|
||
uint32_t lserdyf : 1; // 1 LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYIE is set. Cleared by software setting the LSERDYC bit.
|
||
uint32_t msisrdyf : 1; // 2 MSIS ready interrupt flag Set by hardware when the MSIS clock becomes stable and MSISRDYIE is set. Cleared by software setting the MSISRDYC bit.
|
||
uint32_t hsirdyf : 1; // 3 HSI16 ready interrupt flag Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit.
|
||
uint32_t hserdyf : 1; // 4 HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit.
|
||
uint32_t hsi48rdyf : 1; // 5 HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. Cleared by software setting the HSI48RDYC bit.
|
||
uint32_t pll1rdyf : 1; // 6 PLL1 ready interrupt flag Set by hardware when the PLL1 locks and PLL1RDYIE is set. Cleared by software setting the PLL1RDYC bit.
|
||
uint32_t pll2rdyf : 1; // 7 PLL2 ready interrupt flag Set by hardware when the PLL2 locks and PLL2RDYIE is set. Cleared by software setting the PLL2RDYC bit.
|
||
uint32_t pll3rdyf : 1; // 8 PLL3 ready interrupt flag Set by hardware when the PLL3 locks and PLL3RDYIE is set. Cleared by software setting the PLL3RDYC bit.
|
||
uint32_t reserve0 : 1; // 9 Reserve
|
||
uint32_t cssf : 1; // 10 Clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit.
|
||
uint32_t msikrdyf : 1; // 11 MSIK ready interrupt flag Set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set. Cleared by software setting the MSIKRDYC bit.
|
||
uint32_t shsirdyf : 1; // 12 SHSI ready interrupt flag Set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set. Cleared by software setting the SHSIRDYC bit.
|
||
uint32_t reserve1 : 19; // 13 Reserve
|
||
} reg_sec_rcc_rcc_cifr_t;
|
||
|
||
typedef struct {
|
||
uint32_t lsirdyc : 1; // 0 LSI ready interrupt clear Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect.
|
||
uint32_t lserdyc : 1; // 1 LSE ready interrupt clear Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect.
|
||
uint32_t msisrdyc : 1; // 2 MSIS ready interrupt clear Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect.
|
||
uint32_t hsirdyc : 1; // 3 HSI16 ready interrupt clear Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect.
|
||
uint32_t hserdyc : 1; // 4 HSE ready interrupt clear Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect.
|
||
uint32_t hsi48rdyc : 1; // 5 HSI48 ready interrupt clear Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect.
|
||
uint32_t pll1rdyc : 1; // 6 PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect.
|
||
uint32_t pll2rdyc : 1; // 7 PLL2 ready interrupt clear Writing this bit to 1 clears the PLL2RDYF flag. Writing 0 has no effect.
|
||
uint32_t pll3rdyc : 1; // 8 PLL3 ready interrupt clear Writing this bit to 1 clears the PLL3RDYF flag. Writing 0 has no effect.
|
||
uint32_t reserve0 : 1; // 9 Reserve
|
||
uint32_t cssc : 1; // 10 Clock security system interrupt clear Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect.
|
||
uint32_t msikrdyc : 1; // 11 MSIK oscillator ready interrupt clear Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect.
|
||
uint32_t shsirdyc : 1; // 12 SHSI oscillator ready interrupt clear Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect.
|
||
uint32_t reserve1 : 19; // 13 Reserve
|
||
} reg_sec_rcc_rcc_cicr_t;
|
||
|
||
typedef struct {
|
||
uint32_t gpdma1rst : 1; // 0 GPDMA1 reset Set and cleared by software.
|
||
uint32_t cordicrst : 1; // 1 CORDIC reset Set and cleared by software.
|
||
uint32_t fmacrst : 1; // 2 FMAC reset Set and cleared by software.
|
||
uint32_t mdf1rst : 1; // 3 MDF1 reset Set and cleared by software.
|
||
uint32_t reserve0 : 8; // 4 Reserve
|
||
uint32_t crcrst : 1; // 12 CRC reset Set and cleared by software.
|
||
uint32_t reserve1 : 3; // 13 Reserve
|
||
uint32_t tscrst : 1; // 16 TSC reset Set and cleared by software.
|
||
uint32_t ramcfgrst : 1; // 17 RAMCFG reset Set and cleared by software.
|
||
uint32_t dma2drst : 1; // 18 DMA2D reset Set and cleared by software.
|
||
uint32_t reserve2 : 13; // 19 Reserve
|
||
} reg_sec_rcc_rcc_ahb1rstr_t;
|
||
|
||
typedef struct {
|
||
uint32_t gpioarst : 1; // 0 IO port A reset Set and cleared by software.
|
||
uint32_t gpiobrst : 1; // 1 IO port B reset Set and cleared by software.
|
||
uint32_t gpiocrst : 1; // 2 IO port C reset Set and cleared by software.
|
||
uint32_t gpiodrst : 1; // 3 IO port D reset Set and cleared by software.
|
||
uint32_t gpioerst : 1; // 4 IO port E reset Set and cleared by software.
|
||
uint32_t gpiofrst : 1; // 5 IO port F reset Set and cleared by software.
|
||
uint32_t gpiogrst : 1; // 6 IO port G reset Set and cleared by software.
|
||
uint32_t gpiohrst : 1; // 7 IO port H reset Set and cleared by software.
|
||
uint32_t gpioirst : 1; // 8 IO port I reset Set and cleared by software.
|
||
uint32_t reserve0 : 1; // 9 Reserve
|
||
uint32_t adc1rst : 1; // 10 ADC1 reset Set and cleared by software.
|
||
uint32_t reserve1 : 1; // 11 Reserve
|
||
uint32_t dcmi_pssirst: 1; // 12 DCMI and PSSI reset Set and cleared by software.
|
||
uint32_t reserve2 : 1; // 13 Reserve
|
||
uint32_t otgrst : 1; // 14 OTG_FS reset Set and cleared by software.
|
||
uint32_t reserve3 : 1; // 15 Reserve
|
||
uint32_t aesrst : 1; // 16 AES hardware accelerator reset Set and cleared by software.
|
||
uint32_t hashrst : 1; // 17 Hash reset Set and cleared by software.
|
||
uint32_t rngrst : 1; // 18 Random number generator reset Set and cleared by software.
|
||
uint32_t pkarst : 1; // 19 PKA reset Set and cleared by software.
|
||
uint32_t saesrst : 1; // 20 SAES hardware accelerator reset Set and cleared by software.
|
||
uint32_t octospimrst: 1; // 21 OCTOSPIM reset Set and cleared by software.
|
||
uint32_t reserve4 : 1; // 22 Reserve
|
||
uint32_t otfdec1rst: 1; // 23 OTFDEC1 reset Set and cleared by software.
|
||
uint32_t otfdec2rst: 1; // 24 OTFDEC2 reset Set and cleared by software.
|
||
uint32_t reserve5 : 2; // 25 Reserve
|
||
uint32_t sdmmc1rst : 1; // 27 SDMMC1 reset Set and cleared by software.
|
||
uint32_t sdmmc2rst : 1; // 28 SDMMC2 reset Set and cleared by software.
|
||
uint32_t reserve6 : 3; // 29 Reserve
|
||
} reg_sec_rcc_rcc_ahb2rstr1_t;
|
||
|
||
typedef struct {
|
||
uint32_t fsmcrst : 1; // 0 Flexible memory controller reset Set and cleared by software.
|
||
uint32_t reserve0 : 3; // 1 Reserve
|
||
uint32_t octospi1rst: 1; // 4 OCTOSPI1 reset Set and cleared by software.
|
||
uint32_t reserve1 : 3; // 5 Reserve
|
||
uint32_t octospi2rst: 1; // 8 OCTOSPI2 reset Set and cleared by software.
|
||
uint32_t reserve2 : 23; // 9 Reserve
|
||
} reg_sec_rcc_rcc_ahb2rstr2_t;
|
||
|
||
typedef struct {
|
||
uint32_t lpgpio1rst: 1; // 0 LPGPIO1 reset Set and cleared by software.
|
||
uint32_t reserve0 : 4; // 1 Reserve
|
||
uint32_t adc4rst : 1; // 5 ADC4 reset Set and cleared by software.
|
||
uint32_t dac1rst : 1; // 6 DAC1 reset Set and cleared by software.
|
||
uint32_t reserve1 : 2; // 7 Reserve
|
||
uint32_t lpdma1rst : 1; // 9 LPDMA1 reset Set and cleared by software.
|
||
uint32_t adf1rst : 1; // 10 ADF1 reset Set and cleared by software.
|
||
uint32_t reserve2 : 21; // 11 Reserve
|
||
} reg_sec_rcc_rcc_ahb3rstr_t;
|
||
|
||
typedef struct {
|
||
uint32_t tim2rst : 1; // 0 TIM2 reset Set and cleared by software.
|
||
uint32_t tim3rst : 1; // 1 TIM3 reset Set and cleared by software.
|
||
uint32_t tim4rst : 1; // 2 TIM4 reset Set and cleared by software.
|
||
uint32_t tim5rst : 1; // 3 TIM5 reset Set and cleared by software.
|
||
uint32_t tim6rst : 1; // 4 TIM6 reset Set and cleared by software.
|
||
uint32_t tim7rst : 1; // 5 TIM7 reset Set and cleared by software.
|
||
uint32_t reserve0 : 8; // 6 Reserve
|
||
uint32_t spi2rst : 1; // 14 SPI2 reset Set and cleared by software.
|
||
uint32_t reserve1 : 2; // 15 Reserve
|
||
uint32_t usart2rst : 1; // 17 USART2 reset Set and cleared by software.
|
||
uint32_t usart3rst : 1; // 18 USART3 reset Set and cleared by software.
|
||
uint32_t uart4rst : 1; // 19 UART4 reset Set and cleared by software.
|
||
uint32_t uart5rst : 1; // 20 UART5 reset Set and cleared by software.
|
||
uint32_t i2c1rst : 1; // 21 I2C1 reset Set and cleared by software.
|
||
uint32_t i2c2rst : 1; // 22 I2C2 reset Set and cleared by software.
|
||
uint32_t reserve2 : 1; // 23 Reserve
|
||
uint32_t crsrst : 1; // 24 CRS reset Set and cleared by software.
|
||
uint32_t reserve3 : 7; // 25 Reserve
|
||
} reg_sec_rcc_rcc_apb1rstr1_t;
|
||
|
||
typedef struct {
|
||
uint32_t reserve0 : 1; // 0 Reserve
|
||
uint32_t i2c4rst : 1; // 1 I2C4 reset Set and cleared by software
|
||
uint32_t reserve1 : 3; // 2 Reserve
|
||
uint32_t lptim2rst : 1; // 5 LPTIM2 reset Set and cleared by software.
|
||
uint32_t reserve2 : 3; // 6 Reserve
|
||
uint32_t fdcan1rst : 1; // 9 FDCAN1 reset Set and cleared by software.
|
||
uint32_t reserve3 : 13; // 10 Reserve
|
||
uint32_t ucpd1rst : 1; // 23 UCPD1 reset Set and cleared by software.
|
||
uint32_t reserve4 : 8; // 24 Reserve
|
||
} reg_sec_rcc_rcc_apb1rstr2_t;
|
||
|
||
typedef struct {
|
||
uint32_t reserve0 : 11; // 0 Reserve
|
||
uint32_t tim1rst : 1; // 11 TIM1 reset Set and cleared by software.
|
||
uint32_t spi1rst : 1; // 12 SPI1 reset Set and cleared by software.
|
||
uint32_t tim8rst : 1; // 13 TIM8 reset Set and cleared by software.
|
||
uint32_t usart1rst : 1; // 14 USART1 reset Set and cleared by software.
|
||
uint32_t reserve1 : 1; // 15 Reserve
|
||
uint32_t tim15rst : 1; // 16 TIM15 reset Set and cleared by software.
|
||
uint32_t tim16rst : 1; // 17 TIM16 reset Set and cleared by software.
|
||
uint32_t tim17rst : 1; // 18 TIM17 reset Set and cleared by software.
|
||
uint32_t reserve2 : 2; // 19 Reserve
|
||
uint32_t sai1rst : 1; // 21 SAI1 reset Set and cleared by software.
|
||
uint32_t sai2rst : 1; // 22 SAI2 reset Set and cleared by software.
|
||
uint32_t reserve3 : 9; // 23 Reserve
|
||
} reg_sec_rcc_rcc_apb2rstr_t;
|
||
|
||
typedef struct {
|
||
uint32_t reserve0 : 1; // 0 Reserve
|
||
uint32_t syscfgrst : 1; // 1 SYSCFG reset Set and cleared by software.
|
||
uint32_t reserve1 : 3; // 2 Reserve
|
||
uint32_t spi3rst : 1; // 5 SPI3 reset Set and cleared by software.
|
||
uint32_t lpuart1rst: 1; // 6 LPUART1 reset Set and cleared by software.
|
||
uint32_t i2c3rst : 1; // 7 I2C3 reset Set and cleared by software.
|
||
uint32_t reserve2 : 3; // 8 Reserve
|
||
uint32_t lptim1rst : 1; // 11 LPTIM1 reset Set and cleared by software.
|
||
uint32_t lptim3rst : 1; // 12 LPTIM3 reset Set and cleared by software.
|
||
uint32_t lptim4rst : 1; // 13 LPTIM4 reset Set and cleared by software.
|
||
uint32_t opamprst : 1; // 14 OPAMP reset Set and cleared by software.
|
||
uint32_t comprst : 1; // 15 COMP reset Set and cleared by software.
|
||
uint32_t reserve3 : 4; // 16 Reserve
|
||
uint32_t vrefrst : 1; // 20 VREFBUF reset Set and cleared by software.
|
||
uint32_t reserve4 : 11; // 21 Reserve
|
||
} reg_sec_rcc_rcc_apb3rstr_t;
|
||
|
||
typedef struct {
|
||
uint32_t gpdma1en : 1; // 0 GPDMA1 clock enable Set and cleared by software.
|
||
uint32_t cordicen : 1; // 1 CORDIC clock enable Set and cleared by software.
|
||
uint32_t fmacen : 1; // 2 FMAC clock enable Set and reset by software.
|
||
uint32_t mdf1en : 1; // 3 MDF1 clock enable Set and reset by software.
|
||
uint32_t reserve0 : 4; // 4 Reserve
|
||
uint32_t flashen : 1; // 8 FLASH clock enable Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode.
|
||
uint32_t reserve1 : 3; // 9 Reserve
|
||
uint32_t crcen : 1; // 12 CRC clock enable Set and cleared by software.
|
||
uint32_t reserve2 : 3; // 13 Reserve
|
||
uint32_t tscen : 1; // 16 Touch sensing controller clock enable Set and cleared by software.
|
||
uint32_t ramcfgen : 1; // 17 RAMCFG clock enable Set and cleared by software.
|
||
uint32_t dma2den : 1; // 18 DMA2D clock enable Set and cleared by software.
|
||
uint32_t reserve3 : 5; // 19 Reserve
|
||
uint32_t gtzc1en : 1; // 24 GTZC1 clock enable Set and reset by software.
|
||
uint32_t reserve4 : 3; // 25 Reserve
|
||
uint32_t bkpsramen : 1; // 28 BKPSRAM clock enable Set and reset by software.
|
||
uint32_t reserve5 : 1; // 29 Reserve
|
||
uint32_t dcache1en : 1; // 30 DCACHE1 clock enable Set and reset by software. Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2 or FSMC, even if the DCACHE1 is bypassed.
|
||
uint32_t sram1en : 1; // 31 SRAM1 clock enable Set and reset by software.
|
||
} reg_sec_rcc_rcc_ahb1enr_t;
|
||
|
||
typedef struct {
|
||
uint32_t gpioaen : 1; // 0 IO port A clock enable Set and cleared by software.
|
||
uint32_t gpioben : 1; // 1 IO port B clock enable Set and cleared by software.
|
||
uint32_t gpiocen : 1; // 2 IO port C clock enable Set and cleared by software.
|
||
uint32_t gpioden : 1; // 3 IO port D clock enable Set and cleared by software.
|
||
uint32_t gpioeen : 1; // 4 IO port E clock enable Set and cleared by software.
|
||
uint32_t gpiofen : 1; // 5 IO port F clock enable Set and cleared by software.
|
||
uint32_t gpiogen : 1; // 6 IO port G clock enable Set and cleared by software.
|
||
uint32_t gpiohen : 1; // 7 IO port H clock enable Set and cleared by software.
|
||
uint32_t gpioien : 1; // 8 IO port I clock enable Set and cleared by software.
|
||
uint32_t reserve0 : 1; // 9 Reserve
|
||
uint32_t adc1en : 1; // 10 ADC1 clock enable Set and cleared by software.
|
||
uint32_t reserve1 : 1; // 11 Reserve
|
||
uint32_t dcmi_pssien: 1; // 12 DCMI and PSSI clock enable Set and cleared by software.
|
||
uint32_t reserve2 : 1; // 13 Reserve
|
||
uint32_t otgen : 1; // 14 OTG_FS clock enable Set and cleared by software.
|
||
uint32_t reserve3 : 1; // 15 Reserve
|
||
uint32_t aesen : 1; // 16 AES clock enable Set and cleared by software.
|
||
uint32_t hashen : 1; // 17 HASH clock enable Set and cleared by software
|
||
uint32_t rngen : 1; // 18 RNG clock enable Set and cleared by software.
|
||
uint32_t pkaen : 1; // 19 PKA clock enable Set and cleared by software.
|
||
uint32_t saesen : 1; // 20 SAES clock enable Set and cleared by software.
|
||
uint32_t octospimen: 1; // 21 OCTOSPIM clock enable Set and cleared by software.
|
||
uint32_t reserve4 : 1; // 22 Reserve
|
||
uint32_t otfdec1en : 1; // 23 OTFDEC1 clock enable Set and cleared by software.
|
||
uint32_t otfdec2en : 1; // 24 OTFDEC2 clock enable Set and cleared by software.
|
||
uint32_t reserve5 : 2; // 25 Reserve
|
||
uint32_t sdmmc1en : 1; // 27 SDMMC1 clock enable Set and cleared by software.
|
||
uint32_t sdmmc2en : 1; // 28 SDMMC2 clock enable Set and cleared by software.
|
||
uint32_t reserve6 : 1; // 29 Reserve
|
||
uint32_t sram2en : 1; // 30 SRAM2 clock enable Set and reset by software.
|
||
uint32_t sram3en : 1; // 31 SRAM3 clock enable Set and reset by software.
|
||
} reg_sec_rcc_rcc_ahb2enr1_t;
|
||
|
||
typedef struct {
|
||
uint32_t fsmcen : 1; // 0 FSMC clock enable Set and cleared by software.
|
||
uint32_t reserve0 : 3; // 1 Reserve
|
||
uint32_t octospi1en: 1; // 4 OCTOSPI1 clock enable Set and cleared by software.
|
||
uint32_t reserve1 : 3; // 5 Reserve
|
||
uint32_t octospi2en: 1; // 8 OCTOSPI2 clock enable Set and cleared by software.
|
||
uint32_t reserve2 : 23; // 9 Reserve
|
||
} reg_sec_rcc_rcc_ahb2enr2_t;
|
||
|
||
typedef struct {
|
||
uint32_t lpgpio1en : 1; // 0 LPGPIO1 enable Set and cleared by software.
|
||
uint32_t reserve0 : 1; // 1 Reserve
|
||
uint32_t pwren : 1; // 2 PWR clock enable Set and cleared by software.
|
||
uint32_t reserve1 : 2; // 3 Reserve
|
||
uint32_t adc4en : 1; // 5 ADC4 clock enable Set and cleared by software.
|
||
uint32_t dac1en : 1; // 6 DAC1 clock enable Set and cleared by software.
|
||
uint32_t reserve2 : 2; // 7 Reserve
|
||
uint32_t lpdma1en : 1; // 9 LPDMA1 clock enable Set and cleared by software.
|
||
uint32_t adf1en : 1; // 10 ADF1 clock enable Set and cleared by software.
|
||
uint32_t reserve3 : 1; // 11 Reserve
|
||
uint32_t gtzc2en : 1; // 12 GTZC2 clock enable Set and cleared by software.
|
||
uint32_t reserve4 : 18; // 13 Reserve
|
||
uint32_t sram4en : 1; // 31 SRAM4 clock enable Set and reset by software.
|
||
} reg_sec_rcc_rcc_ahb3enr_t;
|
||
|
||
typedef struct {
|
||
uint32_t tim2en : 1; // 0 TIM2 clock enable Set and cleared by software.
|
||
uint32_t tim3en : 1; // 1 TIM3 clock enable Set and cleared by software.
|
||
uint32_t tim4en : 1; // 2 TIM4 clock enable Set and cleared by software.
|
||
uint32_t tim5en : 1; // 3 TIM5 clock enable Set and cleared by software.
|
||
uint32_t tim6en : 1; // 4 TIM6 clock enable Set and cleared by software.
|
||
uint32_t tim7en : 1; // 5 TIM7 clock enable Set and cleared by software.
|
||
uint32_t reserve0 : 5; // 6 Reserve
|
||
uint32_t wwdgen : 1; // 11 WWDG clock enable Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset.
|
||
uint32_t reserve1 : 2; // 12 Reserve
|
||
uint32_t spi2en : 1; // 14 SPI2 clock enable Set and cleared by software.
|
||
uint32_t reserve2 : 2; // 15 Reserve
|
||
uint32_t usart2en : 1; // 17 USART2 clock enable Set and cleared by software.
|
||
uint32_t usart3en : 1; // 18 USART3 clock enable Set and cleared by software.
|
||
uint32_t uart4en : 1; // 19 UART4 clock enable Set and cleared by software.
|
||
uint32_t uart5en : 1; // 20 UART5 clock enable Set and cleared by software.
|
||
uint32_t i2c1en : 1; // 21 I2C1 clock enable Set and cleared by software.
|
||
uint32_t i2c2en : 1; // 22 I2C2 clock enable Set and cleared by software.
|
||
uint32_t reserve3 : 1; // 23 Reserve
|
||
uint32_t crsen : 1; // 24 CRS clock enable Set and cleared by software.
|
||
uint32_t reserve4 : 7; // 25 Reserve
|
||
} reg_sec_rcc_rcc_apb1enr1_t;
|
||
|
||
typedef struct {
|
||
uint32_t reserve0 : 1; // 0 Reserve
|
||
uint32_t i2c4en : 1; // 1 I2C4 clock enable Set and cleared by software
|
||
uint32_t reserve1 : 3; // 2 Reserve
|
||
uint32_t lptim2en : 1; // 5 LPTIM2 clock enable Set and cleared by software.
|
||
uint32_t reserve2 : 3; // 6 Reserve
|
||
uint32_t fdcan1en : 1; // 9 FDCAN1 clock enable Set and cleared by software.
|
||
uint32_t reserve3 : 13; // 10 Reserve
|
||
uint32_t ucpd1en : 1; // 23 UCPD1 clock enable Set and cleared by software.
|
||
uint32_t reserve4 : 8; // 24 Reserve
|
||
} reg_sec_rcc_rcc_apb1enr2_t;
|
||
|
||
typedef struct {
|
||
uint32_t reserve0 : 11; // 0 Reserve
|
||
uint32_t tim1en : 1; // 11 TIM1 clock enable Set and cleared by software.
|
||
uint32_t spi1en : 1; // 12 SPI1 clock enable Set and cleared by software.
|
||
uint32_t tim8en : 1; // 13 TIM8 clock enable Set and cleared by software.
|
||
uint32_t usart1en : 1; // 14 USART1clock enable Set and cleared by software.
|
||
uint32_t reserve1 : 1; // 15 Reserve
|
||
uint32_t tim15en : 1; // 16 TIM15 clock enable Set and cleared by software.
|
||
uint32_t tim16en : 1; // 17 TIM16 clock enable Set and cleared by software.
|
||
uint32_t tim17en : 1; // 18 TIM17 clock enable Set and cleared by software.
|
||
uint32_t reserve2 : 2; // 19 Reserve
|
||
uint32_t sai1en : 1; // 21 SAI1 clock enable Set and cleared by software.
|
||
uint32_t sai2en : 1; // 22 SAI2 clock enable Set and cleared by software.
|
||
uint32_t reserve3 : 9; // 23 Reserve
|
||
} reg_sec_rcc_rcc_apb2enr_t;
|
||
|
||
typedef struct {
|
||
uint32_t reserve0 : 1; // 0 Reserve
|
||
uint32_t syscfgen : 1; // 1 SYSCFG clock enable Set and cleared by software.
|
||
uint32_t reserve1 : 3; // 2 Reserve
|
||
uint32_t spi3en : 1; // 5 SPI3 clock enable Set and cleared by software.
|
||
uint32_t lpuart1en : 1; // 6 LPUART1 clock enable Set and cleared by software.
|
||
uint32_t i2c3en : 1; // 7 I2C3 clock enable Set and cleared by software.
|
||
uint32_t reserve2 : 3; // 8 Reserve
|
||
uint32_t lptim1en : 1; // 11 LPTIM1 clock enable Set and cleared by software.
|
||
uint32_t lptim3en : 1; // 12 LPTIM3 clock enable Set and cleared by software.
|
||
uint32_t lptim4en : 1; // 13 LPTIM4 clock enable Set and cleared by software.
|
||
uint32_t opampen : 1; // 14 OPAMP clock enable Set and cleared by software.
|
||
uint32_t compen : 1; // 15 COMP clock enable Set and cleared by software.
|
||
uint32_t reserve3 : 4; // 16 Reserve
|
||
uint32_t vrefen : 1; // 20 VREFBUF clock enable Set and cleared by software.
|
||
uint32_t rtcapben : 1; // 21 RTC and TAMP APB clock enable Set and cleared by software.
|
||
uint32_t reserve4 : 10; // 22 Reserve
|
||
} reg_sec_rcc_rcc_apb3enr_t;
|
||
|
||
typedef struct {
|
||
uint32_t gpdma1smen: 1; // 0 GPDMA1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t cordicsmen: 1; // 1 CORDIC clocks enable during Sleep and Stop modes Set and cleared by software during Sleep mode.
|
||
uint32_t fmacsmen : 1; // 2 FMAC clocks enable during Sleep and Stop modes. Set and cleared by software.
|
||
uint32_t mdf1smen : 1; // 3 MDF1 clocks enable during Sleep and Stop modes. Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t reserve0 : 4; // 4 Reserve
|
||
uint32_t flashsmen : 1; // 8 FLASH clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve1 : 3; // 9 Reserve
|
||
uint32_t crcsmen : 1; // 12 CRC clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve2 : 3; // 13 Reserve
|
||
uint32_t tscsmen : 1; // 16 TSC clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t ramcfgsmen: 1; // 17 RAMCFG clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t dma2dsmen : 1; // 18 DMA2D clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve3 : 5; // 19 Reserve
|
||
uint32_t gtzc1smen : 1; // 24 GTZC1 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve4 : 3; // 25 Reserve
|
||
uint32_t bkpsramsmen: 1; // 28 BKPSRAM clocks enable during Sleep and Stop modes Set and cleared by software
|
||
uint32_t icachesmen: 1; // 29 ICACHE clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t dcache1smen: 1; // 30 DCACHE1 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t sram1smen : 1; // 31 SRAM1 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
} reg_sec_rcc_rcc_ahb1smenr_t;
|
||
|
||
typedef struct {
|
||
uint32_t gpioasmen : 1; // 0 IO port A clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t gpiobsmen : 1; // 1 IO port B clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t gpiocsmen : 1; // 2 IO port C clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t gpiodsmen : 1; // 3 IO port D clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t gpioesmen : 1; // 4 IO port E clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t gpiofsmen : 1; // 5 IO port F clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t gpiogsmen : 1; // 6 IO port G clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t gpiohsmen : 1; // 7 IO port H clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t gpioismen : 1; // 8 IO port I clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve0 : 1; // 9 Reserve
|
||
uint32_t adc1smen : 1; // 10 ADC1 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve1 : 1; // 11 Reserve
|
||
uint32_t dcmi_pssismen: 1; // 12 DCMI and PSSI clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve2 : 1; // 13 Reserve
|
||
uint32_t otgsmen : 1; // 14 OTG_FS clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve3 : 1; // 15 Reserve
|
||
uint32_t aessmen : 1; // 16 AES clock enable during Sleep and Stop modes Set and cleared by software
|
||
uint32_t hashsmen : 1; // 17 HASH clock enable during Sleep and Stop modes Set and cleared by software
|
||
uint32_t rngsmen : 1; // 18 Random number generator (RNG) clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t pkasmen : 1; // 19 PKA clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t saessmen : 1; // 20 SAES accelerator clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t octospimsmen: 1; // 21 OCTOSPIM clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve4 : 1; // 22 Reserve
|
||
uint32_t otfdec1smen: 1; // 23 OTFDEC1 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t otfdec2smen: 1; // 24 OTFDEC2 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve5 : 2; // 25 Reserve
|
||
uint32_t sdmmc1smen: 1; // 27 SDMMC1 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t sdmmc2smen: 1; // 28 SDMMC2 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve6 : 1; // 29 Reserve
|
||
uint32_t sram2smen : 1; // 30 SRAM2 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t sram3smen : 1; // 31 SRAM3 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
} reg_sec_rcc_rcc_ahb2smenr1_t;
|
||
|
||
typedef struct {
|
||
uint32_t fsmcsmen : 1; // 0 FSMC clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve0 : 3; // 1 Reserve
|
||
uint32_t octospi1smen: 1; // 4 OCTOSPI1 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve1 : 3; // 5 Reserve
|
||
uint32_t octospi2smen: 1; // 8 OCTOSPI2 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve2 : 23; // 9 Reserve
|
||
} reg_sec_rcc_rcc_ahb2smenr2_t;
|
||
|
||
typedef struct {
|
||
uint32_t lpgpio1smen: 1; // 0 LPGPIO1 enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve0 : 1; // 1 Reserve
|
||
uint32_t pwrsmen : 1; // 2 PWR clock enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve1 : 2; // 3 Reserve
|
||
uint32_t adc4smen : 1; // 5 ADC4 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t dac1smen : 1; // 6 DAC1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t reserve2 : 2; // 7 Reserve
|
||
uint32_t lpdma1smen: 1; // 9 LPDMA1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t adf1smen : 1; // 10 ADF1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t reserve3 : 1; // 11 Reserve
|
||
uint32_t gtzc2smen : 1; // 12 GTZC2 clock enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve4 : 18; // 13 Reserve
|
||
uint32_t sram4smen : 1; // 31 SRAM4 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
} reg_sec_rcc_rcc_ahb3smenr_t;
|
||
|
||
typedef struct {
|
||
uint32_t tim2smen : 1; // 0 TIM2 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t tim3smen : 1; // 1 TIM3 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t tim4smen : 1; // 2 TIM4 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t tim5smen : 1; // 3 TIM5 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t tim6smen : 1; // 4 TIM6 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t tim7smen : 1; // 5 TIM7 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve0 : 5; // 6 Reserve
|
||
uint32_t wwdgsmen : 1; // 11 Window watchdog clocks enable during Sleep and Stop modes Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated.
|
||
uint32_t reserve1 : 2; // 12 Reserve
|
||
uint32_t spi2smen : 1; // 14 SPI2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t reserve2 : 2; // 15 Reserve
|
||
uint32_t usart2smen: 1; // 17 USART2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t usart3smen: 1; // 18 USART3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t uart4smen : 1; // 19 UART4 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t uart5smen : 1; // 20 UART5 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t i2c1smen : 1; // 21 I2C1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t i2c2smen : 1; // 22 I2C2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t reserve3 : 1; // 23 Reserve
|
||
uint32_t crssmen : 1; // 24 CRS clock enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve4 : 7; // 25 Reserve
|
||
} reg_sec_rcc_rcc_apb1smenr1_t;
|
||
|
||
typedef struct {
|
||
uint32_t reserve0 : 1; // 0 Reserve
|
||
uint32_t i2c4smen : 1; // 1 I2C4 clocks enable during Sleep and Stop modes Set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t reserve1 : 3; // 2 Reserve
|
||
uint32_t lptim2smen: 1; // 5 LPTIM2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t reserve2 : 3; // 6 Reserve
|
||
uint32_t fdcan1smen: 1; // 9 FDCAN1 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve3 : 13; // 10 Reserve
|
||
uint32_t ucpd1smen : 1; // 23 UCPD1 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve4 : 8; // 24 Reserve
|
||
} reg_sec_rcc_rcc_apb1smenr2_t;
|
||
|
||
typedef struct {
|
||
uint32_t reserve0 : 11; // 0 Reserve
|
||
uint32_t tim1smen : 1; // 11 TIM1 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t spi1smen : 1; // 12 SPI1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t tim8smen : 1; // 13 TIM8 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t usart1smen: 1; // 14 USART1clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t reserve1 : 1; // 15 Reserve
|
||
uint32_t tim15smen : 1; // 16 TIM15 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t tim16smen : 1; // 17 TIM16 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t tim17smen : 1; // 18 TIM17 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve2 : 2; // 19 Reserve
|
||
uint32_t sai1smen : 1; // 21 SAI1 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t sai2smen : 1; // 22 SAI2 clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve3 : 9; // 23 Reserve
|
||
} reg_sec_rcc_rcc_apb2smenr_t;
|
||
|
||
typedef struct {
|
||
uint32_t reserve0 : 1; // 0 Reserve
|
||
uint32_t syscfgsmen: 1; // 1 SYSCFG clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve1 : 3; // 2 Reserve
|
||
uint32_t spi3smen : 1; // 5 SPI3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t lpuart1smen: 1; // 6 LPUART1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t i2c3smen : 1; // 7 I2C3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t reserve2 : 3; // 8 Reserve
|
||
uint32_t lptim1smen: 1; // 11 LPTIM1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t lptim3smen: 1; // 12 LPTIM3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t lptim4smen: 1; // 13 LPTIM4 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t opampsmen : 1; // 14 OPAMP clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t compsmen : 1; // 15 COMP clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t reserve3 : 4; // 16 Reserve
|
||
uint32_t vrefsmen : 1; // 20 VREFBUF clocks enable during Sleep and Stop modes Set and cleared by software.
|
||
uint32_t rtcapbsmen: 1; // 21 RTC and TAMP APB clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t reserve4 : 10; // 22 Reserve
|
||
} reg_sec_rcc_rcc_apb3smenr_t;
|
||
|
||
typedef struct {
|
||
uint32_t reserve0 : 5; // 0 Reserve
|
||
uint32_t spi3amen : 1; // 5 SPI3 autonomous mode enable in Stop 0,1, 2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t lpuart1amen: 1; // 6 LPUART1 autonomous mode enable in Stop 0,1, 2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t i2c3amen : 1; // 7 I2C3 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t reserve1 : 3; // 8 Reserve
|
||
uint32_t lptim1amen: 1; // 11 LPTIM1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t lptim3amen: 1; // 12 LPTIM3 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t lptim4amen: 1; // 13 LPTIM4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t opampamen : 1; // 14 OPAMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software.
|
||
uint32_t compamen : 1; // 15 COMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software.
|
||
uint32_t reserve2 : 4; // 16 Reserve
|
||
uint32_t vrefamen : 1; // 20 VREFBUF autonomous mode enable in Stop 0,1,2 mode Set and cleared by software.
|
||
uint32_t rtcapbamen: 1; // 21 RTC and TAMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t reserve3 : 3; // 22 Reserve
|
||
uint32_t adc4amen : 1; // 25 ADC4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t lpgpio1amen: 1; // 26 LPGPIO1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software.
|
||
uint32_t dac1amen : 1; // 27 DAC1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t lpdma1amen: 1; // 28 LPDMA1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t adf1amen : 1; // 29 ADF1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
|
||
uint32_t reserve4 : 1; // 30 Reserve
|
||
uint32_t sram4amen : 1; // 31 SRAM4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software.
|
||
} reg_sec_rcc_rcc_srdamr_t;
|
||
|
||
typedef struct {
|
||
uint32_t usart1sel : 2; // 0 USART1 kernel clock source selection This bits are used to select the USART1 kernel clock source. Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE.
|
||
uint32_t usart2sel : 2; // 2 USART2 kernel clock source selection This bits are used to select the USART2 kernel clock source. Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE.
|
||
uint32_t usart3sel : 2; // 4 USART3 kernel clock source selection This bits are used to select the USART3 kernel clock source. Note: The USART3 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE.
|
||
uint32_t uart4sel : 2; // 6 UART4 kernel clock source selection This bits are used to select the UART4 kernel clock source. Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE.
|
||
uint32_t uart5sel : 2; // 8 UART5 kernel clock source selection These bits are used to select the UART5 kernel clock source. Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE.
|
||
uint32_t i2c1sel : 2; // 10 I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK.
|
||
uint32_t i2c2sel : 2; // 12 I2C2 kernel clock source selection These bits are used to select the I2C2 kernel clock source. Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK.
|
||
uint32_t i2c4sel : 2; // 14 I2C4 kernel clock source selection These bits are used to select the I2C4 kernel clock source. Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK.
|
||
uint32_t spi2sel : 2; // 16 SPI2 kernel clock source selection These bits are used to select the SPI2 kernel clock source. Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK.
|
||
uint32_t lptim2sel : 2; // 18 Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clock source. Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1.
|
||
uint32_t spi1sel : 2; // 20 SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK.
|
||
uint32_t systicksel: 2; // 22 SysTick clock source selection These bits are used to select the SysTick clock source. Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry.
|
||
uint32_t fdcan1sel : 2; // 24 FDCAN1 kernel clock source selection These bits are used to select the FDCAN1 kernel clock source.
|
||
uint32_t iclksel : 2; // 26 intermediate clock source selection These bits are used to select the clock source used by OTG_FS and SDMMC.
|
||
uint32_t reserve0 : 1; // 28 Reserve
|
||
uint32_t timicsel : 3; // 29 Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture When the TIMICSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS. When TIMICSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture. 0xx: HSI, MSIK and MSIS dividers disabled Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division.
|
||
} reg_sec_rcc_rcc_ccipr1_t;
|
||
|
||
typedef struct {
|
||
uint32_t mdf1sel : 3; // 0 MDF1 kernel clock source selection These bits are used to select the MDF1 kernel clock source. others: reserved
|
||
uint32_t reserve0 : 2; // 3 Reserve
|
||
uint32_t sai1sel : 3; // 5 SAI1 kernel clock source selection These bits are used to select the SAI1 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible.
|
||
uint32_t sai2sel : 3; // 8 SAI2 kernel clock source selection These bits are used to select the SAI2 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible.
|
||
uint32_t saessel : 1; // 11 SAES kernel clock source selection This bit is used to select the SAES kernel clock source.
|
||
uint32_t rngsel : 2; // 12 RNGSEL kernel clock source selection These bits are used to select the RNG kernel clock source.
|
||
uint32_t sdmmcsel : 1; // 14 SDMMC1 and SDMMC2 kernel clock source selection This bit is used to select the SDMMC kernel clock source. It is recommended to change this bit only after reset and before enabling the SDMMC.
|
||
uint32_t reserve1 : 5; // 15 Reserve
|
||
uint32_t octospisel: 2; // 20 OCTOSPI1 and OCTOSPI2 kernel clock source selection These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source.
|
||
uint32_t reserve2 : 10; // 22 Reserve
|
||
} reg_sec_rcc_rcc_ccipr2_t;
|
||
|
||
typedef struct {
|
||
uint32_t lpuart1sel: 3; // 0 LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source. others: reserved Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16, LSE or MSIK.
|
||
uint32_t spi3sel : 2; // 3 SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK.
|
||
uint32_t reserve0 : 1; // 5 Reserve
|
||
uint32_t i2c3sel : 2; // 6 I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK.
|
||
uint32_t lptim34sel: 2; // 8 LPTIM3 and LPTIM4 kernel clock source selection These bits are used to select the LPTIM3 and LPTIM4 kernel clock source. Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1 or MSIK with MSIKERON = 1.
|
||
uint32_t lptim1sel : 2; // 10 LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source. Note: The LPTIM1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1 or MSIK with MSIKERON = 1.
|
||
uint32_t adcdacsel : 3; // 12 ADC1, ADC4 and DAC1 kernel clock source selection These bits are used to select the ADC1, ADC4 and DAC1 kernel clock source. others: reserved Note: The ADC1, ADC4 and DAC1 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI16 or MSIK (only ADC4 and DAC1 are functional in Stop 2 mode).
|
||
uint32_t dac1sel : 1; // 15 DAC1 sample and hold clock source selection This bit is used to select the DAC1 sample and hold clock source.
|
||
uint32_t adf1sel : 3; // 16 ADF1 kernel clock source selection These bits are used to select the ADF1 kernel clock source. others: reserved Note: The ADF1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK.
|
||
uint32_t reserve1 : 13; // 19 Reserve
|
||
} reg_sec_rcc_rcc_ccipr3_t;
|
||
|
||
typedef struct {
|
||
uint32_t lseon : 1; // 0 LSE oscillator enable Set and cleared by software.
|
||
uint32_t lserdy : 1; // 1 LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.
|
||
uint32_t lsebyp : 1; // 2 LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).
|
||
uint32_t lsedrv : 2; // 3 LSE oscillator drive capability Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Note: The oscillator is in 'Xtal mode when it is not in bypass mode.
|
||
uint32_t lsecsson : 1; // 5 CSS on LSE enable Set by software to enable the CSS on LSE. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case, the software must disable the LSECSSON bit.
|
||
uint32_t lsecssd : 1; // 6 CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the CCS on the external 32 kHz oscillator (LSE).
|
||
uint32_t lsesysen : 1; // 7 LSE system clock (LSESYS) enable Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed. The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE.
|
||
uint32_t rtcsel : 2; // 8 RTC and TAMP clock source selection Set by software to select the clock source for the RTC and TAMP . Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them.
|
||
uint32_t reserve0 : 1; // 10 Reserve
|
||
uint32_t lsesysrdy : 1; // 11 LSE system clock (LSESYS) ready Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.
|
||
uint32_t lsegfon : 1; // 12 LSE clock glitch filter enable Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)
|
||
uint32_t reserve1 : 2; // 13 Reserve
|
||
uint32_t rtcen : 1; // 15 RTC and TAMP clock enable Set and cleared by software.
|
||
uint32_t bdrst : 1; // 16 Backup domain software reset Set and cleared by software.
|
||
uint32_t reserve2 : 7; // 17 Reserve
|
||
uint32_t lscoen : 1; // 24 Low-speed clock output (LSCO) enable Set and cleared by software.
|
||
uint32_t lscosel : 1; // 25 Low-speed clock output selection Set and cleared by software.
|
||
uint32_t lsion : 1; // 26 LSI oscillator enable Set and cleared by software.
|
||
uint32_t lsirdy : 1; // 27 LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0.
|
||
uint32_t lsiprediv : 1; // 28 Low-speed clock divider configuration Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC.
|
||
uint32_t reserve3 : 3; // 29 Reserve
|
||
} reg_sec_rcc_rcc_bdcr_t;
|
||
|
||
typedef struct {
|
||
uint32_t reserve0 : 8; // 0 Reserve
|
||
uint32_t msiksrange: 4; // 8 MSIK range after Standby mode Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing the MSIKSRANGE does not change the current MSIK frequency.
|
||
uint32_t msissrange: 4; // 12 MSIS range after Standby mode Set by software to chose the MSIS frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSISSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing the MSISSRANGE does not change the current MSIS frequency.
|
||
uint32_t reserve1 : 7; // 16 Reserve
|
||
uint32_t rmvf : 1; // 23 Remove reset flag Set by software to clear the reset flags.
|
||
uint32_t reserve2 : 1; // 24 Reserve
|
||
uint32_t oblrstf : 1; // 25 Option byte loader reset flag Set by hardware when a reset from the option byte loading occurs. Cleared by writing to the RMVF bit.
|
||
uint32_t pinrstf : 1; // 26 NRST pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit.
|
||
uint32_t borrstf : 1; // 27 BOR flag Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit.
|
||
uint32_t sftrstf : 1; // 28 Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit.
|
||
uint32_t iwdgrstf : 1; // 29 Independent watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by writing to the RMVF bit.
|
||
uint32_t wwdgrstf : 1; // 30 Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit.
|
||
uint32_t lpwrrstf : 1; // 31 Low-power reset flag Set by hardware when a reset occurs due to Stop, Standby or Shutdown mode entry, whereas the corresponding nRST_STOP, nRST_STBY or nRST_SHDW option bit is cleared. Cleared by writing to the RMVF bit.
|
||
} reg_sec_rcc_rcc_csr_t;
|
||
|
||
typedef struct {
|
||
uint32_t hsisec : 1; // 0 HSI clock configuration and status bits security Set and reset by software.
|
||
uint32_t hsesec : 1; // 1 HSE clock configuration bits, status bits and HSE_CSS security Set and reset by software.
|
||
uint32_t msisec : 1; // 2 MSI clock configuration and status bits security Set and reset by software.
|
||
uint32_t lsisec : 1; // 3 LSI clock configuration and status bits security Set and reset by software.
|
||
uint32_t lsesec : 1; // 4 LSE clock configuration and status bits security Set and reset by software.
|
||
uint32_t sysclksec : 1; // 5 SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security Set and reset by software.
|
||
uint32_t prescsec : 1; // 6 AHBx/APBx prescaler configuration bits security Set and reset by software.
|
||
uint32_t pll1sec : 1; // 7 PLL1 clock configuration and status bits security Set and reset by software.
|
||
uint32_t pll2sec : 1; // 8 PLL2 clock configuration and status bits security Set and reset by software.
|
||
uint32_t pll3sec : 1; // 9 PLL3 clock configuration and status bits security Set and reset by software.
|
||
uint32_t iclksec : 1; // 10 intermediate clock source selection security Set and reset by software.
|
||
uint32_t hsi48sec : 1; // 11 HSI48 clock configuration and status bits security Set and reset by software.
|
||
uint32_t rmvfsec : 1; // 12 Remove reset flag security Set and reset by software.
|
||
uint32_t reserve0 : 19; // 13 Reserve
|
||
} reg_sec_rcc_rcc_seccfgr_t;
|
||
|
||
typedef struct {
|
||
uint32_t spriv : 1; // 0 RCC secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access.
|
||
uint32_t nspriv : 1; // 1 RCC non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure.
|
||
uint32_t reserve0 : 30; // 2 Reserve
|
||
} reg_sec_rcc_rcc_privcfgr_t;
|
||
|
||
typedef struct {
|
||
volatile reg_sec_rcc_rcc_cr_t rcc_cr;
|
||
volatile uint32_t reserve0[1];
|
||
volatile reg_sec_rcc_rcc_icscr1_t rcc_icscr1;
|
||
volatile reg_sec_rcc_rcc_icscr2_t rcc_icscr2;
|
||
volatile reg_sec_rcc_rcc_icscr3_t rcc_icscr3;
|
||
volatile reg_sec_rcc_rcc_crrcr_t rcc_crrcr;
|
||
volatile uint32_t reserve1[1];
|
||
volatile reg_sec_rcc_rcc_cfgr1_t rcc_cfgr1;
|
||
volatile reg_sec_rcc_rcc_cfgr2_t rcc_cfgr2;
|
||
volatile reg_sec_rcc_rcc_cfgr3_t rcc_cfgr3;
|
||
volatile reg_sec_rcc_rcc_pll1cfgr_t rcc_pll1cfgr;
|
||
volatile reg_sec_rcc_rcc_pll2cfgr_t rcc_pll2cfgr;
|
||
volatile reg_sec_rcc_rcc_pll3cfgr_t rcc_pll3cfgr;
|
||
volatile reg_sec_rcc_rcc_pll1divr_t rcc_pll1divr;
|
||
volatile reg_sec_rcc_rcc_pll1fracr_t rcc_pll1fracr;
|
||
volatile reg_sec_rcc_rcc_pll2divr_t rcc_pll2divr;
|
||
volatile reg_sec_rcc_rcc_pll2fracr_t rcc_pll2fracr;
|
||
volatile reg_sec_rcc_rcc_pll3divr_t rcc_pll3divr;
|
||
volatile reg_sec_rcc_rcc_pll3fracr_t rcc_pll3fracr;
|
||
volatile uint32_t reserve2[1];
|
||
volatile reg_sec_rcc_rcc_cier_t rcc_cier;
|
||
volatile reg_sec_rcc_rcc_cifr_t rcc_cifr;
|
||
volatile reg_sec_rcc_rcc_cicr_t rcc_cicr;
|
||
volatile uint32_t reserve3[1];
|
||
volatile reg_sec_rcc_rcc_ahb1rstr_t rcc_ahb1rstr;
|
||
volatile reg_sec_rcc_rcc_ahb2rstr1_t rcc_ahb2rstr1;
|
||
volatile reg_sec_rcc_rcc_ahb2rstr2_t rcc_ahb2rstr2;
|
||
volatile reg_sec_rcc_rcc_ahb3rstr_t rcc_ahb3rstr;
|
||
volatile uint32_t reserve4[1];
|
||
volatile reg_sec_rcc_rcc_apb1rstr1_t rcc_apb1rstr1;
|
||
volatile reg_sec_rcc_rcc_apb1rstr2_t rcc_apb1rstr2;
|
||
volatile reg_sec_rcc_rcc_apb2rstr_t rcc_apb2rstr;
|
||
volatile reg_sec_rcc_rcc_apb3rstr_t rcc_apb3rstr;
|
||
volatile uint32_t reserve5[1];
|
||
volatile reg_sec_rcc_rcc_ahb1enr_t rcc_ahb1enr;
|
||
volatile reg_sec_rcc_rcc_ahb2enr1_t rcc_ahb2enr1;
|
||
volatile reg_sec_rcc_rcc_ahb2enr2_t rcc_ahb2enr2;
|
||
volatile reg_sec_rcc_rcc_ahb3enr_t rcc_ahb3enr;
|
||
volatile uint32_t reserve6[1];
|
||
volatile reg_sec_rcc_rcc_apb1enr1_t rcc_apb1enr1;
|
||
volatile reg_sec_rcc_rcc_apb1enr2_t rcc_apb1enr2;
|
||
volatile reg_sec_rcc_rcc_apb2enr_t rcc_apb2enr;
|
||
volatile reg_sec_rcc_rcc_apb3enr_t rcc_apb3enr;
|
||
volatile uint32_t reserve7[1];
|
||
volatile reg_sec_rcc_rcc_ahb1smenr_t rcc_ahb1smenr;
|
||
volatile reg_sec_rcc_rcc_ahb2smenr1_t rcc_ahb2smenr1;
|
||
volatile reg_sec_rcc_rcc_ahb2smenr2_t rcc_ahb2smenr2;
|
||
volatile reg_sec_rcc_rcc_ahb3smenr_t rcc_ahb3smenr;
|
||
volatile uint32_t reserve8[1];
|
||
volatile reg_sec_rcc_rcc_apb1smenr1_t rcc_apb1smenr1;
|
||
volatile reg_sec_rcc_rcc_apb1smenr2_t rcc_apb1smenr2;
|
||
volatile reg_sec_rcc_rcc_apb2smenr_t rcc_apb2smenr;
|
||
volatile reg_sec_rcc_rcc_apb3smenr_t rcc_apb3smenr;
|
||
volatile uint32_t reserve9[1];
|
||
volatile reg_sec_rcc_rcc_srdamr_t rcc_srdamr;
|
||
volatile uint32_t reserve10[1];
|
||
volatile reg_sec_rcc_rcc_ccipr1_t rcc_ccipr1;
|
||
volatile reg_sec_rcc_rcc_ccipr2_t rcc_ccipr2;
|
||
volatile reg_sec_rcc_rcc_ccipr3_t rcc_ccipr3;
|
||
volatile uint32_t reserve11[1];
|
||
volatile reg_sec_rcc_rcc_bdcr_t rcc_bdcr;
|
||
volatile reg_sec_rcc_rcc_csr_t rcc_csr;
|
||
volatile uint32_t reserve12[6];
|
||
volatile reg_sec_rcc_rcc_seccfgr_t rcc_seccfgr;
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volatile reg_sec_rcc_rcc_privcfgr_t rcc_privcfgr;
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} reg_sec_rcc_t;
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