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stm32u5_cargo/stm32u5/includes/u575xx/reg_sec_aes_gen.h
2023-11-14 16:25:09 -05:00

175 lines
5.6 KiB
C
Executable File

#include <stdint.h>
typedef struct {
uint32_t en : 1; // 0 AES enable
uint32_t datatype : 2; // 1 Data type selection (for data in and data out to/from the cryptographic block)
uint32_t mode : 2; // 3 AES operating mode
uint32_t chmod : 2; // 5 AES chaining mode
uint32_t reserve0 : 4; // 7 Reserve
uint32_t dmainen : 1; // 11 Enable DMA management of data input phase
uint32_t dmaouten : 1; // 12 Enable DMA management of data output phase
uint32_t gcmph : 2; // 13 GCMPH
uint32_t reserve1 : 1; // 15 Reserve
uint32_t chmod_2 : 1; // 16 CHMOD_2
uint32_t reserve2 : 1; // 17 Reserve
uint32_t keysize : 1; // 18 KEYSIZE
uint32_t reserve3 : 1; // 19 Reserve
uint32_t npblb : 4; // 20 NPBLB
uint32_t kmod : 2; // 24 KMOD
uint32_t reserve4 : 5; // 26 Reserve
uint32_t iprst : 1; // 31 IPRST
} reg_sec_aes_cr_t;
typedef struct {
uint32_t ccf : 1; // 0 Computation complete flag
uint32_t rderr : 1; // 1 Read error flag
uint32_t wrerr : 1; // 2 Write error flag
uint32_t busy : 1; // 3 BUSY
uint32_t reserve0 : 3; // 4 Reserve
uint32_t keyvalid : 1; // 7 Key Valid flag
uint32_t reserve1 : 24; // 8 Reserve
} reg_sec_aes_sr_t;
typedef struct {
uint32_t din : 32; // 0 Input data word
} reg_sec_aes_dinr_t;
typedef struct {
uint32_t dout : 32; // 0 Output data word
} reg_sec_aes_doutr_t;
typedef struct {
uint32_t key : 32; // 0 Cryptographic key, bits [31:0]
} reg_sec_aes_keyr0_t;
typedef struct {
uint32_t key : 32; // 0 Cryptographic key, bits [63:32]
} reg_sec_aes_keyr1_t;
typedef struct {
uint32_t keyr : 32; // 0 Cryptographic key, bits [95:64]
} reg_sec_aes_keyr2_t;
typedef struct {
uint32_t aes_keyr3 : 32; // 0 Cryptographic key, bits [127:96]
} reg_sec_aes_keyr3_t;
typedef struct {
uint32_t ivi : 32; // 0 Initialization vector input, bits [31:0]
} reg_sec_aes_ivr0_t;
typedef struct {
uint32_t ivi : 32; // 0 Initialization vector input, bits [63:32]
} reg_sec_aes_ivr1_t;
typedef struct {
uint32_t ivi : 32; // 0 Initialization vector input, bits [95:64]
} reg_sec_aes_ivr2_t;
typedef struct {
uint32_t ivi : 32; // 0 Initialization vector input, bits [127:96]
} reg_sec_aes_ivr3_t;
typedef struct {
uint32_t key : 32; // 0 Cryptographic key, bits [159:128]
} reg_sec_aes_keyr4_t;
typedef struct {
uint32_t key : 32; // 0 Cryptographic key, bits [191:160]
} reg_sec_aes_keyr5_t;
typedef struct {
uint32_t key : 32; // 0 Cryptographic key, bits [223:192]
} reg_sec_aes_keyr6_t;
typedef struct {
uint32_t key : 32; // 0 Cryptographic key, bits [255:224]
} reg_sec_aes_keyr7_t;
typedef struct {
uint32_t susp0 : 32; // 0 AES suspend
} reg_sec_aes_susp0r_t;
typedef struct {
uint32_t susp1 : 32; // 0 AES suspend
} reg_sec_aes_susp1r_t;
typedef struct {
uint32_t susp2 : 32; // 0 AES suspend
} reg_sec_aes_susp2r_t;
typedef struct {
uint32_t susp3 : 32; // 0 AES suspend
} reg_sec_aes_susp3r_t;
typedef struct {
uint32_t susp4 : 32; // 0 AES suspend
} reg_sec_aes_susp4r_t;
typedef struct {
uint32_t susp5 : 32; // 0 AES suspend
} reg_sec_aes_susp5r_t;
typedef struct {
uint32_t susp6 : 32; // 0 AES suspend
} reg_sec_aes_susp6r_t;
typedef struct {
uint32_t susp7 : 32; // 0 AES suspend
} reg_sec_aes_susp7r_t;
typedef struct {
uint32_t ccfie : 1; // 0 Computation complete flag
uint32_t rweie : 1; // 1 Read or write error interrupt flag
uint32_t keie : 1; // 2 Key error interrupt flag
uint32_t rngeie : 1; // 3 Key error interrupt flag
uint32_t reserve0 : 28; // 4 Reserve
} reg_sec_aes_ier_t;
typedef struct {
uint32_t ccf : 1; // 0 Computation complete flag
uint32_t rweif : 1; // 1 Read or write error interrupt flag
uint32_t keif : 1; // 2 Key error interrupt flag
uint32_t rngeif : 1; // 3 Key error interrupt flag
uint32_t reserve0 : 28; // 4 Reserve
} reg_sec_aes_isr_t;
typedef struct {
uint32_t ccf : 1; // 0 Computation complete flag clear
uint32_t rweif : 1; // 1 Read or write error interrupt flag clear
uint32_t keif : 1; // 2 Key error interrupt flag clear
uint32_t reserve0 : 29; // 3 Reserve
} reg_sec_aes_icr_t;
typedef struct {
volatile reg_sec_aes_cr_t cr;
volatile reg_sec_aes_sr_t sr;
volatile reg_sec_aes_dinr_t dinr;
volatile reg_sec_aes_doutr_t doutr;
volatile reg_sec_aes_keyr0_t keyr0;
volatile reg_sec_aes_keyr1_t keyr1;
volatile reg_sec_aes_keyr2_t keyr2;
volatile reg_sec_aes_keyr3_t keyr3;
volatile reg_sec_aes_ivr0_t ivr0;
volatile reg_sec_aes_ivr1_t ivr1;
volatile reg_sec_aes_ivr2_t ivr2;
volatile reg_sec_aes_ivr3_t ivr3;
volatile reg_sec_aes_keyr4_t keyr4;
volatile reg_sec_aes_keyr5_t keyr5;
volatile reg_sec_aes_keyr6_t keyr6;
volatile reg_sec_aes_keyr7_t keyr7;
volatile reg_sec_aes_susp0r_t susp0r;
volatile reg_sec_aes_susp1r_t susp1r;
volatile reg_sec_aes_susp2r_t susp2r;
volatile reg_sec_aes_susp3r_t susp3r;
volatile reg_sec_aes_susp4r_t susp4r;
volatile reg_sec_aes_susp5r_t susp5r;
volatile reg_sec_aes_susp6r_t susp6r;
volatile reg_sec_aes_susp7r_t susp7r;
volatile uint32_t reserve0[168];
volatile reg_sec_aes_ier_t ier;
volatile reg_sec_aes_isr_t isr;
volatile reg_sec_aes_icr_t icr;
} reg_sec_aes_t;