278 lines
10 KiB
C
Executable File
278 lines
10 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t en : 1; // 0 Enable
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uint32_t abort : 1; // 1 Abort request
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uint32_t dmaen : 1; // 2 DMA enable
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uint32_t tcen : 1; // 3 Timeout counter enable
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uint32_t reserve0 : 2; // 4 Reserve
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uint32_t dqm : 1; // 6 Dual-quad mode
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uint32_t fsel : 1; // 7 FLASH memory selection
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uint32_t fthres : 5; // 8 IFO threshold level
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uint32_t reserve1 : 3; // 13 Reserve
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uint32_t teie : 1; // 16 Transfer error interrupt enable
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uint32_t tcie : 1; // 17 Transfer complete interrupt enable
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uint32_t ftie : 1; // 18 FIFO threshold interrupt enable
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uint32_t smie : 1; // 19 Status match interrupt enable
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uint32_t toie : 1; // 20 TimeOut interrupt enable
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uint32_t reserve2 : 1; // 21 Reserve
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uint32_t apms : 1; // 22 Automatic poll mode stop
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uint32_t pmm : 1; // 23 Polling match mode
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uint32_t reserve3 : 4; // 24 Reserve
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uint32_t fmode : 2; // 28 Functional mode
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uint32_t reserve4 : 2; // 30 Reserve
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} reg_octospi_cr_t;
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typedef struct {
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uint32_t ckmode : 1; // 0 Mode 0 / mode 3
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uint32_t frck : 1; // 1 Free running clock
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uint32_t reserve0 : 1; // 2 Reserve
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uint32_t dlybyp : 1; // 3 Delay block bypass
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uint32_t reserve1 : 4; // 4 Reserve
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uint32_t csht : 6; // 8 Chip-select high time
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uint32_t reserve2 : 2; // 14 Reserve
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uint32_t devsize : 5; // 16 Device size
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uint32_t reserve3 : 3; // 21 Reserve
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uint32_t mtyp : 3; // 24 Memory type
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uint32_t reserve4 : 5; // 27 Reserve
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} reg_octospi_dcr1_t;
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typedef struct {
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uint32_t prescaler : 8; // 0 Clock prescaler
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uint32_t reserve0 : 8; // 8 Reserve
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uint32_t wrapsize : 3; // 16 Wrap size
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uint32_t reserve1 : 13; // 19 Reserve
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} reg_octospi_dcr2_t;
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typedef struct {
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uint32_t maxtran : 8; // 0 Maximum transfer
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uint32_t reserve0 : 8; // 8 Reserve
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uint32_t csbound : 5; // 16 CS boundary
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uint32_t reserve1 : 11; // 21 Reserve
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} reg_octospi_dcr3_t;
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typedef struct {
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uint32_t refresh : 32; // 0 Refresh rate
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} reg_octospi_dcr4_t;
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typedef struct {
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uint32_t tef : 1; // 0 Transfer error flag
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uint32_t tcf : 1; // 1 transfer complete flag
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uint32_t ftf : 1; // 2 FIFO threshold flag
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uint32_t smf : 1; // 3 status match flag
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uint32_t tof : 1; // 4 timeout flag
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uint32_t busy : 1; // 5 BUSY
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uint32_t reserve0 : 2; // 6 Reserve
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uint32_t flevel : 6; // 8 FIFO level
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uint32_t reserve1 : 18; // 14 Reserve
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} reg_octospi_sr_t;
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typedef struct {
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uint32_t ctef : 1; // 0 Clear Transfer error flag
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uint32_t ctcf : 1; // 1 Clear transfer complete flag
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uint32_t reserve0 : 1; // 2 Reserve
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uint32_t csmf : 1; // 3 Clear status match flag
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uint32_t ctof : 1; // 4 Clear timeout flag
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uint32_t reserve1 : 27; // 5 Reserve
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} reg_octospi_fcr_t;
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typedef struct {
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uint32_t dl : 32; // 0 Data length
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} reg_octospi_dlr_t;
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typedef struct {
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uint32_t address : 32; // 0 ADDRESS
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} reg_octospi_ar_t;
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typedef struct {
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uint32_t data : 32; // 0 DATA
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} reg_octospi_dr_t;
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typedef struct {
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uint32_t mask : 32; // 0 Status MASK
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} reg_octospi_psmkr_t;
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typedef struct {
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uint32_t match : 32; // 0 Status match
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} reg_octospi_psmar_t;
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typedef struct {
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uint32_t interval : 16; // 0 polling interval
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_octospi_pir_t;
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typedef struct {
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uint32_t imode : 3; // 0 Instruction mode
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uint32_t idtr : 1; // 3 Instruction double transfer rate
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uint32_t isize : 2; // 4 Instruction size
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uint32_t reserve0 : 2; // 6 Reserve
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uint32_t admode : 3; // 8 Address mode
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uint32_t addtr : 1; // 11 Address double transfer rate
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uint32_t adsize : 2; // 12 Address size
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uint32_t reserve1 : 2; // 14 Reserve
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uint32_t abmode : 3; // 16 Alternate byte mode
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uint32_t abdtr : 1; // 19 Alternate bytes double transfer rate
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uint32_t absize : 2; // 20 Alternate bytes size
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uint32_t reserve2 : 2; // 22 Reserve
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uint32_t dmode : 3; // 24 Data mode
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uint32_t ddtr : 1; // 27 Alternate bytes double transfer rate
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uint32_t reserve3 : 1; // 28 Reserve
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uint32_t dqse : 1; // 29 DQS enable
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uint32_t reserve4 : 1; // 30 Reserve
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uint32_t sioo : 1; // 31 Send instruction only once mode
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} reg_octospi_ccr_t;
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typedef struct {
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uint32_t dcyc : 5; // 0 Number of dummy cycles
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uint32_t reserve0 : 23; // 5 Reserve
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uint32_t dhqc : 1; // 28 Delay hold quarter cycle
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uint32_t reserve1 : 1; // 29 Reserve
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uint32_t sshift : 1; // 30 Sample shift
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uint32_t reserve2 : 1; // 31 Reserve
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} reg_octospi_tcr_t;
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typedef struct {
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uint32_t instruction: 32; // 0 INSTRUCTION
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} reg_octospi_ir_t;
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typedef struct {
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uint32_t alternate : 32; // 0 Alternate bytes
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} reg_octospi_abr_t;
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typedef struct {
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uint32_t timeout : 16; // 0 Timeout period
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_octospi_lptr_t;
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typedef struct {
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uint32_t imode : 3; // 0 Instruction mode
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uint32_t idtr : 1; // 3 Instruction double transfer rate
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uint32_t isize : 2; // 4 Instruction size
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uint32_t reserve0 : 2; // 6 Reserve
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uint32_t admode : 3; // 8 Address mode
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uint32_t addtr : 1; // 11 Address double transfer rate
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uint32_t adsize : 2; // 12 Address size
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uint32_t reserve1 : 2; // 14 Reserve
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uint32_t abmode : 3; // 16 Alternate byte mode
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uint32_t abdtr : 1; // 19 Alternate bytes double transfer rate
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uint32_t absize : 2; // 20 Alternate bytes size
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uint32_t reserve2 : 2; // 22 Reserve
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uint32_t dmode : 3; // 24 Data mode
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uint32_t ddtr : 1; // 27 alternate bytes double transfer rate
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uint32_t reserve3 : 1; // 28 Reserve
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uint32_t dqse : 1; // 29 DQS enable
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uint32_t reserve4 : 2; // 30 Reserve
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} reg_octospi_wpccr_t;
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typedef struct {
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uint32_t dcyc : 5; // 0 Number of dummy cycles
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uint32_t reserve0 : 23; // 5 Reserve
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uint32_t dhqc : 1; // 28 Delay hold quarter cycle
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uint32_t reserve1 : 1; // 29 Reserve
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uint32_t sshift : 1; // 30 Sample shift
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uint32_t reserve2 : 1; // 31 Reserve
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} reg_octospi_wptcr_t;
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typedef struct {
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uint32_t instruction: 32; // 0 INSTRUCTION
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} reg_octospi_wpir_t;
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typedef struct {
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uint32_t alternate : 32; // 0 Alternate bytes
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} reg_octospi_wpabr_t;
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typedef struct {
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uint32_t imode : 3; // 0 Instruction mode
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uint32_t idtr : 1; // 3 Instruction double transfer rate
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uint32_t isize : 2; // 4 Instruction size
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uint32_t reserve0 : 2; // 6 Reserve
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uint32_t admode : 3; // 8 Address mode
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uint32_t addtr : 1; // 11 Address double transfer rate
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uint32_t adsize : 2; // 12 Address size
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uint32_t reserve1 : 2; // 14 Reserve
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uint32_t abmode : 3; // 16 Alternate byte mode
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uint32_t abdtr : 1; // 19 Alternate bytes double transfer rate
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uint32_t absize : 2; // 20 Alternate bytes size
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uint32_t reserve2 : 2; // 22 Reserve
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uint32_t dmode : 3; // 24 Data mode
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uint32_t ddtr : 1; // 27 alternate bytes double transfer rate
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uint32_t reserve3 : 1; // 28 Reserve
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uint32_t dqse : 1; // 29 DQS enable
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uint32_t reserve4 : 2; // 30 Reserve
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} reg_octospi_wccr_t;
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typedef struct {
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uint32_t dcyc : 5; // 0 Number of dummy cycles
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uint32_t reserve0 : 27; // 5 Reserve
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} reg_octospi_wtcr_t;
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typedef struct {
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uint32_t instruction: 32; // 0 INSTRUCTION
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} reg_octospi_wir_t;
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typedef struct {
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uint32_t alternate : 32; // 0 ALTERNATE
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} reg_octospi_wabr_t;
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typedef struct {
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uint32_t lm : 1; // 0 Latency mode
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uint32_t wzl : 1; // 1 Write zero latency
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uint32_t reserve0 : 6; // 2 Reserve
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uint32_t tacc : 8; // 8 Access time
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uint32_t trwr : 8; // 16 Read write recovery time
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uint32_t reserve1 : 8; // 24 Reserve
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} reg_octospi_hlcr_t;
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typedef struct {
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volatile reg_octospi_cr_t cr;
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volatile uint32_t reserve0[1];
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volatile reg_octospi_dcr1_t dcr1;
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volatile reg_octospi_dcr2_t dcr2;
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volatile reg_octospi_dcr3_t dcr3;
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volatile reg_octospi_dcr4_t dcr4;
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volatile uint32_t reserve1[2];
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volatile reg_octospi_sr_t sr;
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volatile reg_octospi_fcr_t fcr;
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volatile uint32_t reserve2[6];
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volatile reg_octospi_dlr_t dlr;
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volatile uint32_t reserve3[1];
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volatile reg_octospi_ar_t ar;
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volatile uint32_t reserve4[1];
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volatile reg_octospi_dr_t dr;
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volatile uint32_t reserve5[11];
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volatile reg_octospi_psmkr_t psmkr;
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volatile uint32_t reserve6[1];
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volatile reg_octospi_psmar_t psmar;
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volatile uint32_t reserve7[1];
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volatile reg_octospi_pir_t pir;
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volatile uint32_t reserve8[27];
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volatile reg_octospi_ccr_t ccr;
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volatile uint32_t reserve9[1];
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volatile reg_octospi_tcr_t tcr;
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volatile uint32_t reserve10[1];
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volatile reg_octospi_ir_t ir;
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volatile uint32_t reserve11[3];
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volatile reg_octospi_abr_t abr;
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volatile uint32_t reserve12[3];
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volatile reg_octospi_lptr_t lptr;
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volatile uint32_t reserve13[3];
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volatile reg_octospi_wpccr_t wpccr;
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volatile uint32_t reserve14[1];
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volatile reg_octospi_wptcr_t wptcr;
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volatile uint32_t reserve15[1];
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volatile reg_octospi_wpir_t wpir;
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volatile uint32_t reserve16[3];
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volatile reg_octospi_wpabr_t wpabr;
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volatile uint32_t reserve17[7];
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volatile reg_octospi_wccr_t wccr;
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volatile uint32_t reserve18[1];
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volatile reg_octospi_wtcr_t wtcr;
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volatile uint32_t reserve19[1];
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volatile reg_octospi_wir_t wir;
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volatile uint32_t reserve20[3];
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volatile reg_octospi_wabr_t wabr;
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volatile uint32_t reserve21[23];
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volatile reg_octospi_hlcr_t hlcr;
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} reg_octospi_t;
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