243 lines
11 KiB
C
Executable File
243 lines
11 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t cc1if : 1; // 0 Compare 1 interrupt flag
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uint32_t arrm : 1; // 1 Autoreload match
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uint32_t exttrig : 1; // 2 External trigger edge event
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uint32_t cmp1ok : 1; // 3 Compare register 1 update OK
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uint32_t arrok : 1; // 4 Autoreload register update OK
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uint32_t up : 1; // 5 Counter direction change down to up
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uint32_t down : 1; // 6 Counter direction change up to down
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uint32_t ue : 1; // 7 LPTIM update event occurred
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uint32_t repok : 1; // 8 Repetition register update Ok
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uint32_t cc2if : 1; // 9 Compare 2 interrupt flag
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uint32_t reserve0 : 9; // 10 Reserve
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uint32_t cmp2ok : 1; // 19 Compare register 2 update OK
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uint32_t reserve1 : 4; // 20 Reserve
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uint32_t dierok : 1; // 24 Interrupt enable register update OK
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uint32_t reserve2 : 7; // 25 Reserve
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} reg_lptim_isr_output_t;
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typedef struct {
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uint32_t cc1if : 1; // 0 Compare 1 interrupt flag
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uint32_t arrm : 1; // 1 Autoreload match
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uint32_t exttrig : 1; // 2 External trigger edge event
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t arrok : 1; // 4 Autoreload register update OK
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uint32_t up : 1; // 5 Counter direction change down to up
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uint32_t down : 1; // 6 Counter direction change up to down
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uint32_t ue : 1; // 7 LPTIM update event occurred
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uint32_t repok : 1; // 8 Repetition register update Ok
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uint32_t cc2if : 1; // 9 Capture 2 interrupt flag
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uint32_t reserve1 : 2; // 10 Reserve
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uint32_t cc1of : 1; // 12 Capture 1 over-capture flag
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uint32_t cc2of : 1; // 13 Capture 2 over-capture flag
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uint32_t reserve2 : 10; // 14 Reserve
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uint32_t dierok : 1; // 24 Interrupt enable register update OK
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uint32_t reserve3 : 7; // 25 Reserve
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} reg_lptim_isr_intput_t;
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typedef struct {
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uint32_t cc1if : 1; // 0 Capture/compare 1 clear flag
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uint32_t arrmcf : 1; // 1 Autoreload match Clear Flag
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uint32_t exttrigcf : 1; // 2 External trigger valid edge Clear Flag
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uint32_t cmp1okcf : 1; // 3 Compare register 1 update OK Clear Flag
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uint32_t arrokcf : 1; // 4 Autoreload register update OK Clear Flag
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uint32_t upcf : 1; // 5 Direction change to UP Clear Flag
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uint32_t downcf : 1; // 6 Direction change to down Clear Flag
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uint32_t uecf : 1; // 7 Update event clear flag
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uint32_t repokcf : 1; // 8 Repetition register update OK clear flag
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uint32_t cc2cf : 1; // 9 Capture/compare 2 clear flag
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uint32_t reserve0 : 9; // 10 Reserve
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uint32_t cmp2okcf : 1; // 19 Compare register 2 update OK clear flag
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uint32_t reserve1 : 4; // 20 Reserve
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uint32_t dierokcf : 1; // 24 Interrupt enable register update OK clear flag
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uint32_t reserve2 : 7; // 25 Reserve
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} reg_lptim_icr_output_t;
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typedef struct {
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uint32_t cc1if : 1; // 0 Capture/compare 1 clear flag
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uint32_t arrmcf : 1; // 1 Autoreload match Clear Flag
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uint32_t exttrigcf : 1; // 2 External trigger valid edge Clear Flag
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t arrokcf : 1; // 4 Autoreload register update OK Clear Flag
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uint32_t upcf : 1; // 5 Direction change to UP Clear Flag
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uint32_t downcf : 1; // 6 Direction change to down Clear Flag
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uint32_t uecf : 1; // 7 Update event clear flag
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uint32_t repokcf : 1; // 8 Repetition register update OK clear flag
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uint32_t cc2cf : 1; // 9 Capture/compare 2 clear flag
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uint32_t reserve1 : 2; // 10 Reserve
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uint32_t cc1ocf : 1; // 12 Capture/compare 1 over-capture clear flag
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uint32_t cc2ocf : 1; // 13 Capture/compare 2 over-capture clear flag
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uint32_t reserve2 : 10; // 14 Reserve
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uint32_t dierokcf : 1; // 24 Interrupt enable register update OK clear flag
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uint32_t reserve3 : 7; // 25 Reserve
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} reg_lptim_icr_intput_t;
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typedef struct {
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uint32_t cc1if : 1; // 0 Capture/compare 1 clear flag
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uint32_t arrmie : 1; // 1 Autoreload match Interrupt Enable
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uint32_t exttrigie : 1; // 2 External trigger valid edge Interrupt Enable
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uint32_t cmp1okie : 1; // 3 Compare register 1 update OK Interrupt Enable
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uint32_t arrokie : 1; // 4 Autoreload register update OK Interrupt Enable
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uint32_t upie : 1; // 5 Direction change to UP Interrupt Enable
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uint32_t downie : 1; // 6 Direction change to down Interrupt Enable
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uint32_t ueie : 1; // 7 Update event interrupt enable
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uint32_t repokie : 1; // 8 REPOKIE
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uint32_t cc2ie : 1; // 9 Capture/compare 2 interrupt enable
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uint32_t reserve0 : 9; // 10 Reserve
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uint32_t cmp2okie : 1; // 19 Compare register 2 update OK interrupt enable
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uint32_t reserve1 : 3; // 20 Reserve
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uint32_t uede : 1; // 23 Update event DMA request enable
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uint32_t reserve2 : 8; // 24 Reserve
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} reg_lptim_dier_output_t;
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typedef struct {
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uint32_t cc1if : 1; // 0 Capture/compare 1 clear flag
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uint32_t arrmie : 1; // 1 Autoreload match Interrupt Enable
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uint32_t exttrigie : 1; // 2 External trigger valid edge Interrupt Enable
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t arrokie : 1; // 4 Autoreload register update OK Interrupt Enable
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uint32_t upie : 1; // 5 Direction change to UP Interrupt Enable
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uint32_t downie : 1; // 6 Direction change to down Interrupt Enable
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uint32_t ueie : 1; // 7 Update event interrupt enable
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uint32_t repokie : 1; // 8 REPOKIE
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uint32_t cc2ie : 1; // 9 Capture/compare 2 interrupt enable
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uint32_t reserve1 : 2; // 10 Reserve
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uint32_t cc1oie : 1; // 12 Capture/compare 1 over-capture interrupt enable
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uint32_t cc2oie : 1; // 13 Capture/compare 2 over-capture interrupt enable
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uint32_t reserve2 : 2; // 14 Reserve
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uint32_t cc1de : 1; // 16 Capture/compare 1 DMA request enable
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uint32_t reserve3 : 8; // 17 Reserve
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uint32_t cc2de : 1; // 25 Capture/compare 2 DMA request enable
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uint32_t reserve4 : 6; // 26 Reserve
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} reg_lptim_dier_intput_t;
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typedef struct {
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uint32_t cksel : 1; // 0 Clock selector
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uint32_t ckpol : 2; // 1 Clock Polarity
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uint32_t ckflt : 2; // 3 Configurable digital filter for external clock
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uint32_t reserve0 : 1; // 5 Reserve
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uint32_t trgflt : 2; // 6 Configurable digital filter for trigger
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uint32_t reserve1 : 1; // 8 Reserve
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uint32_t presc : 3; // 9 Clock prescaler
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uint32_t reserve2 : 1; // 12 Reserve
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uint32_t trigsel : 3; // 13 Trigger selector
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uint32_t reserve3 : 1; // 16 Reserve
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uint32_t trigen : 2; // 17 Trigger enable and polarity
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uint32_t timout : 1; // 19 Timeout enable
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uint32_t wave : 1; // 20 Waveform shape
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uint32_t wavpol : 1; // 21 Waveform shape polarity
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uint32_t preload : 1; // 22 Registers update mode
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uint32_t countmode : 1; // 23 counter mode enabled
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uint32_t enc : 1; // 24 Encoder mode enable
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uint32_t reserve4 : 7; // 25 Reserve
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} reg_lptim_cfgr_t;
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typedef struct {
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uint32_t enable : 1; // 0 LPTIM Enable
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uint32_t sngstrt : 1; // 1 LPTIM start in single mode
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uint32_t cntstrt : 1; // 2 Timer start in continuous mode
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uint32_t countrst : 1; // 3 Counter reset
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uint32_t rstare : 1; // 4 Reset after read enable
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uint32_t reserve0 : 27; // 5 Reserve
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} reg_lptim_cr_t;
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typedef struct {
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uint32_t ccr1 : 16; // 0 Capture/compare 1 value
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_lptim_ccr1_t;
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typedef struct {
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uint32_t arr : 16; // 0 Auto reload value
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_lptim_arr_t;
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typedef struct {
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uint32_t cnt : 16; // 0 Counter value
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_lptim_cnt_t;
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typedef struct {
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uint32_t in1sel : 2; // 0 LPTIM input 1 selection
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uint32_t reserve0 : 2; // 2 Reserve
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uint32_t in2sel : 2; // 4 LPTIM input 2 selection
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uint32_t reserve1 : 10; // 6 Reserve
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uint32_t ic1sel : 2; // 16 LPTIM input capture 1 selection
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uint32_t reserve2 : 2; // 18 Reserve
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uint32_t ic2sel : 2; // 20 LPTIM input capture 2 selection
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uint32_t reserve3 : 10; // 22 Reserve
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} reg_lptim_cfgr2_t;
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typedef struct {
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uint32_t rep : 8; // 0 Repetition register value
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uint32_t reserve0 : 24; // 8 Reserve
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} reg_lptim_rcr_t;
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typedef struct {
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uint32_t cc1sel : 1; // 0 Capture/compare 1 selection
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uint32_t cc1e : 1; // 1 Capture/compare 1 output enable
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uint32_t cc1p : 2; // 2 Capture/compare 1 output polarity
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uint32_t reserve0 : 4; // 4 Reserve
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uint32_t ic1psc : 2; // 8 Input capture 1 prescaler
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uint32_t reserve1 : 2; // 10 Reserve
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uint32_t ic1f : 2; // 12 Input capture 1 filter
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uint32_t reserve2 : 2; // 14 Reserve
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uint32_t cc2sel : 1; // 16 Capture/compare 2 selection
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uint32_t cc2e : 1; // 17 Capture/compare 2 output enable
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uint32_t cc2p : 2; // 18 Capture/compare 2 output polarity
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uint32_t reserve3 : 4; // 20 Reserve
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uint32_t ic2psc : 2; // 24 Input capture 2 prescaler
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uint32_t reserve4 : 2; // 26 Reserve
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uint32_t ic2f : 2; // 28 Input capture 2 filter
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uint32_t reserve5 : 2; // 30 Reserve
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} reg_lptim_ccmr1_t;
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typedef struct {
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uint32_t ccr2 : 16; // 0 Capture/compare 2 value
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uint32_t reserve0 : 16; // 16 Reserve
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} reg_lptim_ccr2_t;
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typedef struct {
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uint32_t cfg1 : 4; // 0 peripheral hardware configuration 1
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uint32_t reserve0 : 4; // 4 Reserve
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uint32_t cfg2 : 8; // 8 peripheral hardware configuration 2
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uint32_t cfg3 : 1; // 16 peripheral hardware configuration 3
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uint32_t reserve1 : 15; // 17 Reserve
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} reg_lptim_hwcfgr2_t;
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typedef struct {
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uint32_t cfg1 : 8; // 0 peripheral hardware configuration 1
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uint32_t cfg2 : 8; // 8 peripheral hardware configuration 2
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uint32_t cfg3 : 4; // 16 peripheral hardware configuration 3
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uint32_t reserve0 : 4; // 20 Reserve
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uint32_t cfg4 : 8; // 24 peripheral hardware configuration 4
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} reg_lptim_hwcfgr1_t;
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typedef struct {
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volatile reg_lptim_isr_output_t isr_output;
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volatile uint32_t reserve0[-1];
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volatile reg_lptim_isr_intput_t isr_intput;
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volatile reg_lptim_icr_output_t icr_output;
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volatile uint32_t reserve1[-1];
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volatile reg_lptim_icr_intput_t icr_intput;
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volatile reg_lptim_dier_output_t dier_output;
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volatile uint32_t reserve2[-1];
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volatile reg_lptim_dier_intput_t dier_intput;
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volatile reg_lptim_cfgr_t cfgr;
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volatile reg_lptim_cr_t cr;
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volatile reg_lptim_ccr1_t ccr1;
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volatile reg_lptim_arr_t arr;
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volatile reg_lptim_cnt_t cnt;
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volatile uint32_t reserve3[1];
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volatile reg_lptim_cfgr2_t cfgr2;
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volatile reg_lptim_rcr_t rcr;
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volatile reg_lptim_ccmr1_t ccmr1;
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volatile uint32_t reserve4[1];
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volatile reg_lptim_ccr2_t ccr2;
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volatile uint32_t reserve5[237];
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volatile reg_lptim_hwcfgr2_t hwcfgr2;
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volatile reg_lptim_hwcfgr1_t hwcfgr1;
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} reg_lptim_t;
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