520 lines
69 KiB
C
Executable File
520 lines
69 KiB
C
Executable File
#include <stdint.h>
|
|
|
|
typedef struct {
|
|
uint32_t sec0 : 1; // 0 SEC0
|
|
uint32_t sec1 : 1; // 1 SEC1
|
|
uint32_t sec2 : 1; // 2 SEC2
|
|
uint32_t sec3 : 1; // 3 SEC3
|
|
uint32_t reserve0 : 28; // 4 Reserve
|
|
} reg_lpdma_seccfgr_t;
|
|
|
|
typedef struct {
|
|
uint32_t priv0 : 1; // 0 PRIV0
|
|
uint32_t priv1 : 1; // 1 PRIV1
|
|
uint32_t priv2 : 1; // 2 PRIV2
|
|
uint32_t priv3 : 1; // 3 PRIV3
|
|
uint32_t reserve0 : 28; // 4 Reserve
|
|
} reg_lpdma_privcfgr_t;
|
|
|
|
typedef struct {
|
|
uint32_t lock0 : 1; // 0 LOCK0
|
|
uint32_t lock1 : 1; // 1 LOCK1
|
|
uint32_t lock2 : 1; // 2 LOCK2
|
|
uint32_t lock3 : 1; // 3 LOCK3
|
|
uint32_t reserve0 : 28; // 4 Reserve
|
|
} reg_lpdma_rcfglockr_t;
|
|
|
|
typedef struct {
|
|
uint32_t mis0 : 1; // 0 MIS0
|
|
uint32_t mis1 : 1; // 1 MIS1
|
|
uint32_t mis2 : 1; // 2 MIS2
|
|
uint32_t mis3 : 1; // 3 MIS3
|
|
uint32_t reserve0 : 28; // 4 Reserve
|
|
} reg_lpdma_misr_t;
|
|
|
|
typedef struct {
|
|
uint32_t mis0 : 1; // 0 MIS0
|
|
uint32_t mis1 : 1; // 1 MIS1
|
|
uint32_t mis2 : 1; // 2 MIS2
|
|
uint32_t mis3 : 1; // 3 MIS3
|
|
uint32_t reserve0 : 28; // 4 Reserve
|
|
} reg_lpdma_smisr_t;
|
|
|
|
typedef struct {
|
|
uint32_t reserve0 : 16; // 0 Reserve
|
|
uint32_t lba : 16; // 16 linked-list base address of LPDMA channel x
|
|
} reg_lpdma_c0lbar_t;
|
|
|
|
typedef struct {
|
|
uint32_t reserve0 : 8; // 0 Reserve
|
|
uint32_t tcf : 1; // 8 transfer complete flag clear
|
|
uint32_t htf : 1; // 9 half transfer flag clear
|
|
uint32_t dtef : 1; // 10 data transfer error flag clear
|
|
uint32_t ulef : 1; // 11 update link transfer error flag clear
|
|
uint32_t usef : 1; // 12 user setting error flag clear
|
|
uint32_t suspf : 1; // 13 completed suspension flag clear
|
|
uint32_t tof : 1; // 14 trigger overrun flag clear
|
|
uint32_t reserve1 : 17; // 15 Reserve
|
|
} reg_lpdma_c0fcr_t;
|
|
|
|
typedef struct {
|
|
uint32_t idlef : 1; // 0 idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state).
|
|
uint32_t reserve0 : 7; // 1 Reserve
|
|
uint32_t tcf : 1; // 8 transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode LPDMA_CxTR2.TCEM[1:0].
|
|
uint32_t htf : 1; // 9 half transfer flag An half transfer event is an half block transfer that occurs when half of the bytes of the source block size (rounded-up integer of LPDMA_CxBR1.BNDT[15:0] / 2) has been transferred to the destination.
|
|
uint32_t dtef : 1; // 10 data transfer error flag
|
|
uint32_t ulef : 1; // 11 update link transfer error flag
|
|
uint32_t usef : 1; // 12 user setting error flag
|
|
uint32_t suspf : 1; // 13 completed suspension flag
|
|
uint32_t tof : 1; // 14 trigger overrun flag clear
|
|
uint32_t reserve1 : 17; // 15 Reserve
|
|
} reg_lpdma_c0sr_t;
|
|
|
|
typedef struct {
|
|
uint32_t en : 1; // 0 enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.
|
|
uint32_t reset : 1; // 1 reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (LPDMA_CxSR.SUSPF = 1 and LPDMA_CxSR.IDLEF = LPDMA_CxCR.EN = 1) - channel in disabled state (LPDMA_CxSR.IDLEF = 1 and LPDMA_CxCR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR) before enabling again the channel (see the programming sequence in ).
|
|
uint32_t susp : 1; // 2 suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in sequence.
|
|
uint32_t reserve0 : 5; // 3 Reserve
|
|
uint32_t tcie : 1; // 8 transfer complete interrupt enable
|
|
uint32_t htie : 1; // 9 half transfer complete interrupt enable
|
|
uint32_t dteie : 1; // 10 data transfer error interrupt enable
|
|
uint32_t uleie : 1; // 11 update link transfer error interrupt enable
|
|
uint32_t useie : 1; // 12 user setting error interrupt enable
|
|
uint32_t suspie : 1; // 13 completed suspension interrupt enable
|
|
uint32_t toie : 1; // 14 trigger overrun interrupt enable
|
|
uint32_t reserve1 : 1; // 15 Reserve
|
|
uint32_t lsm : 1; // 16 Link step mode First the block transfer is executed as defined by the current internal register file until LPDMA_CxBR1.BNDT[15:0 ] =0). Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1.
|
|
uint32_t reserve2 : 5; // 17 Reserve
|
|
uint32_t prio : 2; // 22 priority level of the channel x LPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
|
|
uint32_t reserve3 : 8; // 24 Reserve
|
|
} reg_lpdma_c0cr_t;
|
|
|
|
typedef struct {
|
|
uint32_t sdw_log2 : 2; // 0 binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. a source block size must be a multiple of the source data width (LPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address LPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.
|
|
uint32_t reserve0 : 1; // 2 Reserve
|
|
uint32_t sinc : 1; // 3 source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a single transfer or is incremented by the offset value corresponding to a contiguous data after a single transfer.
|
|
uint32_t reserve1 : 7; // 4 Reserve
|
|
uint32_t pam : 1; // 11 padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination transfer is equal to the data width of a single source transfer, this bit is ignored. Else: Case 1: If destination data width > source data width Case 2: If destination data width < source data width
|
|
uint32_t reserve2 : 3; // 12 Reserve
|
|
uint32_t ssec : 1; // 15 security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx =1 . A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer from the source is non-secure.
|
|
uint32_t ddw_log2 : 2; // 16 binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination single transfer must have an aligned address with its data width (start address LPDMA_CxDAR[2:0] versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and none transfer is issued.
|
|
uint32_t reserve3 : 1; // 18 Reserve
|
|
uint32_t dinc : 1; // 19 destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant after a single transfer, or is incremented by the offset value corresponding to a contiguous data after a single transfer.
|
|
uint32_t reserve4 : 11; // 20 Reserve
|
|
uint32_t dsec : 1; // 31 security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx = 1. A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer to the destination is non-secure.
|
|
} reg_lpdma_c0tr1_t;
|
|
|
|
typedef struct {
|
|
uint32_t reqsel : 5; // 0 DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per request. Note: The user must not assign a same input hardware request (same REQSEL[4:0] value) to different active DMA channels (LPDMA_CxCR.EN = 1 and LPDMA_CxTR2.SWREQ = 0 for these channels). DMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting.
|
|
uint32_t reserve0 : 4; // 5 Reserve
|
|
uint32_t swreq : 1; // 9 software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted.
|
|
uint32_t reserve1 : 1; // 10 Reserve
|
|
uint32_t breq : 1; // 11 block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:
|
|
uint32_t reserve2 : 2; // 12 Reserve
|
|
uint32_t trigm : 2; // 14 trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (LPDMA_CxCR.EN asserted) with TRIGPOL[1:0] = 0b00 or 0b11, these TRIGM[1:0] bits are ignored. Else, a DMA transfer is conditioned by at least one trigger hit: The LPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 0b01 or respectively TRIGPOL[1:0] = 0b10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[4:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the LPDMA_CxTR2 with a new value for any of TRIGSEL[4:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized, and a trigger overrun flag is reported (LPDMA_CxSR.TOF = 1), an interrupt is generated if enabled (LPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun.
|
|
uint32_t trigsel : 5; // 16 trigger event input selection These bits select the trigger event input of the LPDMA transfer (as per Programmed LPDMA1 trigger), with an active trigger event if TRIGPOL[1:0] = 00.
|
|
uint32_t reserve3 : 3; // 21 Reserve
|
|
uint32_t trigpol : 2; // 24 trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[4:0].
|
|
uint32_t reserve4 : 4; // 26 Reserve
|
|
uint32_t tcem : 2; // 30 transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1.
|
|
} reg_lpdma_c0tr2_t;
|
|
|
|
typedef struct {
|
|
uint32_t bndt : 16; // 0 block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if LPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if LPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value. - if all LPDMA_CxLLR.Uxx = 0 and if LPDMA_CxLLR.LA[15:0] = 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if LPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.
|
|
uint32_t reserve0 : 16; // 16 Reserve
|
|
} reg_lpdma_c0br1_t;
|
|
|
|
typedef struct {
|
|
uint32_t sa : 32; // 0 source address This field is the pointer to the address from which the next data is read. During the channel activity, depending on the source addressing mode (LPDMA_CxTR1.SINC), this field is either kept fixed or incremented by the data width (LPDMA_CxTR1.SDW_LOG2[1:0]) after each single source data, reflecting the next address from which data is read. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by LPDMA from the memory, provided the LLI is set with LPDMA_CxLLR.USA = 1. Note: A source address must be aligned with the programmed data width of a source single (SA[32:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
|
|
} reg_lpdma_c0sar_t;
|
|
|
|
typedef struct {
|
|
uint32_t da : 32; // 0 destination address This field is the pointer to the address from which the next data is written. During the channel activity, depending on the destination addressing mode (LPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (LPDMA_CxTR1.DDW_LOG2[21:0]) after each single destination data, reflecting the next address from which data is written. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by DMA from the memory, provided the LLI is set with LPDMA_CxLLR.UDA = 1. Note: A destination address must be aligned with the programmed data width of a destination single (DA[2:0] versus LPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
|
|
} reg_lpdma_c0dar_t;
|
|
|
|
typedef struct {
|
|
uint32_t reserve0 : 2; // 0 Reserve
|
|
uint32_t la : 14; // 2 pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file (LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.
|
|
uint32_t ull : 1; // 16 Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR register from the memory during the link transfer.
|
|
uint32_t reserve1 : 10; // 17 Reserve
|
|
uint32_t uda : 1; // 27 Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR register from the memory during the link transfer.
|
|
uint32_t usa : 1; // 28 update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer.
|
|
uint32_t ub1 : 1; // 29 Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer.
|
|
uint32_t ut2 : 1; // 30 Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer.
|
|
uint32_t ut1 : 1; // 31 Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer.
|
|
} reg_lpdma_c0llr_t;
|
|
|
|
typedef struct {
|
|
uint32_t reserve0 : 16; // 0 Reserve
|
|
uint32_t lba : 16; // 16 linked-list base address of LPDMA channel x
|
|
} reg_lpdma_c1lbar_t;
|
|
|
|
typedef struct {
|
|
uint32_t reserve0 : 8; // 0 Reserve
|
|
uint32_t tcf : 1; // 8 transfer complete flag clear
|
|
uint32_t htf : 1; // 9 half transfer flag clear
|
|
uint32_t dtef : 1; // 10 data transfer error flag clear
|
|
uint32_t ulef : 1; // 11 update link transfer error flag clear
|
|
uint32_t usef : 1; // 12 user setting error flag clear
|
|
uint32_t suspf : 1; // 13 completed suspension flag clear
|
|
uint32_t tof : 1; // 14 trigger overrun flag clear
|
|
uint32_t reserve1 : 17; // 15 Reserve
|
|
} reg_lpdma_c1fcr_t;
|
|
|
|
typedef struct {
|
|
uint32_t idlef : 1; // 0 idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state).
|
|
uint32_t reserve0 : 7; // 1 Reserve
|
|
uint32_t tcf : 1; // 8 transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode LPDMA_CxTR2.TCEM[1:0].
|
|
uint32_t htf : 1; // 9 half transfer flag An half transfer event is an half block transfer that occurs when half of the bytes of the source block size (rounded-up integer of LPDMA_CxBR1.BNDT[15:0] / 2) has been transferred to the destination.
|
|
uint32_t dtef : 1; // 10 data transfer error flag
|
|
uint32_t ulef : 1; // 11 update link transfer error flag
|
|
uint32_t usef : 1; // 12 user setting error flag
|
|
uint32_t suspf : 1; // 13 completed suspension flag
|
|
uint32_t tof : 1; // 14 trigger overrun flag clear
|
|
uint32_t reserve1 : 17; // 15 Reserve
|
|
} reg_lpdma_c1sr_t;
|
|
|
|
typedef struct {
|
|
uint32_t en : 1; // 0 enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.
|
|
uint32_t reset : 1; // 1 reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (LPDMA_CxSR.SUSPF = 1 and LPDMA_CxSR.IDLEF = LPDMA_CxCR.EN = 1) - channel in disabled state (LPDMA_CxSR.IDLEF = 1 and LPDMA_CxCR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR) before enabling again the channel (see the programming sequence in ).
|
|
uint32_t susp : 1; // 2 suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in sequence.
|
|
uint32_t reserve0 : 5; // 3 Reserve
|
|
uint32_t tcie : 1; // 8 transfer complete interrupt enable
|
|
uint32_t htie : 1; // 9 half transfer complete interrupt enable
|
|
uint32_t dteie : 1; // 10 data transfer error interrupt enable
|
|
uint32_t uleie : 1; // 11 update link transfer error interrupt enable
|
|
uint32_t useie : 1; // 12 user setting error interrupt enable
|
|
uint32_t suspie : 1; // 13 completed suspension interrupt enable
|
|
uint32_t toie : 1; // 14 trigger overrun interrupt enable
|
|
uint32_t reserve1 : 1; // 15 Reserve
|
|
uint32_t lsm : 1; // 16 Link step mode First the block transfer is executed as defined by the current internal register file until LPDMA_CxBR1.BNDT[15:0 ] =0). Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1.
|
|
uint32_t reserve2 : 5; // 17 Reserve
|
|
uint32_t prio : 2; // 22 priority level of the channel x LPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
|
|
uint32_t reserve3 : 8; // 24 Reserve
|
|
} reg_lpdma_c1cr_t;
|
|
|
|
typedef struct {
|
|
uint32_t sdw_log2 : 2; // 0 binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. a source block size must be a multiple of the source data width (LPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address LPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.
|
|
uint32_t reserve0 : 1; // 2 Reserve
|
|
uint32_t sinc : 1; // 3 source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a single transfer or is incremented by the offset value corresponding to a contiguous data after a single transfer.
|
|
uint32_t reserve1 : 7; // 4 Reserve
|
|
uint32_t pam : 1; // 11 padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination transfer is equal to the data width of a single source transfer, this bit is ignored. Else: Case 1: If destination data width > source data width Case 2: If destination data width < source data width
|
|
uint32_t reserve2 : 3; // 12 Reserve
|
|
uint32_t ssec : 1; // 15 security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx =1 . A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer from the source is non-secure.
|
|
uint32_t ddw_log2 : 2; // 16 binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination single transfer must have an aligned address with its data width (start address LPDMA_CxDAR[2:0] versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and none transfer is issued.
|
|
uint32_t reserve3 : 1; // 18 Reserve
|
|
uint32_t dinc : 1; // 19 destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant after a single transfer, or is incremented by the offset value corresponding to a contiguous data after a single transfer.
|
|
uint32_t reserve4 : 11; // 20 Reserve
|
|
uint32_t dsec : 1; // 31 security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx = 1. A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer to the destination is non-secure.
|
|
} reg_lpdma_c1tr1_t;
|
|
|
|
typedef struct {
|
|
uint32_t reqsel : 5; // 0 DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per request. Note: The user must not assign a same input hardware request (same REQSEL[4:0] value) to different active DMA channels (LPDMA_CxCR.EN = 1 and LPDMA_CxTR2.SWREQ = 0 for these channels). DMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting.
|
|
uint32_t reserve0 : 4; // 5 Reserve
|
|
uint32_t swreq : 1; // 9 software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted.
|
|
uint32_t reserve1 : 1; // 10 Reserve
|
|
uint32_t breq : 1; // 11 block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:
|
|
uint32_t reserve2 : 2; // 12 Reserve
|
|
uint32_t trigm : 2; // 14 trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (LPDMA_CxCR.EN asserted) with TRIGPOL[1:0] = 0b00 or 0b11, these TRIGM[1:0] bits are ignored. Else, a DMA transfer is conditioned by at least one trigger hit: The LPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 0b01 or respectively TRIGPOL[1:0] = 0b10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[4:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the LPDMA_CxTR2 with a new value for any of TRIGSEL[4:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized, and a trigger overrun flag is reported (LPDMA_CxSR.TOF = 1), an interrupt is generated if enabled (LPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun.
|
|
uint32_t trigsel : 5; // 16 trigger event input selection These bits select the trigger event input of the LPDMA transfer (as per Programmed LPDMA1 trigger), with an active trigger event if TRIGPOL[1:0] = 00.
|
|
uint32_t reserve3 : 3; // 21 Reserve
|
|
uint32_t trigpol : 2; // 24 trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[4:0].
|
|
uint32_t reserve4 : 4; // 26 Reserve
|
|
uint32_t tcem : 2; // 30 transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1.
|
|
} reg_lpdma_c1tr2_t;
|
|
|
|
typedef struct {
|
|
uint32_t bndt : 16; // 0 block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if LPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if LPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value. - if all LPDMA_CxLLR.Uxx = 0 and if LPDMA_CxLLR.LA[15:0] = 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if LPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.
|
|
uint32_t reserve0 : 16; // 16 Reserve
|
|
} reg_lpdma_c1br1_t;
|
|
|
|
typedef struct {
|
|
uint32_t sa : 32; // 0 source address This field is the pointer to the address from which the next data is read. During the channel activity, depending on the source addressing mode (LPDMA_CxTR1.SINC), this field is either kept fixed or incremented by the data width (LPDMA_CxTR1.SDW_LOG2[1:0]) after each single source data, reflecting the next address from which data is read. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by LPDMA from the memory, provided the LLI is set with LPDMA_CxLLR.USA = 1. Note: A source address must be aligned with the programmed data width of a source single (SA[32:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
|
|
} reg_lpdma_c1sar_t;
|
|
|
|
typedef struct {
|
|
uint32_t da : 32; // 0 destination address This field is the pointer to the address from which the next data is written. During the channel activity, depending on the destination addressing mode (LPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (LPDMA_CxTR1.DDW_LOG2[21:0]) after each single destination data, reflecting the next address from which data is written. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by DMA from the memory, provided the LLI is set with LPDMA_CxLLR.UDA = 1. Note: A destination address must be aligned with the programmed data width of a destination single (DA[2:0] versus LPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
|
|
} reg_lpdma_c1dar_t;
|
|
|
|
typedef struct {
|
|
uint32_t reserve0 : 2; // 0 Reserve
|
|
uint32_t la : 14; // 2 pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file (LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.
|
|
uint32_t ull : 1; // 16 Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR register from the memory during the link transfer.
|
|
uint32_t reserve1 : 10; // 17 Reserve
|
|
uint32_t uda : 1; // 27 Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR register from the memory during the link transfer.
|
|
uint32_t usa : 1; // 28 update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer.
|
|
uint32_t ub1 : 1; // 29 Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer.
|
|
uint32_t ut2 : 1; // 30 Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer.
|
|
uint32_t ut1 : 1; // 31 Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer.
|
|
} reg_lpdma_c1llr_t;
|
|
|
|
typedef struct {
|
|
uint32_t reserve0 : 16; // 0 Reserve
|
|
uint32_t lba : 16; // 16 linked-list base address of LPDMA channel x
|
|
} reg_lpdma_c2lbar_t;
|
|
|
|
typedef struct {
|
|
uint32_t reserve0 : 8; // 0 Reserve
|
|
uint32_t tcf : 1; // 8 transfer complete flag clear
|
|
uint32_t htf : 1; // 9 half transfer flag clear
|
|
uint32_t dtef : 1; // 10 data transfer error flag clear
|
|
uint32_t ulef : 1; // 11 update link transfer error flag clear
|
|
uint32_t usef : 1; // 12 user setting error flag clear
|
|
uint32_t suspf : 1; // 13 completed suspension flag clear
|
|
uint32_t tof : 1; // 14 trigger overrun flag clear
|
|
uint32_t reserve1 : 17; // 15 Reserve
|
|
} reg_lpdma_c2fcr_t;
|
|
|
|
typedef struct {
|
|
uint32_t idlef : 1; // 0 idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state).
|
|
uint32_t reserve0 : 7; // 1 Reserve
|
|
uint32_t tcf : 1; // 8 transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode LPDMA_CxTR2.TCEM[1:0].
|
|
uint32_t htf : 1; // 9 half transfer flag An half transfer event is an half block transfer that occurs when half of the bytes of the source block size (rounded-up integer of LPDMA_CxBR1.BNDT[15:0] / 2) has been transferred to the destination.
|
|
uint32_t dtef : 1; // 10 data transfer error flag
|
|
uint32_t ulef : 1; // 11 update link transfer error flag
|
|
uint32_t usef : 1; // 12 user setting error flag
|
|
uint32_t suspf : 1; // 13 completed suspension flag
|
|
uint32_t tof : 1; // 14 trigger overrun flag clear
|
|
uint32_t reserve1 : 17; // 15 Reserve
|
|
} reg_lpdma_c2sr_t;
|
|
|
|
typedef struct {
|
|
uint32_t en : 1; // 0 enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.
|
|
uint32_t reset : 1; // 1 reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (LPDMA_CxSR.SUSPF = 1 and LPDMA_CxSR.IDLEF = LPDMA_CxCR.EN = 1) - channel in disabled state (LPDMA_CxSR.IDLEF = 1 and LPDMA_CxCR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR) before enabling again the channel (see the programming sequence in ).
|
|
uint32_t susp : 1; // 2 suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in sequence.
|
|
uint32_t reserve0 : 5; // 3 Reserve
|
|
uint32_t tcie : 1; // 8 transfer complete interrupt enable
|
|
uint32_t htie : 1; // 9 half transfer complete interrupt enable
|
|
uint32_t dteie : 1; // 10 data transfer error interrupt enable
|
|
uint32_t uleie : 1; // 11 update link transfer error interrupt enable
|
|
uint32_t useie : 1; // 12 user setting error interrupt enable
|
|
uint32_t suspie : 1; // 13 completed suspension interrupt enable
|
|
uint32_t toie : 1; // 14 trigger overrun interrupt enable
|
|
uint32_t reserve1 : 1; // 15 Reserve
|
|
uint32_t lsm : 1; // 16 Link step mode First the block transfer is executed as defined by the current internal register file until LPDMA_CxBR1.BNDT[15:0 ] =0). Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1.
|
|
uint32_t reserve2 : 5; // 17 Reserve
|
|
uint32_t prio : 2; // 22 priority level of the channel x LPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
|
|
uint32_t reserve3 : 8; // 24 Reserve
|
|
} reg_lpdma_c2cr_t;
|
|
|
|
typedef struct {
|
|
uint32_t sdw_log2 : 2; // 0 binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. a source block size must be a multiple of the source data width (LPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address LPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.
|
|
uint32_t reserve0 : 1; // 2 Reserve
|
|
uint32_t sinc : 1; // 3 source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a single transfer or is incremented by the offset value corresponding to a contiguous data after a single transfer.
|
|
uint32_t reserve1 : 7; // 4 Reserve
|
|
uint32_t pam : 1; // 11 padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination transfer is equal to the data width of a single source transfer, this bit is ignored. Else: Case 1: If destination data width > source data width Case 2: If destination data width < source data width
|
|
uint32_t reserve2 : 3; // 12 Reserve
|
|
uint32_t ssec : 1; // 15 security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx =1 . A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer from the source is non-secure.
|
|
uint32_t ddw_log2 : 2; // 16 binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination single transfer must have an aligned address with its data width (start address LPDMA_CxDAR[2:0] versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and none transfer is issued.
|
|
uint32_t reserve3 : 1; // 18 Reserve
|
|
uint32_t dinc : 1; // 19 destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant after a single transfer, or is incremented by the offset value corresponding to a contiguous data after a single transfer.
|
|
uint32_t reserve4 : 11; // 20 Reserve
|
|
uint32_t dsec : 1; // 31 security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx = 1. A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer to the destination is non-secure.
|
|
} reg_lpdma_c2tr1_t;
|
|
|
|
typedef struct {
|
|
uint32_t reqsel : 5; // 0 DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per request. Note: The user must not assign a same input hardware request (same REQSEL[4:0] value) to different active DMA channels (LPDMA_CxCR.EN = 1 and LPDMA_CxTR2.SWREQ = 0 for these channels). DMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting.
|
|
uint32_t reserve0 : 4; // 5 Reserve
|
|
uint32_t swreq : 1; // 9 software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted.
|
|
uint32_t reserve1 : 1; // 10 Reserve
|
|
uint32_t breq : 1; // 11 block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:
|
|
uint32_t reserve2 : 2; // 12 Reserve
|
|
uint32_t trigm : 2; // 14 trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (LPDMA_CxCR.EN asserted) with TRIGPOL[1:0] = 0b00 or 0b11, these TRIGM[1:0] bits are ignored. Else, a DMA transfer is conditioned by at least one trigger hit: The LPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 0b01 or respectively TRIGPOL[1:0] = 0b10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[4:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the LPDMA_CxTR2 with a new value for any of TRIGSEL[4:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized, and a trigger overrun flag is reported (LPDMA_CxSR.TOF = 1), an interrupt is generated if enabled (LPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun.
|
|
uint32_t trigsel : 5; // 16 trigger event input selection These bits select the trigger event input of the LPDMA transfer (as per Programmed LPDMA1 trigger), with an active trigger event if TRIGPOL[1:0] = 00.
|
|
uint32_t reserve3 : 3; // 21 Reserve
|
|
uint32_t trigpol : 2; // 24 trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[4:0].
|
|
uint32_t reserve4 : 4; // 26 Reserve
|
|
uint32_t tcem : 2; // 30 transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1.
|
|
} reg_lpdma_c2tr2_t;
|
|
|
|
typedef struct {
|
|
uint32_t bndt : 16; // 0 block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if LPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if LPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value. - if all LPDMA_CxLLR.Uxx = 0 and if LPDMA_CxLLR.LA[15:0] = 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if LPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.
|
|
uint32_t reserve0 : 16; // 16 Reserve
|
|
} reg_lpdma_c2br1_t;
|
|
|
|
typedef struct {
|
|
uint32_t sa : 32; // 0 source address This field is the pointer to the address from which the next data is read. During the channel activity, depending on the source addressing mode (LPDMA_CxTR1.SINC), this field is either kept fixed or incremented by the data width (LPDMA_CxTR1.SDW_LOG2[1:0]) after each single source data, reflecting the next address from which data is read. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by LPDMA from the memory, provided the LLI is set with LPDMA_CxLLR.USA = 1. Note: A source address must be aligned with the programmed data width of a source single (SA[32:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
|
|
} reg_lpdma_c2sar_t;
|
|
|
|
typedef struct {
|
|
uint32_t da : 32; // 0 destination address This field is the pointer to the address from which the next data is written. During the channel activity, depending on the destination addressing mode (LPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (LPDMA_CxTR1.DDW_LOG2[21:0]) after each single destination data, reflecting the next address from which data is written. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by DMA from the memory, provided the LLI is set with LPDMA_CxLLR.UDA = 1. Note: A destination address must be aligned with the programmed data width of a destination single (DA[2:0] versus LPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
|
|
} reg_lpdma_c2dar_t;
|
|
|
|
typedef struct {
|
|
uint32_t reserve0 : 2; // 0 Reserve
|
|
uint32_t la : 14; // 2 pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file (LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.
|
|
uint32_t ull : 1; // 16 Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR register from the memory during the link transfer.
|
|
uint32_t reserve1 : 10; // 17 Reserve
|
|
uint32_t uda : 1; // 27 Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR register from the memory during the link transfer.
|
|
uint32_t usa : 1; // 28 update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer.
|
|
uint32_t ub1 : 1; // 29 Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer.
|
|
uint32_t ut2 : 1; // 30 Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer.
|
|
uint32_t ut1 : 1; // 31 Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer.
|
|
} reg_lpdma_c2llr_t;
|
|
|
|
typedef struct {
|
|
uint32_t reserve0 : 16; // 0 Reserve
|
|
uint32_t lba : 16; // 16 linked-list base address of LPDMA channel x
|
|
} reg_lpdma_c3lbar_t;
|
|
|
|
typedef struct {
|
|
uint32_t reserve0 : 8; // 0 Reserve
|
|
uint32_t tcf : 1; // 8 transfer complete flag clear
|
|
uint32_t htf : 1; // 9 half transfer flag clear
|
|
uint32_t dtef : 1; // 10 data transfer error flag clear
|
|
uint32_t ulef : 1; // 11 update link transfer error flag clear
|
|
uint32_t usef : 1; // 12 user setting error flag clear
|
|
uint32_t suspf : 1; // 13 completed suspension flag clear
|
|
uint32_t tof : 1; // 14 trigger overrun flag clear
|
|
uint32_t reserve1 : 17; // 15 Reserve
|
|
} reg_lpdma_c3fcr_t;
|
|
|
|
typedef struct {
|
|
uint32_t idlef : 1; // 0 idle flag This idle flag is de-asserted by hardware when the channel is enabled (LPDMA_CxCR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state).
|
|
uint32_t reserve0 : 7; // 1 Reserve
|
|
uint32_t tcf : 1; // 8 transfer complete flag A transfer complete event is a block transfer complete or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode LPDMA_CxTR2.TCEM[1:0].
|
|
uint32_t htf : 1; // 9 half transfer flag An half transfer event is an half block transfer that occurs when half of the bytes of the source block size (rounded-up integer of LPDMA_CxBR1.BNDT[15:0] / 2) has been transferred to the destination.
|
|
uint32_t dtef : 1; // 10 data transfer error flag
|
|
uint32_t ulef : 1; // 11 update link transfer error flag
|
|
uint32_t usef : 1; // 12 user setting error flag
|
|
uint32_t suspf : 1; // 13 completed suspension flag
|
|
uint32_t tof : 1; // 14 trigger overrun flag clear
|
|
uint32_t reserve1 : 17; // 15 Reserve
|
|
} reg_lpdma_c3sr_t;
|
|
|
|
typedef struct {
|
|
uint32_t en : 1; // 0 enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.
|
|
uint32_t reset : 1; // 1 reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (LPDMA_CxSR.SUSPF = 1 and LPDMA_CxSR.IDLEF = LPDMA_CxCR.EN = 1) - channel in disabled state (LPDMA_CxSR.IDLEF = 1 and LPDMA_CxCR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR) before enabling again the channel (see the programming sequence in ).
|
|
uint32_t susp : 1; // 2 suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in sequence.
|
|
uint32_t reserve0 : 5; // 3 Reserve
|
|
uint32_t tcie : 1; // 8 transfer complete interrupt enable
|
|
uint32_t htie : 1; // 9 half transfer complete interrupt enable
|
|
uint32_t dteie : 1; // 10 data transfer error interrupt enable
|
|
uint32_t uleie : 1; // 11 update link transfer error interrupt enable
|
|
uint32_t useie : 1; // 12 user setting error interrupt enable
|
|
uint32_t suspie : 1; // 13 completed suspension interrupt enable
|
|
uint32_t toie : 1; // 14 trigger overrun interrupt enable
|
|
uint32_t reserve1 : 1; // 15 Reserve
|
|
uint32_t lsm : 1; // 16 Link step mode First the block transfer is executed as defined by the current internal register file until LPDMA_CxBR1.BNDT[15:0 ] =0). Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1.
|
|
uint32_t reserve2 : 5; // 17 Reserve
|
|
uint32_t prio : 2; // 22 priority level of the channel x LPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
|
|
uint32_t reserve3 : 8; // 24 Reserve
|
|
} reg_lpdma_c3cr_t;
|
|
|
|
typedef struct {
|
|
uint32_t sdw_log2 : 2; // 0 binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. a source block size must be a multiple of the source data width (LPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address LPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.
|
|
uint32_t reserve0 : 1; // 2 Reserve
|
|
uint32_t sinc : 1; // 3 source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a single transfer or is incremented by the offset value corresponding to a contiguous data after a single transfer.
|
|
uint32_t reserve1 : 7; // 4 Reserve
|
|
uint32_t pam : 1; // 11 padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination transfer is equal to the data width of a single source transfer, this bit is ignored. Else: Case 1: If destination data width > source data width Case 2: If destination data width < source data width
|
|
uint32_t reserve2 : 3; // 12 Reserve
|
|
uint32_t ssec : 1; // 15 security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx =1 . A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer from the source is non-secure.
|
|
uint32_t ddw_log2 : 2; // 16 binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination single transfer must have an aligned address with its data width (start address LPDMA_CxDAR[2:0] versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and none transfer is issued.
|
|
uint32_t reserve3 : 1; // 18 Reserve
|
|
uint32_t dinc : 1; // 19 destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant after a single transfer, or is incremented by the offset value corresponding to a contiguous data after a single transfer.
|
|
uint32_t reserve4 : 11; // 20 Reserve
|
|
uint32_t dsec : 1; // 31 security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx = 1. A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer to the destination is non-secure.
|
|
} reg_lpdma_c3tr1_t;
|
|
|
|
typedef struct {
|
|
uint32_t reqsel : 5; // 0 DMA hardware request selection These bits are ignored if channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per request. Note: The user must not assign a same input hardware request (same REQSEL[4:0] value) to different active DMA channels (LPDMA_CxCR.EN = 1 and LPDMA_CxTR2.SWREQ = 0 for these channels). DMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting.
|
|
uint32_t reserve0 : 4; // 5 Reserve
|
|
uint32_t swreq : 1; // 9 software request This bit is internally taken into account when LPDMA_CxCR.EN is asserted.
|
|
uint32_t reserve1 : 1; // 10 Reserve
|
|
uint32_t breq : 1; // 11 block hardware request If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:
|
|
uint32_t reserve2 : 2; // 12 Reserve
|
|
uint32_t trigm : 2; // 14 trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (LPDMA_CxCR.EN asserted) with TRIGPOL[1:0] = 0b00 or 0b11, these TRIGM[1:0] bits are ignored. Else, a DMA transfer is conditioned by at least one trigger hit: The LPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 0b01 or respectively TRIGPOL[1:0] = 0b10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[4:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the LPDMA_CxTR2 with a new value for any of TRIGSEL[4:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized, and a trigger overrun flag is reported (LPDMA_CxSR.TOF = 1), an interrupt is generated if enabled (LPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun.
|
|
uint32_t trigsel : 5; // 16 trigger event input selection These bits select the trigger event input of the LPDMA transfer (as per Programmed LPDMA1 trigger), with an active trigger event if TRIGPOL[1:0] = 00.
|
|
uint32_t reserve3 : 3; // 21 Reserve
|
|
uint32_t trigpol : 2; // 24 trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[4:0].
|
|
uint32_t reserve4 : 4; // 26 Reserve
|
|
uint32_t tcem : 2; // 30 transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1.
|
|
} reg_lpdma_c3tr2_t;
|
|
|
|
typedef struct {
|
|
uint32_t bndt : 16; // 0 block number of data bytes to transfer from the source Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if LPDMA_CxLLR.UB1 = 1, this field is updated by the LLI in the memory. - if LPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value. - if all LPDMA_CxLLR.Uxx = 0 and if LPDMA_CxLLR.LA[15:0] = 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if LPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.
|
|
uint32_t reserve0 : 16; // 16 Reserve
|
|
} reg_lpdma_c3br1_t;
|
|
|
|
typedef struct {
|
|
uint32_t sa : 32; // 0 source address This field is the pointer to the address from which the next data is read. During the channel activity, depending on the source addressing mode (LPDMA_CxTR1.SINC), this field is either kept fixed or incremented by the data width (LPDMA_CxTR1.SDW_LOG2[1:0]) after each single source data, reflecting the next address from which data is read. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by LPDMA from the memory, provided the LLI is set with LPDMA_CxLLR.USA = 1. Note: A source address must be aligned with the programmed data width of a source single (SA[32:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
|
|
} reg_lpdma_c3sar_t;
|
|
|
|
typedef struct {
|
|
uint32_t da : 32; // 0 destination address This field is the pointer to the address from which the next data is written. During the channel activity, depending on the destination addressing mode (LPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (LPDMA_CxTR1.DDW_LOG2[21:0]) after each single destination data, reflecting the next address from which data is written. In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by DMA from the memory, provided the LLI is set with LPDMA_CxLLR.UDA = 1. Note: A destination address must be aligned with the programmed data width of a destination single (DA[2:0] versus LPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.
|
|
} reg_lpdma_c3dar_t;
|
|
|
|
typedef struct {
|
|
uint32_t reserve0 : 2; // 0 Reserve
|
|
uint32_t la : 14; // 2 pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file (LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.
|
|
uint32_t ull : 1; // 16 Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR register from the memory during the link transfer.
|
|
uint32_t reserve1 : 10; // 17 Reserve
|
|
uint32_t uda : 1; // 27 Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR register from the memory during the link transfer.
|
|
uint32_t usa : 1; // 28 update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer.
|
|
uint32_t ub1 : 1; // 29 Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer.
|
|
uint32_t ut2 : 1; // 30 Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer.
|
|
uint32_t ut1 : 1; // 31 Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer.
|
|
} reg_lpdma_c3llr_t;
|
|
|
|
typedef struct {
|
|
volatile reg_lpdma_seccfgr_t seccfgr;
|
|
volatile reg_lpdma_privcfgr_t privcfgr;
|
|
volatile reg_lpdma_rcfglockr_t rcfglockr;
|
|
volatile reg_lpdma_misr_t misr;
|
|
volatile reg_lpdma_smisr_t smisr;
|
|
volatile uint32_t reserve0[15];
|
|
volatile reg_lpdma_c0lbar_t c0lbar;
|
|
volatile uint32_t reserve1[2];
|
|
volatile reg_lpdma_c0fcr_t c0fcr;
|
|
volatile reg_lpdma_c0sr_t c0sr;
|
|
volatile reg_lpdma_c0cr_t c0cr;
|
|
volatile uint32_t reserve2[10];
|
|
volatile reg_lpdma_c0tr1_t c0tr1;
|
|
volatile reg_lpdma_c0tr2_t c0tr2;
|
|
volatile reg_lpdma_c0br1_t c0br1;
|
|
volatile reg_lpdma_c0sar_t c0sar;
|
|
volatile reg_lpdma_c0dar_t c0dar;
|
|
volatile uint32_t reserve3[10];
|
|
volatile reg_lpdma_c0llr_t c0llr;
|
|
volatile reg_lpdma_c1lbar_t c1lbar;
|
|
volatile uint32_t reserve4[2];
|
|
volatile reg_lpdma_c1fcr_t c1fcr;
|
|
volatile reg_lpdma_c1sr_t c1sr;
|
|
volatile reg_lpdma_c1cr_t c1cr;
|
|
volatile uint32_t reserve5[10];
|
|
volatile reg_lpdma_c1tr1_t c1tr1;
|
|
volatile reg_lpdma_c1tr2_t c1tr2;
|
|
volatile reg_lpdma_c1br1_t c1br1;
|
|
volatile reg_lpdma_c1sar_t c1sar;
|
|
volatile reg_lpdma_c1dar_t c1dar;
|
|
volatile uint32_t reserve6[10];
|
|
volatile reg_lpdma_c1llr_t c1llr;
|
|
volatile reg_lpdma_c2lbar_t c2lbar;
|
|
volatile uint32_t reserve7[2];
|
|
volatile reg_lpdma_c2fcr_t c2fcr;
|
|
volatile reg_lpdma_c2sr_t c2sr;
|
|
volatile reg_lpdma_c2cr_t c2cr;
|
|
volatile uint32_t reserve8[10];
|
|
volatile reg_lpdma_c2tr1_t c2tr1;
|
|
volatile reg_lpdma_c2tr2_t c2tr2;
|
|
volatile reg_lpdma_c2br1_t c2br1;
|
|
volatile reg_lpdma_c2sar_t c2sar;
|
|
volatile reg_lpdma_c2dar_t c2dar;
|
|
volatile uint32_t reserve9[10];
|
|
volatile reg_lpdma_c2llr_t c2llr;
|
|
volatile reg_lpdma_c3lbar_t c3lbar;
|
|
volatile uint32_t reserve10[2];
|
|
volatile reg_lpdma_c3fcr_t c3fcr;
|
|
volatile reg_lpdma_c3sr_t c3sr;
|
|
volatile reg_lpdma_c3cr_t c3cr;
|
|
volatile uint32_t reserve11[10];
|
|
volatile reg_lpdma_c3tr1_t c3tr1;
|
|
volatile reg_lpdma_c3tr2_t c3tr2;
|
|
volatile reg_lpdma_c3br1_t c3br1;
|
|
volatile reg_lpdma_c3sar_t c3sar;
|
|
volatile reg_lpdma_c3dar_t c3dar;
|
|
volatile uint32_t reserve12[10];
|
|
volatile reg_lpdma_c3llr_t c3llr;
|
|
} reg_lpdma_t;
|
|
|