881 lines
63 KiB
C
Executable File
881 lines
63 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t latency : 4; // 0 Latency These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory access time. ...
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uint32_t reserve0 : 4; // 4 Reserve
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uint32_t prften : 1; // 8 Prefetch enable This bit enables the prefetch buffer in the embedded Flash memory.
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uint32_t reserve1 : 2; // 9 Reserve
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uint32_t lpm : 1; // 11 Low-power read mode This bit puts the Flash memory in low-power read mode.
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uint32_t pdreq1 : 1; // 12 Bank 1 power-down mode request This bit is write-protected with FLASH_PDKEY1R. This bit requests bank 1 to enter power-down mode. When bank 1 enters power-down mode, this bit is cleared by hardware and the PDKEY1R is locked.
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uint32_t pdreq2 : 1; // 13 Bank 2 power-down mode request This bit is write-protected with FLASH_PDKEY2R. This bit requests bank 2 to enter power-down mode. When bank 2 enters power-down mode, this bit is cleared by hardware and the PDKEY2R is locked.
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uint32_t sleep_pd : 1; // 14 Flash memory power-down mode during Sleep mode This bit determines whether the Flash memory is in power-down mode or Idle mode when the device is in Sleep mode. The Flash must not be put in power-down while a program or an erase operation is on-going.
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uint32_t reserve2 : 17; // 15 Reserve
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} reg_flash_acr_t;
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typedef struct {
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uint32_t nskey : 32; // 0 Flash memory non-secure key
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} reg_flash_nskeyr_t;
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typedef struct {
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uint32_t seckey : 32; // 0 Flash memory secure key
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} reg_flash_seckeyr_t;
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typedef struct {
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uint32_t optkey : 32; // 0 Option byte key
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} reg_flash_optkeyr_t;
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typedef struct {
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uint32_t pdkey1 : 32; // 0 Bank 1 power-down key
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} reg_flash_pdkey1r_t;
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typedef struct {
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uint32_t pdkey2 : 32; // 0 Bank 2 power-down key
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} reg_flash_pdkey2r_t;
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typedef struct {
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uint32_t eop : 1; // 0 Non-secure end of operation
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uint32_t operr : 1; // 1 Non-secure operation error
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uint32_t reserve0 : 1; // 2 Reserve
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uint32_t progerr : 1; // 3 Non-secure programming error This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1.
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uint32_t wrperr : 1; // 4 Non-secure write protection error This bit is set by hardware when an non-secure address to be erased/programmed belongs to a write-protected part (by WRP, HDP or RDP level 1) of the Flash memory. This bit is cleared by writing 1. Refer to for full conditions of error flag setting.
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uint32_t pgaerr : 1; // 5 Non-secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1.
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uint32_t sizerr : 1; // 6 Non-secure size error This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1.
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uint32_t pgserr : 1; // 7 Non-secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to for full conditions of error flag setting.
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uint32_t reserve1 : 5; // 8 Reserve
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uint32_t optwerr : 1; // 13 Option write error This bit is set by hardware when the options bytes are written with an invalid configuration. It is cleared by writing 1. Refer to for full conditions of error flag setting.
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uint32_t reserve2 : 2; // 14 Reserve
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uint32_t bsy : 1; // 16 Non-secure busy This indicates that a Flash memory secure or non-secure operation is in progress. This bit is set at the beginning of a Flash operation and reset when the operation finishes or when an error occurs.
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uint32_t wdw : 1; // 17 Non-secure wait data to write This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory.
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uint32_t oem1lock : 1; // 18 OEM1 lock This bit indicates that the OEM1 RDP key read during the OBL is not virgin. When set, the OEM1 RDP lock mechanism is active.
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uint32_t oem2lock : 1; // 19 OEM2 lock This bit indicates that the OEM2 RDP key read during the OBL is not virgin. When set, the OEM2 RDP lock mechanism is active.
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uint32_t pd1 : 1; // 20 Bank 1 in power-down mode This bit indicates that the Flash memory bank 1 is in power-down state. It is reset when bank 1 is in normal mode or being awaken.
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uint32_t pd2 : 1; // 21 Bank 2 in power-down mode This bit indicates that the Flash memory bank 2 is in power-down state. It is reset when bank 2 is in normal mode or being awaken.
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uint32_t reserve3 : 10; // 22 Reserve
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} reg_flash_nssr_t;
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typedef struct {
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uint32_t eop : 1; // 0 Secure end of operation This bit is set by hardware when one or more Flash memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_SECCR). This bit is cleared by writing 1.
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uint32_t operr : 1; // 1 Secure operation error This bit is set by hardware when a Flash memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1.
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uint32_t reserve0 : 1; // 2 Reserve
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uint32_t progerr : 1; // 3 Secure programming error This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1.
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uint32_t wrperr : 1; // 4 Secure write protection error This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP, PCROP, HDP or RDP level 1) of the Flash memory.This bit is cleared by writing 1. Refer to for full conditions of error flag setting.
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uint32_t pgaerr : 1; // 5 Secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1.
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uint32_t sizerr : 1; // 6 Secure size error This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1.
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uint32_t pgserr : 1; // 7 Secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to for full conditions of error flag setting.
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uint32_t reserve1 : 8; // 8 Reserve
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uint32_t bsy : 1; // 16 Secure busy This bit indicates that a Flash memory secure or non-secure operation is in progress. This is set on the beginning of a Flash operation and reset when the operation finishes or when an error occurs.
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uint32_t wdw : 1; // 17 Secure wait data to write This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory.
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uint32_t reserve2 : 14; // 18 Reserve
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} reg_flash_secsr_t;
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typedef struct {
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uint32_t pg : 1; // 0 Non-secure programming
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uint32_t per : 1; // 1 Non-secure page erase
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uint32_t mer1 : 1; // 2 Non-secure bank 1 mass erase This bit triggers the bank 1 non-secure mass erase (all bank 1 user pages) when set.
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uint32_t pnb : 7; // 3 Non-secure page number selection These bits select the page to erase. ...
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uint32_t reserve0 : 1; // 10 Reserve
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uint32_t bker : 1; // 11 Non-secure bank selection for page erase
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uint32_t reserve1 : 2; // 12 Reserve
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uint32_t bwr : 1; // 14 Non-secure burst write programming mode When set, this bit selects the burst write programming mode.
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uint32_t mer2 : 1; // 15 Non-secure bank 2 mass erase This bit triggers the bank 2 non-secure mass erase (all bank 2 user pages) when set.
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uint32_t strt : 1; // 16 Non-secure start This bit triggers a non-secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR bit in FLASH_NSSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_NSSR.
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uint32_t optstrt : 1; // 17 Options modification start This bit triggers an options operation when set. It can not be written if OPTLOCK bit is set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_NSSR.
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uint32_t reserve2 : 6; // 18 Reserve
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uint32_t eopie : 1; // 24 Non-secure end of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_NSSR is set to 1.
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uint32_t errie : 1; // 25 Non-secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_NSSR is set to 1.
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uint32_t reserve3 : 1; // 26 Reserve
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uint32_t obl_launch: 1; // 27 Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set.
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uint32_t reserve4 : 2; // 28 Reserve
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uint32_t optlock : 1; // 30 Option lock This bit is set only. When set, all bits concerning user options in FLASH_NSCR register are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit in the FLASH_NSCR must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset.
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uint32_t lock : 1; // 31 Non-secure lock This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_NSKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset.
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} reg_flash_nscr_t;
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typedef struct {
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uint32_t pg : 1; // 0 Secure programming
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uint32_t per : 1; // 1 Secure page erase
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uint32_t mer1 : 1; // 2 Secure bank 1 mass erase This bit triggers the bank 1 secure mass erase (all bank 1 user pages) when set.
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uint32_t pnb : 7; // 3 Secure page number selection These bits select the page to erase: ...
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uint32_t reserve0 : 1; // 10 Reserve
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uint32_t bker : 1; // 11 Secure bank selection for page erase
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uint32_t reserve1 : 2; // 12 Reserve
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uint32_t bwr : 1; // 14 Secure burst write programming mode When set, this bit selects the burst write programming mode.
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uint32_t mer2 : 1; // 15 Secure bank 2 mass erase This bit triggers the bank 2 secure mass erase (all bank 2 user pages) when set.
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uint32_t strt : 1; // 16 Secure start This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR.
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uint32_t reserve2 : 7; // 17 Reserve
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uint32_t eopie : 1; // 24 Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SECSR is set to 1.
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uint32_t errie : 1; // 25 Secure error interrupt enable
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uint32_t rderrie : 1; // 26 Secure PCROP read error interrupt enable
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uint32_t reserve3 : 2; // 27 Reserve
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uint32_t inv : 1; // 29 Flash memory security state invert This bit inverts the Flash memory security state.
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uint32_t reserve4 : 1; // 30 Reserve
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uint32_t lock : 1; // 31 Secure lock This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset.
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} reg_flash_seccr_t;
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typedef struct {
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uint32_t addr_ecc : 20; // 0 ECC fail address
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uint32_t reserve0 : 1; // 20 Reserve
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uint32_t bk_ecc : 1; // 21 ECC fail bank
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uint32_t sysf_ecc : 1; // 22 System Flash memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory.
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uint32_t reserve1 : 1; // 23 Reserve
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uint32_t eccie : 1; // 24 ECC correction interrupt enable This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR register is set.
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uint32_t reserve2 : 5; // 25 Reserve
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uint32_t eccc : 1; // 30 ECC correction This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1.
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uint32_t eccd : 1; // 31 ECC detection This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1.
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} reg_flash_eccr_t;
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typedef struct {
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uint32_t addr_op : 20; // 0 Interrupted operation address This field indicates which address in the Flash memory was accessed when reset occurred. The address is given by bank from address 0x0 0000 to 0xF FFF0.
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uint32_t reserve0 : 1; // 20 Reserve
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uint32_t bk_op : 1; // 21 Interrupted operation bank This bit indicates which Flash memory bank was accessed when reset occurred
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uint32_t sysf_op : 1; // 22 Operation in system Flash memory interrupted This bit indicates that the reset occurred during an operation in the system Flash memory.
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uint32_t reserve1 : 6; // 23 Reserve
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uint32_t code_op : 3; // 29 Flash memory operation code This field indicates which Flash memory operation has been interrupted by a system reset:
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} reg_flash_opsr_t;
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typedef struct {
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uint32_t rdp : 8; // 0 Readout protection level Others: Level 1 (memories readout protection active) Note: Refer to for more details.
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uint32_t bor_lev : 3; // 8 BOR reset level These bits contain the VDD supply level threshold that activates/releases the reset.
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uint32_t reserve0 : 1; // 11 Reserve
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uint32_t nrst_stop : 1; // 12 Reset generation in Stop mode
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uint32_t nrst_stdby: 1; // 13 Reset generation in Standby mode
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uint32_t nrst_shdw : 1; // 14 Reset generation in Shutdown mode
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uint32_t sram1345_rst: 1; // 15 SRAM1, SRAM3 and SRAM4 erase upon system reset
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uint32_t iwdg_sw : 1; // 16 Independent watchdog selection
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uint32_t iwdg_stop : 1; // 17 Independent watchdog counter freeze in Stop mode
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uint32_t iwdg_stdby: 1; // 18 Independent watchdog counter freeze in Standby mode
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uint32_t wwdg_sw : 1; // 19 Window watchdog selection
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uint32_t swap_bank : 1; // 20 Swap banks
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uint32_t dualbank : 1; // 21 Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices
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uint32_t bkpram_ecc: 1; // 22 Backup RAM ECC detection and correction enable
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uint32_t sram3_ecc : 1; // 23 SRAM3 ECC detection and correction enable
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uint32_t sram2_ecc : 1; // 24 SRAM2 ECC detection and correction enable
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uint32_t sram2_rst : 1; // 25 SRAM2 erase when system reset
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uint32_t nswboot0 : 1; // 26 Software BOOT0
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uint32_t nboot0 : 1; // 27 nBOOT0 option bit
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uint32_t pa15_pupen: 1; // 28 PA15 pull-up enable
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uint32_t io_vdd_hslv: 1; // 29 High-speed IO at low VDD voltage configuration bit This bit can be set only with VDD below 2.5V
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uint32_t io_vddio2_hslv: 1; // 30 High-speed IO at low VDDIO2 voltage configuration bit This bit can be set only with VDDIO2 below 2.5 V.
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uint32_t tzen : 1; // 31 Global TrustZone security enable
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} reg_flash_optr_t;
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typedef struct {
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uint32_t reserve0 : 7; // 0 Reserve
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uint32_t nsbootadd0: 25; // 7 Non-secure boot base address 0 The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: NSBOOTADD0[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000) NSBOOTADD0[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000) NSBOOTADD0[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000)
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} reg_flash_nsbootadd0r_t;
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typedef struct {
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uint32_t reserve0 : 7; // 0 Reserve
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uint32_t nsbootadd1: 25; // 7 Non-secure boot address 1 The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: NSBOOTADD1[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000) NSBOOTADD1[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000) NSBOOTADD1[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000)
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} reg_flash_nsbootadd1r_t;
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typedef struct {
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uint32_t boot_lock : 1; // 0 Boot lock When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP at level 0.
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uint32_t reserve0 : 6; // 1 Reserve
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uint32_t secbootadd0: 25; // 7 Secure boot base address 0 The secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: SECBOOTADD0[24:0] = 0x018 0000: Boot from secure Flash memory (0x0C00 0000) SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS (0x0FF8 0000) SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000)
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} reg_flash_secbootadd0r_t;
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typedef struct {
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uint32_t secwm1_pstrt: 7; // 0 Start page of first secure area This field contains the first page of the secure area in bank 1.
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uint32_t reserve0 : 9; // 7 Reserve
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uint32_t secwm1_pend: 7; // 16 End page of first secure area This field contains the last page of the secure area in bank 1.
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uint32_t reserve1 : 9; // 23 Reserve
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} reg_flash_secwm1r1_t;
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typedef struct {
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uint32_t reserve0 : 16; // 0 Reserve
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uint32_t hdp1_pend : 7; // 16 End page of first hide protection area This field contains the last page of the HDP area in bank 1.
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uint32_t reserve1 : 8; // 23 Reserve
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uint32_t hdp1en : 1; // 31 Hide protection first area enable
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} reg_flash_secwm1r2_t;
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typedef struct {
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uint32_t wrp1a_pstrt: 7; // 0 bank 1 WPR first area A start page This field contains the first page of the first WPR area for bank 1.
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uint32_t reserve0 : 9; // 7 Reserve
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uint32_t wrp1a_pend: 7; // 16 Bank 1 WPR first area A end page This field contains the last page of the first WPR area in bank 1.
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uint32_t reserve1 : 8; // 23 Reserve
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uint32_t unlock : 1; // 31 Bank 1 WPR first area A unlock
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} reg_flash_wrp1ar_t;
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typedef struct {
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uint32_t wrp1b_pstrt: 7; // 0 Bank 1 WRP second area B start page This field contains the first page of the second WRP area for bank 1.
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uint32_t reserve0 : 9; // 7 Reserve
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uint32_t wrp1b_pend: 7; // 16 Bank 1 WRP second area B end page This field contains the last page of the second WRP area in bank 1.
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uint32_t reserve1 : 8; // 23 Reserve
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uint32_t unlock : 1; // 31 Bank 1 WPR second area B unlock
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} reg_flash_wrp1br_t;
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typedef struct {
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uint32_t secwm2_pstrt: 7; // 0 Start page of second secure area This field contains the first page of the secure area in bank 2.
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uint32_t reserve0 : 9; // 7 Reserve
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uint32_t secwm2_pend: 7; // 16 End page of second secure area This field contains the last page of the secure area in bank 2.
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uint32_t reserve1 : 9; // 23 Reserve
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} reg_flash_secwm2r1_t;
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typedef struct {
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uint32_t reserve0 : 16; // 0 Reserve
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uint32_t hdp2_pend : 7; // 16 End page of hide protection second area HDP2_PEND contains the last page of the HDP area in bank 2.
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uint32_t reserve1 : 8; // 23 Reserve
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uint32_t hdp2en : 1; // 31 Hide protection second area enable
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} reg_flash_secwm2r2_t;
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typedef struct {
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uint32_t wrp2a_pstrt: 7; // 0 Bank 2 WPR first area A start page This field contains the first page of the first WRP area for bank 2.
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uint32_t reserve0 : 9; // 7 Reserve
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uint32_t wrp2a_pend: 7; // 16 Bank 2 WPR first area A end page This field contains the last page of the first WRP area in bank 2.
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uint32_t reserve1 : 8; // 23 Reserve
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uint32_t unlock : 1; // 31 Bank 2 WPR first area A unlock
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} reg_flash_wrp2ar_t;
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typedef struct {
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uint32_t wrp2b_pstrt: 7; // 0 Bank 2 WPR second area B start page This field contains the first page of the second WRP area for bank 2.
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uint32_t reserve0 : 9; // 7 Reserve
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uint32_t wrp2b_pend: 7; // 16 Bank 2 WPR second area B end page This field contains the last page of the second WRP area in bank 2.
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uint32_t reserve1 : 8; // 23 Reserve
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uint32_t unlock : 1; // 31 Bank 2 WPR second area B unlock
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} reg_flash_wrp2br_t;
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typedef struct {
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uint32_t oem1key : 32; // 0 OEM1 least significant bytes key
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} reg_flash_oem1keyr1_t;
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typedef struct {
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uint32_t oem1key : 32; // 0 OEM1 most significant bytes key
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} reg_flash_oem1keyr2_t;
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typedef struct {
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uint32_t oem2key : 32; // 0 OEM2 least significant bytes key
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} reg_flash_oem2keyr1_t;
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typedef struct {
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uint32_t oem2key : 32; // 0 OEM2 most significant bytes key
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} reg_flash_oem2keyr2_t;
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typedef struct {
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uint32_t sec1bb0 : 1; // 0 page secure/non-secure attribution
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uint32_t sec1bb1 : 1; // 1 page secure/non-secure attribution
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uint32_t sec1bb2 : 1; // 2 page secure/non-secure attribution
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uint32_t sec1bb3 : 1; // 3 page secure/non-secure attribution
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uint32_t sec1bb4 : 1; // 4 page secure/non-secure attribution
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uint32_t sec1bb5 : 1; // 5 page secure/non-secure attribution
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uint32_t sec1bb6 : 1; // 6 page secure/non-secure attribution
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uint32_t sec1bb7 : 1; // 7 page secure/non-secure attribution
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uint32_t sec1bb8 : 1; // 8 page secure/non-secure attribution
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|
uint32_t sec1bb9 : 1; // 9 page secure/non-secure attribution
|
|
uint32_t sec1bb10 : 1; // 10 page secure/non-secure attribution
|
|
uint32_t sec1bb11 : 1; // 11 page secure/non-secure attribution
|
|
uint32_t sec1bb12 : 1; // 12 page secure/non-secure attribution
|
|
uint32_t sec1bb13 : 1; // 13 page secure/non-secure attribution
|
|
uint32_t sec1bb14 : 1; // 14 page secure/non-secure attribution
|
|
uint32_t sec1bb15 : 1; // 15 page secure/non-secure attribution
|
|
uint32_t sec1bb16 : 1; // 16 page secure/non-secure attribution
|
|
uint32_t sec1bb17 : 1; // 17 page secure/non-secure attribution
|
|
uint32_t sec1bb18 : 1; // 18 page secure/non-secure attribution
|
|
uint32_t sec1bb19 : 1; // 19 page secure/non-secure attribution
|
|
uint32_t sec1bb20 : 1; // 20 page secure/non-secure attribution
|
|
uint32_t sec1bb21 : 1; // 21 page secure/non-secure attribution
|
|
uint32_t sec1bb22 : 1; // 22 page secure/non-secure attribution
|
|
uint32_t sec1bb23 : 1; // 23 page secure/non-secure attribution
|
|
uint32_t sec1bb24 : 1; // 24 page secure/non-secure attribution
|
|
uint32_t sec1bb25 : 1; // 25 page secure/non-secure attribution
|
|
uint32_t sec1bb26 : 1; // 26 page secure/non-secure attribution
|
|
uint32_t sec1bb27 : 1; // 27 page secure/non-secure attribution
|
|
uint32_t sec1bb28 : 1; // 28 page secure/non-secure attribution
|
|
uint32_t sec1bb29 : 1; // 29 page secure/non-secure attribution
|
|
uint32_t sec1bb30 : 1; // 30 page secure/non-secure attribution
|
|
uint32_t sec1bb31 : 1; // 31 page secure/non-secure attribution
|
|
} reg_flash_sec1bbr1_t;
|
|
|
|
typedef struct {
|
|
uint32_t sec1bb0 : 1; // 0 page secure/non-secure attribution
|
|
uint32_t sec1bb1 : 1; // 1 page secure/non-secure attribution
|
|
uint32_t sec1bb2 : 1; // 2 page secure/non-secure attribution
|
|
uint32_t sec1bb3 : 1; // 3 page secure/non-secure attribution
|
|
uint32_t sec1bb4 : 1; // 4 page secure/non-secure attribution
|
|
uint32_t sec1bb5 : 1; // 5 page secure/non-secure attribution
|
|
uint32_t sec1bb6 : 1; // 6 page secure/non-secure attribution
|
|
uint32_t sec1bb7 : 1; // 7 page secure/non-secure attribution
|
|
uint32_t sec1bb8 : 1; // 8 page secure/non-secure attribution
|
|
uint32_t sec1bb9 : 1; // 9 page secure/non-secure attribution
|
|
uint32_t sec1bb10 : 1; // 10 page secure/non-secure attribution
|
|
uint32_t sec1bb11 : 1; // 11 page secure/non-secure attribution
|
|
uint32_t sec1bb12 : 1; // 12 page secure/non-secure attribution
|
|
uint32_t sec1bb13 : 1; // 13 page secure/non-secure attribution
|
|
uint32_t sec1bb14 : 1; // 14 page secure/non-secure attribution
|
|
uint32_t sec1bb15 : 1; // 15 page secure/non-secure attribution
|
|
uint32_t sec1bb16 : 1; // 16 page secure/non-secure attribution
|
|
uint32_t sec1bb17 : 1; // 17 page secure/non-secure attribution
|
|
uint32_t sec1bb18 : 1; // 18 page secure/non-secure attribution
|
|
uint32_t sec1bb19 : 1; // 19 page secure/non-secure attribution
|
|
uint32_t sec1bb20 : 1; // 20 page secure/non-secure attribution
|
|
uint32_t sec1bb21 : 1; // 21 page secure/non-secure attribution
|
|
uint32_t sec1bb22 : 1; // 22 page secure/non-secure attribution
|
|
uint32_t sec1bb23 : 1; // 23 page secure/non-secure attribution
|
|
uint32_t sec1bb24 : 1; // 24 page secure/non-secure attribution
|
|
uint32_t sec1bb25 : 1; // 25 page secure/non-secure attribution
|
|
uint32_t sec1bb26 : 1; // 26 page secure/non-secure attribution
|
|
uint32_t sec1bb27 : 1; // 27 page secure/non-secure attribution
|
|
uint32_t sec1bb28 : 1; // 28 page secure/non-secure attribution
|
|
uint32_t sec1bb29 : 1; // 29 page secure/non-secure attribution
|
|
uint32_t sec1bb30 : 1; // 30 page secure/non-secure attribution
|
|
uint32_t sec1bb31 : 1; // 31 page secure/non-secure attribution
|
|
} reg_flash_sec1bbr2_t;
|
|
|
|
typedef struct {
|
|
uint32_t sec1bb0 : 1; // 0 page secure/non-secure attribution
|
|
uint32_t sec1bb1 : 1; // 1 page secure/non-secure attribution
|
|
uint32_t sec1bb2 : 1; // 2 page secure/non-secure attribution
|
|
uint32_t sec1bb3 : 1; // 3 page secure/non-secure attribution
|
|
uint32_t sec1bb4 : 1; // 4 page secure/non-secure attribution
|
|
uint32_t sec1bb5 : 1; // 5 page secure/non-secure attribution
|
|
uint32_t sec1bb6 : 1; // 6 page secure/non-secure attribution
|
|
uint32_t sec1bb7 : 1; // 7 page secure/non-secure attribution
|
|
uint32_t sec1bb8 : 1; // 8 page secure/non-secure attribution
|
|
uint32_t sec1bb9 : 1; // 9 page secure/non-secure attribution
|
|
uint32_t sec1bb10 : 1; // 10 page secure/non-secure attribution
|
|
uint32_t sec1bb11 : 1; // 11 page secure/non-secure attribution
|
|
uint32_t sec1bb12 : 1; // 12 page secure/non-secure attribution
|
|
uint32_t sec1bb13 : 1; // 13 page secure/non-secure attribution
|
|
uint32_t sec1bb14 : 1; // 14 page secure/non-secure attribution
|
|
uint32_t sec1bb15 : 1; // 15 page secure/non-secure attribution
|
|
uint32_t sec1bb16 : 1; // 16 page secure/non-secure attribution
|
|
uint32_t sec1bb17 : 1; // 17 page secure/non-secure attribution
|
|
uint32_t sec1bb18 : 1; // 18 page secure/non-secure attribution
|
|
uint32_t sec1bb19 : 1; // 19 page secure/non-secure attribution
|
|
uint32_t sec1bb20 : 1; // 20 page secure/non-secure attribution
|
|
uint32_t sec1bb21 : 1; // 21 page secure/non-secure attribution
|
|
uint32_t sec1bb22 : 1; // 22 page secure/non-secure attribution
|
|
uint32_t sec1bb23 : 1; // 23 page secure/non-secure attribution
|
|
uint32_t sec1bb24 : 1; // 24 page secure/non-secure attribution
|
|
uint32_t sec1bb25 : 1; // 25 page secure/non-secure attribution
|
|
uint32_t sec1bb26 : 1; // 26 page secure/non-secure attribution
|
|
uint32_t sec1bb27 : 1; // 27 page secure/non-secure attribution
|
|
uint32_t sec1bb28 : 1; // 28 page secure/non-secure attribution
|
|
uint32_t sec1bb29 : 1; // 29 page secure/non-secure attribution
|
|
uint32_t sec1bb30 : 1; // 30 page secure/non-secure attribution
|
|
uint32_t sec1bb31 : 1; // 31 page secure/non-secure attribution
|
|
} reg_flash_sec1bbr3_t;
|
|
|
|
typedef struct {
|
|
uint32_t sec1bb0 : 1; // 0 page secure/non-secure attribution
|
|
uint32_t sec1bb1 : 1; // 1 page secure/non-secure attribution
|
|
uint32_t sec1bb2 : 1; // 2 page secure/non-secure attribution
|
|
uint32_t sec1bb3 : 1; // 3 page secure/non-secure attribution
|
|
uint32_t sec1bb4 : 1; // 4 page secure/non-secure attribution
|
|
uint32_t sec1bb5 : 1; // 5 page secure/non-secure attribution
|
|
uint32_t sec1bb6 : 1; // 6 page secure/non-secure attribution
|
|
uint32_t sec1bb7 : 1; // 7 page secure/non-secure attribution
|
|
uint32_t sec1bb8 : 1; // 8 page secure/non-secure attribution
|
|
uint32_t sec1bb9 : 1; // 9 page secure/non-secure attribution
|
|
uint32_t sec1bb10 : 1; // 10 page secure/non-secure attribution
|
|
uint32_t sec1bb11 : 1; // 11 page secure/non-secure attribution
|
|
uint32_t sec1bb12 : 1; // 12 page secure/non-secure attribution
|
|
uint32_t sec1bb13 : 1; // 13 page secure/non-secure attribution
|
|
uint32_t sec1bb14 : 1; // 14 page secure/non-secure attribution
|
|
uint32_t sec1bb15 : 1; // 15 page secure/non-secure attribution
|
|
uint32_t sec1bb16 : 1; // 16 page secure/non-secure attribution
|
|
uint32_t sec1bb17 : 1; // 17 page secure/non-secure attribution
|
|
uint32_t sec1bb18 : 1; // 18 page secure/non-secure attribution
|
|
uint32_t sec1bb19 : 1; // 19 page secure/non-secure attribution
|
|
uint32_t sec1bb20 : 1; // 20 page secure/non-secure attribution
|
|
uint32_t sec1bb21 : 1; // 21 page secure/non-secure attribution
|
|
uint32_t sec1bb22 : 1; // 22 page secure/non-secure attribution
|
|
uint32_t sec1bb23 : 1; // 23 page secure/non-secure attribution
|
|
uint32_t sec1bb24 : 1; // 24 page secure/non-secure attribution
|
|
uint32_t sec1bb25 : 1; // 25 page secure/non-secure attribution
|
|
uint32_t sec1bb26 : 1; // 26 page secure/non-secure attribution
|
|
uint32_t sec1bb27 : 1; // 27 page secure/non-secure attribution
|
|
uint32_t sec1bb28 : 1; // 28 page secure/non-secure attribution
|
|
uint32_t sec1bb29 : 1; // 29 page secure/non-secure attribution
|
|
uint32_t sec1bb30 : 1; // 30 page secure/non-secure attribution
|
|
uint32_t sec1bb31 : 1; // 31 page secure/non-secure attribution
|
|
} reg_flash_sec1bbr4_t;
|
|
|
|
typedef struct {
|
|
uint32_t sec2bb0 : 1; // 0 page secure/non-secure attribution
|
|
uint32_t sec2bb1 : 1; // 1 page secure/non-secure attribution
|
|
uint32_t sec2bb2 : 1; // 2 page secure/non-secure attribution
|
|
uint32_t sec2bb3 : 1; // 3 page secure/non-secure attribution
|
|
uint32_t sec2bb4 : 1; // 4 page secure/non-secure attribution
|
|
uint32_t sec2bb5 : 1; // 5 page secure/non-secure attribution
|
|
uint32_t sec2bb6 : 1; // 6 page secure/non-secure attribution
|
|
uint32_t sec2bb7 : 1; // 7 page secure/non-secure attribution
|
|
uint32_t sec2bb8 : 1; // 8 page secure/non-secure attribution
|
|
uint32_t sec2bb9 : 1; // 9 page secure/non-secure attribution
|
|
uint32_t sec2bb10 : 1; // 10 page secure/non-secure attribution
|
|
uint32_t sec2bb11 : 1; // 11 page secure/non-secure attribution
|
|
uint32_t sec2bb12 : 1; // 12 page secure/non-secure attribution
|
|
uint32_t sec2bb13 : 1; // 13 page secure/non-secure attribution
|
|
uint32_t sec2bb14 : 1; // 14 page secure/non-secure attribution
|
|
uint32_t sec2bb15 : 1; // 15 page secure/non-secure attribution
|
|
uint32_t sec2bb16 : 1; // 16 page secure/non-secure attribution
|
|
uint32_t sec2bb17 : 1; // 17 page secure/non-secure attribution
|
|
uint32_t sec2bb18 : 1; // 18 page secure/non-secure attribution
|
|
uint32_t sec2bb19 : 1; // 19 page secure/non-secure attribution
|
|
uint32_t sec2bb20 : 1; // 20 page secure/non-secure attribution
|
|
uint32_t sec2bb21 : 1; // 21 page secure/non-secure attribution
|
|
uint32_t sec2bb22 : 1; // 22 page secure/non-secure attribution
|
|
uint32_t sec2bb23 : 1; // 23 page secure/non-secure attribution
|
|
uint32_t sec2bb24 : 1; // 24 page secure/non-secure attribution
|
|
uint32_t sec2bb25 : 1; // 25 page secure/non-secure attribution
|
|
uint32_t sec2bb26 : 1; // 26 page secure/non-secure attribution
|
|
uint32_t sec2bb27 : 1; // 27 page secure/non-secure attribution
|
|
uint32_t sec2bb28 : 1; // 28 page secure/non-secure attribution
|
|
uint32_t sec2bb29 : 1; // 29 page secure/non-secure attribution
|
|
uint32_t sec2bb30 : 1; // 30 page secure/non-secure attribution
|
|
uint32_t sec2bb31 : 1; // 31 page secure/non-secure attribution
|
|
} reg_flash_sec2bbr1_t;
|
|
|
|
typedef struct {
|
|
uint32_t sec2bb0 : 1; // 0 page secure/non-secure attribution
|
|
uint32_t sec2bb1 : 1; // 1 page secure/non-secure attribution
|
|
uint32_t sec2bb2 : 1; // 2 page secure/non-secure attribution
|
|
uint32_t sec2bb3 : 1; // 3 page secure/non-secure attribution
|
|
uint32_t sec2bb4 : 1; // 4 page secure/non-secure attribution
|
|
uint32_t sec2bb5 : 1; // 5 page secure/non-secure attribution
|
|
uint32_t sec2bb6 : 1; // 6 page secure/non-secure attribution
|
|
uint32_t sec2bb7 : 1; // 7 page secure/non-secure attribution
|
|
uint32_t sec2bb8 : 1; // 8 page secure/non-secure attribution
|
|
uint32_t sec2bb9 : 1; // 9 page secure/non-secure attribution
|
|
uint32_t sec2bb10 : 1; // 10 page secure/non-secure attribution
|
|
uint32_t sec2bb11 : 1; // 11 page secure/non-secure attribution
|
|
uint32_t sec2bb12 : 1; // 12 page secure/non-secure attribution
|
|
uint32_t sec2bb13 : 1; // 13 page secure/non-secure attribution
|
|
uint32_t sec2bb14 : 1; // 14 page secure/non-secure attribution
|
|
uint32_t sec2bb15 : 1; // 15 page secure/non-secure attribution
|
|
uint32_t sec2bb16 : 1; // 16 page secure/non-secure attribution
|
|
uint32_t sec2bb17 : 1; // 17 page secure/non-secure attribution
|
|
uint32_t sec2bb18 : 1; // 18 page secure/non-secure attribution
|
|
uint32_t sec2bb19 : 1; // 19 page secure/non-secure attribution
|
|
uint32_t sec2bb20 : 1; // 20 page secure/non-secure attribution
|
|
uint32_t sec2bb21 : 1; // 21 page secure/non-secure attribution
|
|
uint32_t sec2bb22 : 1; // 22 page secure/non-secure attribution
|
|
uint32_t sec2bb23 : 1; // 23 page secure/non-secure attribution
|
|
uint32_t sec2bb24 : 1; // 24 page secure/non-secure attribution
|
|
uint32_t sec2bb25 : 1; // 25 page secure/non-secure attribution
|
|
uint32_t sec2bb26 : 1; // 26 page secure/non-secure attribution
|
|
uint32_t sec2bb27 : 1; // 27 page secure/non-secure attribution
|
|
uint32_t sec2bb28 : 1; // 28 page secure/non-secure attribution
|
|
uint32_t sec2bb29 : 1; // 29 page secure/non-secure attribution
|
|
uint32_t sec2bb30 : 1; // 30 page secure/non-secure attribution
|
|
uint32_t sec2bb31 : 1; // 31 page secure/non-secure attribution
|
|
} reg_flash_sec2bbr2_t;
|
|
|
|
typedef struct {
|
|
uint32_t sec2bb0 : 1; // 0 page secure/non-secure attribution
|
|
uint32_t sec2bb1 : 1; // 1 page secure/non-secure attribution
|
|
uint32_t sec2bb2 : 1; // 2 page secure/non-secure attribution
|
|
uint32_t sec2bb3 : 1; // 3 page secure/non-secure attribution
|
|
uint32_t sec2bb4 : 1; // 4 page secure/non-secure attribution
|
|
uint32_t sec2bb5 : 1; // 5 page secure/non-secure attribution
|
|
uint32_t sec2bb6 : 1; // 6 page secure/non-secure attribution
|
|
uint32_t sec2bb7 : 1; // 7 page secure/non-secure attribution
|
|
uint32_t sec2bb8 : 1; // 8 page secure/non-secure attribution
|
|
uint32_t sec2bb9 : 1; // 9 page secure/non-secure attribution
|
|
uint32_t sec2bb10 : 1; // 10 page secure/non-secure attribution
|
|
uint32_t sec2bb11 : 1; // 11 page secure/non-secure attribution
|
|
uint32_t sec2bb12 : 1; // 12 page secure/non-secure attribution
|
|
uint32_t sec2bb13 : 1; // 13 page secure/non-secure attribution
|
|
uint32_t sec2bb14 : 1; // 14 page secure/non-secure attribution
|
|
uint32_t sec2bb15 : 1; // 15 page secure/non-secure attribution
|
|
uint32_t sec2bb16 : 1; // 16 page secure/non-secure attribution
|
|
uint32_t sec2bb17 : 1; // 17 page secure/non-secure attribution
|
|
uint32_t sec2bb18 : 1; // 18 page secure/non-secure attribution
|
|
uint32_t sec2bb19 : 1; // 19 page secure/non-secure attribution
|
|
uint32_t sec2bb20 : 1; // 20 page secure/non-secure attribution
|
|
uint32_t sec2bb21 : 1; // 21 page secure/non-secure attribution
|
|
uint32_t sec2bb22 : 1; // 22 page secure/non-secure attribution
|
|
uint32_t sec2bb23 : 1; // 23 page secure/non-secure attribution
|
|
uint32_t sec2bb24 : 1; // 24 page secure/non-secure attribution
|
|
uint32_t sec2bb25 : 1; // 25 page secure/non-secure attribution
|
|
uint32_t sec2bb26 : 1; // 26 page secure/non-secure attribution
|
|
uint32_t sec2bb27 : 1; // 27 page secure/non-secure attribution
|
|
uint32_t sec2bb28 : 1; // 28 page secure/non-secure attribution
|
|
uint32_t sec2bb29 : 1; // 29 page secure/non-secure attribution
|
|
uint32_t sec2bb30 : 1; // 30 page secure/non-secure attribution
|
|
uint32_t sec2bb31 : 1; // 31 page secure/non-secure attribution
|
|
} reg_flash_sec2bbr3_t;
|
|
|
|
typedef struct {
|
|
uint32_t sec2bb0 : 1; // 0 page secure/non-secure attribution
|
|
uint32_t sec2bb1 : 1; // 1 page secure/non-secure attribution
|
|
uint32_t sec2bb2 : 1; // 2 page secure/non-secure attribution
|
|
uint32_t sec2bb3 : 1; // 3 page secure/non-secure attribution
|
|
uint32_t sec2bb4 : 1; // 4 page secure/non-secure attribution
|
|
uint32_t sec2bb5 : 1; // 5 page secure/non-secure attribution
|
|
uint32_t sec2bb6 : 1; // 6 page secure/non-secure attribution
|
|
uint32_t sec2bb7 : 1; // 7 page secure/non-secure attribution
|
|
uint32_t sec2bb8 : 1; // 8 page secure/non-secure attribution
|
|
uint32_t sec2bb9 : 1; // 9 page secure/non-secure attribution
|
|
uint32_t sec2bb10 : 1; // 10 page secure/non-secure attribution
|
|
uint32_t sec2bb11 : 1; // 11 page secure/non-secure attribution
|
|
uint32_t sec2bb12 : 1; // 12 page secure/non-secure attribution
|
|
uint32_t sec2bb13 : 1; // 13 page secure/non-secure attribution
|
|
uint32_t sec2bb14 : 1; // 14 page secure/non-secure attribution
|
|
uint32_t sec2bb15 : 1; // 15 page secure/non-secure attribution
|
|
uint32_t sec2bb16 : 1; // 16 page secure/non-secure attribution
|
|
uint32_t sec2bb17 : 1; // 17 page secure/non-secure attribution
|
|
uint32_t sec2bb18 : 1; // 18 page secure/non-secure attribution
|
|
uint32_t sec2bb19 : 1; // 19 page secure/non-secure attribution
|
|
uint32_t sec2bb20 : 1; // 20 page secure/non-secure attribution
|
|
uint32_t sec2bb21 : 1; // 21 page secure/non-secure attribution
|
|
uint32_t sec2bb22 : 1; // 22 page secure/non-secure attribution
|
|
uint32_t sec2bb23 : 1; // 23 page secure/non-secure attribution
|
|
uint32_t sec2bb24 : 1; // 24 page secure/non-secure attribution
|
|
uint32_t sec2bb25 : 1; // 25 page secure/non-secure attribution
|
|
uint32_t sec2bb26 : 1; // 26 page secure/non-secure attribution
|
|
uint32_t sec2bb27 : 1; // 27 page secure/non-secure attribution
|
|
uint32_t sec2bb28 : 1; // 28 page secure/non-secure attribution
|
|
uint32_t sec2bb29 : 1; // 29 page secure/non-secure attribution
|
|
uint32_t sec2bb30 : 1; // 30 page secure/non-secure attribution
|
|
uint32_t sec2bb31 : 1; // 31 page secure/non-secure attribution
|
|
} reg_flash_sec2bbr4_t;
|
|
|
|
typedef struct {
|
|
uint32_t hdp1_accdis: 1; // 0 HDP1 area access disable When set, this bit is only cleared by a system reset.
|
|
uint32_t hdp2_accdis: 1; // 1 HDP2 area access disable When set, this bit is only cleared by a system reset.
|
|
uint32_t reserve0 : 30; // 2 Reserve
|
|
} reg_flash_sechdpcr_t;
|
|
|
|
typedef struct {
|
|
uint32_t spriv : 1; // 0 Privileged protection for secure registers This bit can be accessed only when TrustZone is enabled (TZEN = 1). This bit can be read by both privileged or unprivileged, secure and non-secure access. The SPRIV bit can be written only by a secure privileged access. A non-secure write access on SPRIV bit is ignored. A secure unprivileged write access on SPRIV bit is ignored.
|
|
uint32_t nspriv : 1; // 1 Privileged protection for non-secure registers This bit can be read by both privileged or unprivileged, secure and non-secure access. The NSPRIV bit can be written by a secure or non-secure privileged access. A secure or non-secure unprivileged write access on NSPRIV bit is ignored.
|
|
uint32_t reserve0 : 30; // 2 Reserve
|
|
} reg_flash_privcfgr_t;
|
|
|
|
typedef struct {
|
|
uint32_t priv1bb0 : 1; // 0 page privileged/unprivileged attribution
|
|
uint32_t priv1bb1 : 1; // 1 page privileged/unprivileged attribution
|
|
uint32_t priv1bb2 : 1; // 2 page privileged/unprivileged attribution
|
|
uint32_t priv1bb3 : 1; // 3 page privileged/unprivileged attribution
|
|
uint32_t priv1bb4 : 1; // 4 page privileged/unprivileged attribution
|
|
uint32_t priv1bb5 : 1; // 5 page privileged/unprivileged attribution
|
|
uint32_t priv1bb6 : 1; // 6 page privileged/unprivileged attribution
|
|
uint32_t priv1bb7 : 1; // 7 page privileged/unprivileged attribution
|
|
uint32_t priv1bb8 : 1; // 8 page privileged/unprivileged attribution
|
|
uint32_t priv1bb9 : 1; // 9 page privileged/unprivileged attribution
|
|
uint32_t priv1bb10 : 1; // 10 page privileged/unprivileged attribution
|
|
uint32_t priv1bb11 : 1; // 11 page privileged/unprivileged attribution
|
|
uint32_t priv1bb12 : 1; // 12 page privileged/unprivileged attribution
|
|
uint32_t priv1bb13 : 1; // 13 page privileged/unprivileged attribution
|
|
uint32_t priv1bb14 : 1; // 14 page privileged/unprivileged attribution
|
|
uint32_t priv1bb15 : 1; // 15 page privileged/unprivileged attribution
|
|
uint32_t priv1bb16 : 1; // 16 page privileged/unprivileged attribution
|
|
uint32_t priv1bb17 : 1; // 17 page privileged/unprivileged attribution
|
|
uint32_t priv1bb18 : 1; // 18 page privileged/unprivileged attribution
|
|
uint32_t priv1bb19 : 1; // 19 page privileged/unprivileged attribution
|
|
uint32_t priv1bb20 : 1; // 20 page privileged/unprivileged attribution
|
|
uint32_t priv1bb21 : 1; // 21 page privileged/unprivileged attribution
|
|
uint32_t priv1bb22 : 1; // 22 page privileged/unprivileged attribution
|
|
uint32_t priv1bb23 : 1; // 23 page privileged/unprivileged attribution
|
|
uint32_t priv1bb24 : 1; // 24 page privileged/unprivileged attribution
|
|
uint32_t priv1bb25 : 1; // 25 page privileged/unprivileged attribution
|
|
uint32_t priv1bb26 : 1; // 26 page privileged/unprivileged attribution
|
|
uint32_t priv1bb27 : 1; // 27 page privileged/unprivileged attribution
|
|
uint32_t priv1bb28 : 1; // 28 page privileged/unprivileged attribution
|
|
uint32_t priv1bb29 : 1; // 29 page privileged/unprivileged attribution
|
|
uint32_t priv1bb30 : 1; // 30 page privileged/unprivileged attribution
|
|
uint32_t priv1bb31 : 1; // 31 page privileged/unprivileged attribution
|
|
} reg_flash_priv1bbr1_t;
|
|
|
|
typedef struct {
|
|
uint32_t priv1bb0 : 1; // 0 page privileged/unprivileged attribution
|
|
uint32_t priv1bb1 : 1; // 1 page privileged/unprivileged attribution
|
|
uint32_t priv1bb2 : 1; // 2 page privileged/unprivileged attribution
|
|
uint32_t priv1bb3 : 1; // 3 page privileged/unprivileged attribution
|
|
uint32_t priv1bb4 : 1; // 4 page privileged/unprivileged attribution
|
|
uint32_t priv1bb5 : 1; // 5 page privileged/unprivileged attribution
|
|
uint32_t priv1bb6 : 1; // 6 page privileged/unprivileged attribution
|
|
uint32_t priv1bb7 : 1; // 7 page privileged/unprivileged attribution
|
|
uint32_t priv1bb8 : 1; // 8 page privileged/unprivileged attribution
|
|
uint32_t priv1bb9 : 1; // 9 page privileged/unprivileged attribution
|
|
uint32_t priv1bb10 : 1; // 10 page privileged/unprivileged attribution
|
|
uint32_t priv1bb11 : 1; // 11 page privileged/unprivileged attribution
|
|
uint32_t priv1bb12 : 1; // 12 page privileged/unprivileged attribution
|
|
uint32_t priv1bb13 : 1; // 13 page privileged/unprivileged attribution
|
|
uint32_t priv1bb14 : 1; // 14 page privileged/unprivileged attribution
|
|
uint32_t priv1bb15 : 1; // 15 page privileged/unprivileged attribution
|
|
uint32_t priv1bb16 : 1; // 16 page privileged/unprivileged attribution
|
|
uint32_t priv1bb17 : 1; // 17 page privileged/unprivileged attribution
|
|
uint32_t priv1bb18 : 1; // 18 page privileged/unprivileged attribution
|
|
uint32_t priv1bb19 : 1; // 19 page privileged/unprivileged attribution
|
|
uint32_t priv1bb20 : 1; // 20 page privileged/unprivileged attribution
|
|
uint32_t priv1bb21 : 1; // 21 page privileged/unprivileged attribution
|
|
uint32_t priv1bb22 : 1; // 22 page privileged/unprivileged attribution
|
|
uint32_t priv1bb23 : 1; // 23 page privileged/unprivileged attribution
|
|
uint32_t priv1bb24 : 1; // 24 page privileged/unprivileged attribution
|
|
uint32_t priv1bb25 : 1; // 25 page privileged/unprivileged attribution
|
|
uint32_t priv1bb26 : 1; // 26 page privileged/unprivileged attribution
|
|
uint32_t priv1bb27 : 1; // 27 page privileged/unprivileged attribution
|
|
uint32_t priv1bb28 : 1; // 28 page privileged/unprivileged attribution
|
|
uint32_t priv1bb29 : 1; // 29 page privileged/unprivileged attribution
|
|
uint32_t priv1bb30 : 1; // 30 page privileged/unprivileged attribution
|
|
uint32_t priv1bb31 : 1; // 31 page privileged/unprivileged attribution
|
|
} reg_flash_priv1bbr2_t;
|
|
|
|
typedef struct {
|
|
uint32_t priv1bb0 : 1; // 0 page privileged/unprivileged attribution
|
|
uint32_t priv1bb1 : 1; // 1 page privileged/unprivileged attribution
|
|
uint32_t priv1bb2 : 1; // 2 page privileged/unprivileged attribution
|
|
uint32_t priv1bb3 : 1; // 3 page privileged/unprivileged attribution
|
|
uint32_t priv1bb4 : 1; // 4 page privileged/unprivileged attribution
|
|
uint32_t priv1bb5 : 1; // 5 page privileged/unprivileged attribution
|
|
uint32_t priv1bb6 : 1; // 6 page privileged/unprivileged attribution
|
|
uint32_t priv1bb7 : 1; // 7 page privileged/unprivileged attribution
|
|
uint32_t priv1bb8 : 1; // 8 page privileged/unprivileged attribution
|
|
uint32_t priv1bb9 : 1; // 9 page privileged/unprivileged attribution
|
|
uint32_t priv1bb10 : 1; // 10 page privileged/unprivileged attribution
|
|
uint32_t priv1bb11 : 1; // 11 page privileged/unprivileged attribution
|
|
uint32_t priv1bb12 : 1; // 12 page privileged/unprivileged attribution
|
|
uint32_t priv1bb13 : 1; // 13 page privileged/unprivileged attribution
|
|
uint32_t priv1bb14 : 1; // 14 page privileged/unprivileged attribution
|
|
uint32_t priv1bb15 : 1; // 15 page privileged/unprivileged attribution
|
|
uint32_t priv1bb16 : 1; // 16 page privileged/unprivileged attribution
|
|
uint32_t priv1bb17 : 1; // 17 page privileged/unprivileged attribution
|
|
uint32_t priv1bb18 : 1; // 18 page privileged/unprivileged attribution
|
|
uint32_t priv1bb19 : 1; // 19 page privileged/unprivileged attribution
|
|
uint32_t priv1bb20 : 1; // 20 page privileged/unprivileged attribution
|
|
uint32_t priv1bb21 : 1; // 21 page privileged/unprivileged attribution
|
|
uint32_t priv1bb22 : 1; // 22 page privileged/unprivileged attribution
|
|
uint32_t priv1bb23 : 1; // 23 page privileged/unprivileged attribution
|
|
uint32_t priv1bb24 : 1; // 24 page privileged/unprivileged attribution
|
|
uint32_t priv1bb25 : 1; // 25 page privileged/unprivileged attribution
|
|
uint32_t priv1bb26 : 1; // 26 page privileged/unprivileged attribution
|
|
uint32_t priv1bb27 : 1; // 27 page privileged/unprivileged attribution
|
|
uint32_t priv1bb28 : 1; // 28 page privileged/unprivileged attribution
|
|
uint32_t priv1bb29 : 1; // 29 page privileged/unprivileged attribution
|
|
uint32_t priv1bb30 : 1; // 30 page privileged/unprivileged attribution
|
|
uint32_t priv1bb31 : 1; // 31 page privileged/unprivileged attribution
|
|
} reg_flash_priv1bbr3_t;
|
|
|
|
typedef struct {
|
|
uint32_t priv1bb0 : 1; // 0 page privileged/unprivileged attribution
|
|
uint32_t priv1bb1 : 1; // 1 page privileged/unprivileged attribution
|
|
uint32_t priv1bb2 : 1; // 2 page privileged/unprivileged attribution
|
|
uint32_t priv1bb3 : 1; // 3 page privileged/unprivileged attribution
|
|
uint32_t priv1bb4 : 1; // 4 page privileged/unprivileged attribution
|
|
uint32_t priv1bb5 : 1; // 5 page privileged/unprivileged attribution
|
|
uint32_t priv1bb6 : 1; // 6 page privileged/unprivileged attribution
|
|
uint32_t priv1bb7 : 1; // 7 page privileged/unprivileged attribution
|
|
uint32_t priv1bb8 : 1; // 8 page privileged/unprivileged attribution
|
|
uint32_t priv1bb9 : 1; // 9 page privileged/unprivileged attribution
|
|
uint32_t priv1bb10 : 1; // 10 page privileged/unprivileged attribution
|
|
uint32_t priv1bb11 : 1; // 11 page privileged/unprivileged attribution
|
|
uint32_t priv1bb12 : 1; // 12 page privileged/unprivileged attribution
|
|
uint32_t priv1bb13 : 1; // 13 page privileged/unprivileged attribution
|
|
uint32_t priv1bb14 : 1; // 14 page privileged/unprivileged attribution
|
|
uint32_t priv1bb15 : 1; // 15 page privileged/unprivileged attribution
|
|
uint32_t priv1bb16 : 1; // 16 page privileged/unprivileged attribution
|
|
uint32_t priv1bb17 : 1; // 17 page privileged/unprivileged attribution
|
|
uint32_t priv1bb18 : 1; // 18 page privileged/unprivileged attribution
|
|
uint32_t priv1bb19 : 1; // 19 page privileged/unprivileged attribution
|
|
uint32_t priv1bb20 : 1; // 20 page privileged/unprivileged attribution
|
|
uint32_t priv1bb21 : 1; // 21 page privileged/unprivileged attribution
|
|
uint32_t priv1bb22 : 1; // 22 page privileged/unprivileged attribution
|
|
uint32_t priv1bb23 : 1; // 23 page privileged/unprivileged attribution
|
|
uint32_t priv1bb24 : 1; // 24 page privileged/unprivileged attribution
|
|
uint32_t priv1bb25 : 1; // 25 page privileged/unprivileged attribution
|
|
uint32_t priv1bb26 : 1; // 26 page privileged/unprivileged attribution
|
|
uint32_t priv1bb27 : 1; // 27 page privileged/unprivileged attribution
|
|
uint32_t priv1bb28 : 1; // 28 page privileged/unprivileged attribution
|
|
uint32_t priv1bb29 : 1; // 29 page privileged/unprivileged attribution
|
|
uint32_t priv1bb30 : 1; // 30 page privileged/unprivileged attribution
|
|
uint32_t priv1bb31 : 1; // 31 page privileged/unprivileged attribution
|
|
} reg_flash_priv1bbr4_t;
|
|
|
|
typedef struct {
|
|
uint32_t priv2bb0 : 1; // 0 page privileged/unprivileged attribution
|
|
uint32_t priv2bb1 : 1; // 1 page privileged/unprivileged attribution
|
|
uint32_t priv2bb2 : 1; // 2 page privileged/unprivileged attribution
|
|
uint32_t priv2bb3 : 1; // 3 page privileged/unprivileged attribution
|
|
uint32_t priv2bb4 : 1; // 4 page privileged/unprivileged attribution
|
|
uint32_t priv2bb5 : 1; // 5 page privileged/unprivileged attribution
|
|
uint32_t priv2bb6 : 1; // 6 page privileged/unprivileged attribution
|
|
uint32_t priv2bb7 : 1; // 7 page privileged/unprivileged attribution
|
|
uint32_t priv2bb8 : 1; // 8 page privileged/unprivileged attribution
|
|
uint32_t priv2bb9 : 1; // 9 page privileged/unprivileged attribution
|
|
uint32_t priv2bb10 : 1; // 10 page privileged/unprivileged attribution
|
|
uint32_t priv2bb11 : 1; // 11 page privileged/unprivileged attribution
|
|
uint32_t priv2bb12 : 1; // 12 page privileged/unprivileged attribution
|
|
uint32_t priv2bb13 : 1; // 13 page privileged/unprivileged attribution
|
|
uint32_t priv2bb14 : 1; // 14 page privileged/unprivileged attribution
|
|
uint32_t priv2bb15 : 1; // 15 page privileged/unprivileged attribution
|
|
uint32_t priv2bb16 : 1; // 16 page privileged/unprivileged attribution
|
|
uint32_t priv2bb17 : 1; // 17 page privileged/unprivileged attribution
|
|
uint32_t priv2bb18 : 1; // 18 page privileged/unprivileged attribution
|
|
uint32_t priv2bb19 : 1; // 19 page privileged/unprivileged attribution
|
|
uint32_t priv2bb20 : 1; // 20 page privileged/unprivileged attribution
|
|
uint32_t priv2bb21 : 1; // 21 page privileged/unprivileged attribution
|
|
uint32_t priv2bb22 : 1; // 22 page privileged/unprivileged attribution
|
|
uint32_t priv2bb23 : 1; // 23 page privileged/unprivileged attribution
|
|
uint32_t priv2bb24 : 1; // 24 page privileged/unprivileged attribution
|
|
uint32_t priv2bb25 : 1; // 25 page privileged/unprivileged attribution
|
|
uint32_t priv2bb26 : 1; // 26 page privileged/unprivileged attribution
|
|
uint32_t priv2bb27 : 1; // 27 page privileged/unprivileged attribution
|
|
uint32_t priv2bb28 : 1; // 28 page privileged/unprivileged attribution
|
|
uint32_t priv2bb29 : 1; // 29 page privileged/unprivileged attribution
|
|
uint32_t priv2bb30 : 1; // 30 page privileged/unprivileged attribution
|
|
uint32_t priv2bb31 : 1; // 31 page privileged/unprivileged attribution
|
|
} reg_flash_priv2bbr1_t;
|
|
|
|
typedef struct {
|
|
uint32_t priv2bb0 : 1; // 0 page privileged/unprivileged attribution
|
|
uint32_t priv2bb1 : 1; // 1 page privileged/unprivileged attribution
|
|
uint32_t priv2bb2 : 1; // 2 page privileged/unprivileged attribution
|
|
uint32_t priv2bb3 : 1; // 3 page privileged/unprivileged attribution
|
|
uint32_t priv2bb4 : 1; // 4 page privileged/unprivileged attribution
|
|
uint32_t priv2bb5 : 1; // 5 page privileged/unprivileged attribution
|
|
uint32_t priv2bb6 : 1; // 6 page privileged/unprivileged attribution
|
|
uint32_t priv2bb7 : 1; // 7 page privileged/unprivileged attribution
|
|
uint32_t priv2bb8 : 1; // 8 page privileged/unprivileged attribution
|
|
uint32_t priv2bb9 : 1; // 9 page privileged/unprivileged attribution
|
|
uint32_t priv2bb10 : 1; // 10 page privileged/unprivileged attribution
|
|
uint32_t priv2bb11 : 1; // 11 page privileged/unprivileged attribution
|
|
uint32_t priv2bb12 : 1; // 12 page privileged/unprivileged attribution
|
|
uint32_t priv2bb13 : 1; // 13 page privileged/unprivileged attribution
|
|
uint32_t priv2bb14 : 1; // 14 page privileged/unprivileged attribution
|
|
uint32_t priv2bb15 : 1; // 15 page privileged/unprivileged attribution
|
|
uint32_t priv2bb16 : 1; // 16 page privileged/unprivileged attribution
|
|
uint32_t priv2bb17 : 1; // 17 page privileged/unprivileged attribution
|
|
uint32_t priv2bb18 : 1; // 18 page privileged/unprivileged attribution
|
|
uint32_t priv2bb19 : 1; // 19 page privileged/unprivileged attribution
|
|
uint32_t priv2bb20 : 1; // 20 page privileged/unprivileged attribution
|
|
uint32_t priv2bb21 : 1; // 21 page privileged/unprivileged attribution
|
|
uint32_t priv2bb22 : 1; // 22 page privileged/unprivileged attribution
|
|
uint32_t priv2bb23 : 1; // 23 page privileged/unprivileged attribution
|
|
uint32_t priv2bb24 : 1; // 24 page privileged/unprivileged attribution
|
|
uint32_t priv2bb25 : 1; // 25 page privileged/unprivileged attribution
|
|
uint32_t priv2bb26 : 1; // 26 page privileged/unprivileged attribution
|
|
uint32_t priv2bb27 : 1; // 27 page privileged/unprivileged attribution
|
|
uint32_t priv2bb28 : 1; // 28 page privileged/unprivileged attribution
|
|
uint32_t priv2bb29 : 1; // 29 page privileged/unprivileged attribution
|
|
uint32_t priv2bb30 : 1; // 30 page privileged/unprivileged attribution
|
|
uint32_t priv2bb31 : 1; // 31 page privileged/unprivileged attribution
|
|
} reg_flash_priv2bbr2_t;
|
|
|
|
typedef struct {
|
|
uint32_t priv2bb0 : 1; // 0 page privileged/unprivileged attribution
|
|
uint32_t priv2bb1 : 1; // 1 page privileged/unprivileged attribution
|
|
uint32_t priv2bb2 : 1; // 2 page privileged/unprivileged attribution
|
|
uint32_t priv2bb3 : 1; // 3 page privileged/unprivileged attribution
|
|
uint32_t priv2bb4 : 1; // 4 page privileged/unprivileged attribution
|
|
uint32_t priv2bb5 : 1; // 5 page privileged/unprivileged attribution
|
|
uint32_t priv2bb6 : 1; // 6 page privileged/unprivileged attribution
|
|
uint32_t priv2bb7 : 1; // 7 page privileged/unprivileged attribution
|
|
uint32_t priv2bb8 : 1; // 8 page privileged/unprivileged attribution
|
|
uint32_t priv2bb9 : 1; // 9 page privileged/unprivileged attribution
|
|
uint32_t priv2bb10 : 1; // 10 page privileged/unprivileged attribution
|
|
uint32_t priv2bb11 : 1; // 11 page privileged/unprivileged attribution
|
|
uint32_t priv2bb12 : 1; // 12 page privileged/unprivileged attribution
|
|
uint32_t priv2bb13 : 1; // 13 page privileged/unprivileged attribution
|
|
uint32_t priv2bb14 : 1; // 14 page privileged/unprivileged attribution
|
|
uint32_t priv2bb15 : 1; // 15 page privileged/unprivileged attribution
|
|
uint32_t priv2bb16 : 1; // 16 page privileged/unprivileged attribution
|
|
uint32_t priv2bb17 : 1; // 17 page privileged/unprivileged attribution
|
|
uint32_t priv2bb18 : 1; // 18 page privileged/unprivileged attribution
|
|
uint32_t priv2bb19 : 1; // 19 page privileged/unprivileged attribution
|
|
uint32_t priv2bb20 : 1; // 20 page privileged/unprivileged attribution
|
|
uint32_t priv2bb21 : 1; // 21 page privileged/unprivileged attribution
|
|
uint32_t priv2bb22 : 1; // 22 page privileged/unprivileged attribution
|
|
uint32_t priv2bb23 : 1; // 23 page privileged/unprivileged attribution
|
|
uint32_t priv2bb24 : 1; // 24 page privileged/unprivileged attribution
|
|
uint32_t priv2bb25 : 1; // 25 page privileged/unprivileged attribution
|
|
uint32_t priv2bb26 : 1; // 26 page privileged/unprivileged attribution
|
|
uint32_t priv2bb27 : 1; // 27 page privileged/unprivileged attribution
|
|
uint32_t priv2bb28 : 1; // 28 page privileged/unprivileged attribution
|
|
uint32_t priv2bb29 : 1; // 29 page privileged/unprivileged attribution
|
|
uint32_t priv2bb30 : 1; // 30 page privileged/unprivileged attribution
|
|
uint32_t priv2bb31 : 1; // 31 page privileged/unprivileged attribution
|
|
} reg_flash_priv2bbr3_t;
|
|
|
|
typedef struct {
|
|
uint32_t priv2bb0 : 1; // 0 page privileged/unprivileged attribution
|
|
uint32_t priv2bb1 : 1; // 1 page privileged/unprivileged attribution
|
|
uint32_t priv2bb2 : 1; // 2 page privileged/unprivileged attribution
|
|
uint32_t priv2bb3 : 1; // 3 page privileged/unprivileged attribution
|
|
uint32_t priv2bb4 : 1; // 4 page privileged/unprivileged attribution
|
|
uint32_t priv2bb5 : 1; // 5 page privileged/unprivileged attribution
|
|
uint32_t priv2bb6 : 1; // 6 page privileged/unprivileged attribution
|
|
uint32_t priv2bb7 : 1; // 7 page privileged/unprivileged attribution
|
|
uint32_t priv2bb8 : 1; // 8 page privileged/unprivileged attribution
|
|
uint32_t priv2bb9 : 1; // 9 page privileged/unprivileged attribution
|
|
uint32_t priv2bb10 : 1; // 10 page privileged/unprivileged attribution
|
|
uint32_t priv2bb11 : 1; // 11 page privileged/unprivileged attribution
|
|
uint32_t priv2bb12 : 1; // 12 page privileged/unprivileged attribution
|
|
uint32_t priv2bb13 : 1; // 13 page privileged/unprivileged attribution
|
|
uint32_t priv2bb14 : 1; // 14 page privileged/unprivileged attribution
|
|
uint32_t priv2bb15 : 1; // 15 page privileged/unprivileged attribution
|
|
uint32_t priv2bb16 : 1; // 16 page privileged/unprivileged attribution
|
|
uint32_t priv2bb17 : 1; // 17 page privileged/unprivileged attribution
|
|
uint32_t priv2bb18 : 1; // 18 page privileged/unprivileged attribution
|
|
uint32_t priv2bb19 : 1; // 19 page privileged/unprivileged attribution
|
|
uint32_t priv2bb20 : 1; // 20 page privileged/unprivileged attribution
|
|
uint32_t priv2bb21 : 1; // 21 page privileged/unprivileged attribution
|
|
uint32_t priv2bb22 : 1; // 22 page privileged/unprivileged attribution
|
|
uint32_t priv2bb23 : 1; // 23 page privileged/unprivileged attribution
|
|
uint32_t priv2bb24 : 1; // 24 page privileged/unprivileged attribution
|
|
uint32_t priv2bb25 : 1; // 25 page privileged/unprivileged attribution
|
|
uint32_t priv2bb26 : 1; // 26 page privileged/unprivileged attribution
|
|
uint32_t priv2bb27 : 1; // 27 page privileged/unprivileged attribution
|
|
uint32_t priv2bb28 : 1; // 28 page privileged/unprivileged attribution
|
|
uint32_t priv2bb29 : 1; // 29 page privileged/unprivileged attribution
|
|
uint32_t priv2bb30 : 1; // 30 page privileged/unprivileged attribution
|
|
uint32_t priv2bb31 : 1; // 31 page privileged/unprivileged attribution
|
|
} reg_flash_priv2bbr4_t;
|
|
|
|
typedef struct {
|
|
volatile reg_flash_acr_t acr;
|
|
volatile uint32_t reserve0[1];
|
|
volatile reg_flash_nskeyr_t nskeyr;
|
|
volatile reg_flash_seckeyr_t seckeyr;
|
|
volatile reg_flash_optkeyr_t optkeyr;
|
|
volatile uint32_t reserve1[1];
|
|
volatile reg_flash_pdkey1r_t pdkey1r;
|
|
volatile reg_flash_pdkey2r_t pdkey2r;
|
|
volatile reg_flash_nssr_t nssr;
|
|
volatile reg_flash_secsr_t secsr;
|
|
volatile reg_flash_nscr_t nscr;
|
|
volatile reg_flash_seccr_t seccr;
|
|
volatile reg_flash_eccr_t eccr;
|
|
volatile reg_flash_opsr_t opsr;
|
|
volatile uint32_t reserve2[2];
|
|
volatile reg_flash_optr_t optr;
|
|
volatile reg_flash_nsbootadd0r_t nsbootadd0r;
|
|
volatile reg_flash_nsbootadd1r_t nsbootadd1r;
|
|
volatile reg_flash_secbootadd0r_t secbootadd0r;
|
|
volatile reg_flash_secwm1r1_t secwm1r1;
|
|
volatile reg_flash_secwm1r2_t secwm1r2;
|
|
volatile reg_flash_wrp1ar_t wrp1ar;
|
|
volatile reg_flash_wrp1br_t wrp1br;
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volatile reg_flash_secwm2r1_t secwm2r1;
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volatile reg_flash_secwm2r2_t secwm2r2;
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volatile reg_flash_wrp2ar_t wrp2ar;
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volatile reg_flash_wrp2br_t wrp2br;
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volatile reg_flash_oem1keyr1_t oem1keyr1;
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volatile reg_flash_oem1keyr2_t oem1keyr2;
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volatile reg_flash_oem2keyr1_t oem2keyr1;
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volatile reg_flash_oem2keyr2_t oem2keyr2;
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volatile reg_flash_sec1bbr1_t sec1bbr1;
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volatile reg_flash_sec1bbr2_t sec1bbr2;
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volatile reg_flash_sec1bbr3_t sec1bbr3;
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volatile reg_flash_sec1bbr4_t sec1bbr4;
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volatile uint32_t reserve3[4];
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volatile reg_flash_sec2bbr1_t sec2bbr1;
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volatile reg_flash_sec2bbr2_t sec2bbr2;
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volatile reg_flash_sec2bbr3_t sec2bbr3;
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volatile reg_flash_sec2bbr4_t sec2bbr4;
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volatile uint32_t reserve4[4];
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volatile reg_flash_sechdpcr_t sechdpcr;
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volatile reg_flash_privcfgr_t privcfgr;
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volatile uint32_t reserve5[2];
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volatile reg_flash_priv1bbr1_t priv1bbr1;
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volatile reg_flash_priv1bbr2_t priv1bbr2;
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volatile reg_flash_priv1bbr3_t priv1bbr3;
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volatile reg_flash_priv1bbr4_t priv1bbr4;
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volatile uint32_t reserve6[4];
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volatile reg_flash_priv2bbr1_t priv2bbr1;
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volatile reg_flash_priv2bbr2_t priv2bbr2;
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volatile reg_flash_priv2bbr3_t priv2bbr3;
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volatile reg_flash_priv2bbr4_t priv2bbr4;
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} reg_flash_t;
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