116 lines
4.7 KiB
C
Executable File
116 lines
4.7 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t capture : 1; // 0 Capture enable
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uint32_t cm : 1; // 1 Capture mode
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uint32_t crop : 1; // 2 Crop feature
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uint32_t jpeg : 1; // 3 JPEG format
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uint32_t ess : 1; // 4 Embedded synchronization select
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uint32_t pckpol : 1; // 5 Pixel clock polarity
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uint32_t hspol : 1; // 6 Horizontal synchronization polarity
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uint32_t vspol : 1; // 7 Vertical synchronization polarity
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uint32_t fcrc : 2; // 8 Frame capture rate control
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uint32_t edm : 2; // 10 Extended data mode
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uint32_t reserve0 : 2; // 12 Reserve
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uint32_t enable : 1; // 14 DCMI enable
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uint32_t reserve1 : 1; // 15 Reserve
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uint32_t bsm : 2; // 16 Byte Select mode
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uint32_t oebs : 1; // 18 Odd/Even Byte Select (Byte Select Start)
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uint32_t lsm : 1; // 19 Line Select mode
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uint32_t oels : 1; // 20 Odd/Even Line Select (Line Select Start)
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uint32_t reserve2 : 11; // 21 Reserve
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} reg_dcmi_cr_t;
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typedef struct {
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uint32_t hsync : 1; // 0 Horizontal synchronization
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uint32_t vsync : 1; // 1 Vertical synchronization
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uint32_t fne : 1; // 2 FIFO not empty
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uint32_t reserve0 : 29; // 3 Reserve
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} reg_dcmi_sr_t;
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typedef struct {
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uint32_t frame_ris : 1; // 0 Capture complete raw interrupt status
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uint32_t ovr_ris : 1; // 1 Overrun raw interrupt status
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uint32_t err_ris : 1; // 2 Synchronization error raw interrupt status
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uint32_t vsync_ris : 1; // 3 DCMI_VSYNC raw interrupt status
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uint32_t line_ris : 1; // 4 Line raw interrupt status
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uint32_t reserve0 : 27; // 5 Reserve
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} reg_dcmi_ris_t;
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typedef struct {
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uint32_t frame_ie : 1; // 0 Capture complete interrupt enable
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uint32_t ovr_ie : 1; // 1 Overrun interrupt enable
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uint32_t err_ie : 1; // 2 Synchronization error interrupt enable
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uint32_t vsync_ie : 1; // 3 DCMI_VSYNC interrupt enable
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uint32_t line_ie : 1; // 4 Line interrupt enable
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uint32_t reserve0 : 27; // 5 Reserve
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} reg_dcmi_ier_t;
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typedef struct {
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uint32_t frame_mis : 1; // 0 Capture complete masked interrupt status
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uint32_t ovr_mis : 1; // 1 Overrun masked interrupt status
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uint32_t err_mis : 1; // 2 Synchronization error masked interrupt status
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uint32_t vsync_mis : 1; // 3 VSYNC masked interrupt status
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uint32_t line_mis : 1; // 4 Line masked interrupt status
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uint32_t reserve0 : 27; // 5 Reserve
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} reg_dcmi_mis_t;
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typedef struct {
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uint32_t frame_isc : 1; // 0 Capture complete interrupt status clear
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uint32_t ovr_isc : 1; // 1 Overrun interrupt status clear
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uint32_t err_isc : 1; // 2 Synchronization error interrupt status clear
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uint32_t vsync_isc : 1; // 3 Vertical Synchronization interrupt status clear
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uint32_t line_isc : 1; // 4 line interrupt status clear
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uint32_t reserve0 : 27; // 5 Reserve
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} reg_dcmi_icr_t;
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typedef struct {
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uint32_t fsc : 8; // 0 Frame start delimiter code
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uint32_t lsc : 8; // 8 Line start delimiter code
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uint32_t lec : 8; // 16 Line end delimiter code
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uint32_t fec : 8; // 24 Frame end delimiter code
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} reg_dcmi_escr_t;
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typedef struct {
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uint32_t fsu : 8; // 0 Frame start delimiter unmask
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uint32_t lsu : 8; // 8 Line start delimiter unmask
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uint32_t leu : 8; // 16 Line end delimiter unmask
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uint32_t feu : 8; // 24 Frame end delimiter unmask
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} reg_dcmi_esur_t;
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typedef struct {
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uint32_t hoffcnt : 14; // 0 Horizontal offset count
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uint32_t reserve0 : 2; // 14 Reserve
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uint32_t vst : 13; // 16 Vertical start line count
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uint32_t reserve1 : 3; // 29 Reserve
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} reg_dcmi_cwstrt_t;
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typedef struct {
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uint32_t capcnt : 14; // 0 Capture count
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uint32_t reserve0 : 2; // 14 Reserve
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uint32_t vline : 14; // 16 Vertical line count
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uint32_t reserve1 : 2; // 30 Reserve
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} reg_dcmi_cwsize_t;
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typedef struct {
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uint32_t byte0 : 8; // 0 Data byte 0
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uint32_t byte1 : 8; // 8 Data byte 1
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uint32_t byte2 : 8; // 16 Data byte 2
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uint32_t byte3 : 8; // 24 Data byte 3
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} reg_dcmi_dr_t;
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typedef struct {
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volatile reg_dcmi_cr_t cr;
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volatile reg_dcmi_sr_t sr;
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volatile reg_dcmi_ris_t ris;
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volatile reg_dcmi_ier_t ier;
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volatile reg_dcmi_mis_t mis;
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volatile reg_dcmi_icr_t icr;
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volatile reg_dcmi_escr_t escr;
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volatile reg_dcmi_esur_t esur;
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volatile reg_dcmi_cwstrt_t cwstrt;
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volatile reg_dcmi_cwsize_t cwsize;
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volatile reg_dcmi_dr_t dr;
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} reg_dcmi_t;
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