69 lines
3.3 KiB
C
Executable File
69 lines
3.3 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t reserve0 : 5; // 0 Reserve
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uint32_t ckpol : 1; // 5 Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN.
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uint32_t depol : 1; // 6 Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface.
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uint32_t reserve1 : 1; // 7 Reserve
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uint32_t rdypol : 1; // 8 Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface.
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uint32_t reserve2 : 1; // 9 Reserve
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uint32_t edm : 2; // 10 Extended data mode
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uint32_t reserve3 : 2; // 12 Reserve
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uint32_t enable : 1; // 14 PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time.
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uint32_t reserve4 : 3; // 15 Reserve
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uint32_t derdycfg : 3; // 18 Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity.
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uint32_t reserve5 : 9; // 21 Reserve
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uint32_t dmaen : 1; // 30 DMA enable bit
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uint32_t outen : 1; // 31 Data direction selection bit
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} reg_sec_pssi_cr_t;
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typedef struct {
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uint32_t reserve0 : 2; // 0 Reserve
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uint32_t rtt4b : 1; // 2 RTT4B
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uint32_t rtt1b : 1; // 3 RTT1B
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uint32_t reserve1 : 28; // 4 Reserve
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} reg_sec_pssi_sr_t;
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typedef struct {
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uint32_t reserve0 : 1; // 0 Reserve
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uint32_t ovr_ris : 1; // 1 OVR_RIS
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uint32_t reserve1 : 30; // 2 Reserve
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} reg_sec_pssi_ris_t;
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typedef struct {
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uint32_t reserve0 : 1; // 0 Reserve
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uint32_t ovr_ie : 1; // 1 OVR_IE
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uint32_t reserve1 : 30; // 2 Reserve
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} reg_sec_pssi_ier_t;
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typedef struct {
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uint32_t reserve0 : 1; // 0 Reserve
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uint32_t ovr_mis : 1; // 1 OVR_MIS
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uint32_t reserve1 : 30; // 2 Reserve
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} reg_sec_pssi_mis_t;
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typedef struct {
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uint32_t reserve0 : 1; // 0 Reserve
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uint32_t ovr_isc : 1; // 1 OVR_ISC
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uint32_t reserve1 : 30; // 2 Reserve
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} reg_sec_pssi_icr_t;
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typedef struct {
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uint32_t byte0 : 8; // 0 Data byte 0
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uint32_t byte1 : 8; // 8 Data byte 1
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uint32_t byte2 : 8; // 16 Data byte 2
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uint32_t byte3 : 8; // 24 Data byte 3
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} reg_sec_pssi_dr_t;
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typedef struct {
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volatile reg_sec_pssi_cr_t cr;
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volatile reg_sec_pssi_sr_t sr;
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volatile reg_sec_pssi_ris_t ris;
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volatile reg_sec_pssi_ier_t ier;
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volatile reg_sec_pssi_mis_t mis;
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volatile reg_sec_pssi_icr_t icr;
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volatile uint32_t reserve0[4];
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volatile reg_sec_pssi_dr_t dr;
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} reg_sec_pssi_t;
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