1118 lines
169 KiB
C
Executable File
1118 lines
169 KiB
C
Executable File
#include <stdint.h>
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typedef struct {
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uint32_t trgo : 1; // 0 TRGO
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uint32_t reserve0 : 3; // 1 Reserve
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uint32_t ilvnb : 4; // 4 ILVNB
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uint32_t reserve1 : 24; // 8 Reserve
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} reg_mdf_gcr_t;
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typedef struct {
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uint32_t ckgden : 1; // 0 CKGDEN
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uint32_t cck0en : 1; // 1 CCK0EN
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uint32_t cck1en : 1; // 2 CCK1EN
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t ckgmod : 1; // 4 CKGMOD
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uint32_t cck0dir : 1; // 5 CCK0DIR
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uint32_t cck1dir : 1; // 6 CCK1DIR
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uint32_t reserve1 : 1; // 7 Reserve
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uint32_t trgsens : 1; // 8 TRGSENS
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uint32_t reserve2 : 3; // 9 Reserve
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uint32_t trgsrc : 4; // 12 TRGSRC
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uint32_t cckdiv : 4; // 16 CCKDIV
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uint32_t reserve3 : 4; // 20 Reserve
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uint32_t procdiv : 7; // 24 PROCDIV
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uint32_t ckgactive : 1; // 31 CKGACTIVE
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} reg_mdf_ckgcr_t;
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typedef struct {
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uint32_t sitfen : 1; // 0 Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled
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uint32_t scksrc : 2; // 1 Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t sitfmod : 2; // 4 Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve1 : 2; // 6 Reserve
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uint32_t sth : 5; // 8 Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve2 : 18; // 13 Reserve
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uint32_t sitfactive: 1; // 31 Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured.
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} reg_mdf_sitf0cr_t;
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typedef struct {
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uint32_t sitfen : 1; // 0 Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled
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uint32_t scksrc : 2; // 1 Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t sitfmod : 2; // 4 Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve1 : 2; // 6 Reserve
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uint32_t sth : 5; // 8 Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve2 : 18; // 13 Reserve
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uint32_t sitfactive: 1; // 31 Serial interface Active flag
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} reg_mdf_sitf1cr_t;
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typedef struct {
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uint32_t sitfen : 1; // 0 Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled
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uint32_t scksrc : 2; // 1 Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t sitfmod : 2; // 4 Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve1 : 2; // 6 Reserve
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uint32_t sth : 5; // 8 Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve2 : 18; // 13 Reserve
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uint32_t sitfactive: 1; // 31 Serial interface Active flag
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} reg_mdf_sitf2cr_t;
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typedef struct {
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uint32_t sitfen : 1; // 0 Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled
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uint32_t scksrc : 2; // 1 Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t sitfmod : 2; // 4 Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve1 : 2; // 6 Reserve
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uint32_t sth : 5; // 8 Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve2 : 18; // 13 Reserve
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uint32_t sitfactive: 1; // 31 Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured.
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} reg_mdf_sitf3cr_t;
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typedef struct {
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uint32_t sitfen : 1; // 0 Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled
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uint32_t scksrc : 2; // 1 Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t sitfmod : 2; // 4 Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve1 : 2; // 6 Reserve
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uint32_t sth : 5; // 8 Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve2 : 18; // 13 Reserve
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uint32_t sitfactive: 1; // 31 Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured.
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} reg_mdf_sitf4cr_t;
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typedef struct {
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uint32_t sitfen : 1; // 0 Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled
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uint32_t scksrc : 2; // 1 Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t sitfmod : 2; // 4 Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve1 : 2; // 6 Reserve
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uint32_t sth : 5; // 8 Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve2 : 18; // 13 Reserve
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uint32_t sitfactive: 1; // 31 Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured.
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} reg_mdf_sitf5cr_t;
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typedef struct {
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uint32_t bssel : 5; // 0 Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 26; // 5 Reserve
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uint32_t bsmxactive: 1; // 31 BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured.
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} reg_mdf_bsmx0cr_t;
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typedef struct {
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uint32_t bssel : 5; // 0 Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 26; // 5 Reserve
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uint32_t bsmxactive: 1; // 31 BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured.
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} reg_mdf_bsmx1cr_t;
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typedef struct {
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uint32_t bssel : 5; // 0 Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 26; // 5 Reserve
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uint32_t bsmxactive: 1; // 31 BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to a . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured.
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} reg_mdf_bsmx2cr_t;
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typedef struct {
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uint32_t bssel : 5; // 0 Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 26; // 5 Reserve
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uint32_t bsmxactive: 1; // 31 BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to a . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to a in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured.
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} reg_mdf_bsmx3cr_t;
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typedef struct {
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uint32_t bssel : 5; // 0 Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 26; // 5 Reserve
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uint32_t bsmxactive: 1; // 31 BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured.
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} reg_mdf_bsmx4cr_t;
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typedef struct {
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uint32_t bssel : 5; // 0 Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 26; // 5 Reserve
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uint32_t bsmxactive: 1; // 31 BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured.
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} reg_mdf_bsmx5cr_t;
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typedef struct {
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uint32_t dflten : 1; // 0 Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,
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uint32_t dmaen : 1; // 1 DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t fth : 1; // 2 RXFIFO Threshold selection Set and cleared by software.
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t acqmod : 3; // 4 Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve1 : 1; // 7 Reserve
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uint32_t trgsens : 1; // 8 Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve2 : 3; // 9 Reserve
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uint32_t trgsrc : 4; // 12 Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t snpsfmt : 1; // 16 Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve3 : 3; // 17 Reserve
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uint32_t nbdis : 8; // 20 Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve4 : 2; // 28 Reserve
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uint32_t dfltrun : 1; // 30 Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running
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uint32_t dfltactive: 1; // 31 Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active
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} reg_mdf_dflt0cr_t;
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typedef struct {
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uint32_t dflten : 1; // 0 Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,
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uint32_t dmaen : 1; // 1 DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t fth : 1; // 2 RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t acqmod : 3; // 4 Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve1 : 1; // 7 Reserve
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uint32_t trgsens : 1; // 8 Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve2 : 3; // 9 Reserve
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uint32_t trgsrc : 4; // 12 Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t snpsfmt : 1; // 16 Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve3 : 3; // 17 Reserve
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uint32_t nbdis : 8; // 20 Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve4 : 2; // 28 Reserve
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uint32_t dfltrun : 1; // 30 Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running
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uint32_t dfltactive: 1; // 31 Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active
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} reg_mdf_dflt1cr_t;
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typedef struct {
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uint32_t dflten : 1; // 0 Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,
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uint32_t dmaen : 1; // 1 DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t fth : 1; // 2 RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t acqmod : 3; // 4 Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve1 : 1; // 7 Reserve
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uint32_t trgsens : 1; // 8 Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve2 : 3; // 9 Reserve
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uint32_t trgsrc : 4; // 12 Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t snpsfmt : 1; // 16 Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve3 : 3; // 17 Reserve
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uint32_t nbdis : 8; // 20 Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve4 : 2; // 28 Reserve
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uint32_t dfltrun : 1; // 30 Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running
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uint32_t dfltactive: 1; // 31 Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active
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} reg_mdf_dflt2cr_t;
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typedef struct {
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uint32_t dflten : 1; // 0 Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,
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uint32_t dmaen : 1; // 1 DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t fth : 1; // 2 RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t acqmod : 3; // 4 Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve1 : 1; // 7 Reserve
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uint32_t trgsens : 1; // 8 Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve2 : 3; // 9 Reserve
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uint32_t trgsrc : 4; // 12 Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t snpsfmt : 1; // 16 Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve3 : 3; // 17 Reserve
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uint32_t nbdis : 8; // 20 Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve4 : 2; // 28 Reserve
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uint32_t dfltrun : 1; // 30 Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running
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uint32_t dfltactive: 1; // 31 Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active
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} reg_mdf_dflt3cr_t;
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typedef struct {
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uint32_t dflten : 1; // 0 Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,
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uint32_t dmaen : 1; // 1 DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t fth : 1; // 2 RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t acqmod : 3; // 4 Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve1 : 1; // 7 Reserve
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uint32_t trgsens : 1; // 8 Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve2 : 3; // 9 Reserve
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uint32_t trgsrc : 4; // 12 Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t snpsfmt : 1; // 16 Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve3 : 3; // 17 Reserve
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uint32_t nbdis : 8; // 20 Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve4 : 2; // 28 Reserve
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uint32_t dfltrun : 1; // 30 Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running
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uint32_t dfltactive: 1; // 31 Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active
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} reg_mdf_dflt4cr_t;
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typedef struct {
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uint32_t dflten : 1; // 0 Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx ,
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uint32_t dmaen : 1; // 1 DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t fth : 1; // 2 RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 1; // 3 Reserve
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uint32_t acqmod : 3; // 4 Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve1 : 1; // 7 Reserve
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uint32_t trgsens : 1; // 8 Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve2 : 3; // 9 Reserve
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uint32_t trgsrc : 4; // 12 Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t snpsfmt : 1; // 16 Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve3 : 3; // 17 Reserve
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uint32_t nbdis : 8; // 20 Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve4 : 2; // 28 Reserve
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uint32_t dfltrun : 1; // 30 Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running
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uint32_t dfltactive: 1; // 31 Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active
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} reg_mdf_dflt5cr_t;
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typedef struct {
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uint32_t datsrc : 2; // 0 Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 2; // 2 Reserve
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uint32_t cicmod : 3; // 4 Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve1 : 1; // 7 Reserve
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uint32_t mcicd : 9; // 8 CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve2 : 3; // 17 Reserve
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uint32_t scale : 6; // 20 Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits
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uint32_t reserve3 : 6; // 26 Reserve
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} reg_mdf_dflt0cicr_t;
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typedef struct {
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uint32_t datsrc : 2; // 0 Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve0 : 2; // 2 Reserve
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uint32_t cicmod : 3; // 4 Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve1 : 1; // 7 Reserve
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uint32_t mcicd : 9; // 8 CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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uint32_t reserve2 : 3; // 17 Reserve
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|
uint32_t scale : 6; // 20 Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits
|
|
uint32_t reserve3 : 6; // 26 Reserve
|
|
} reg_mdf_dflt1cicr_t;
|
|
|
|
typedef struct {
|
|
uint32_t datsrc : 2; // 0 Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t cicmod : 3; // 4 Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 1; // 7 Reserve
|
|
uint32_t mcicd : 9; // 8 CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 3; // 17 Reserve
|
|
uint32_t scale : 6; // 20 Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits
|
|
uint32_t reserve3 : 6; // 26 Reserve
|
|
} reg_mdf_dflt2cicr_t;
|
|
|
|
typedef struct {
|
|
uint32_t datsrc : 2; // 0 Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t cicmod : 3; // 4 Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 1; // 7 Reserve
|
|
uint32_t mcicd : 9; // 8 CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 3; // 17 Reserve
|
|
uint32_t scale : 6; // 20 Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits
|
|
uint32_t reserve3 : 6; // 26 Reserve
|
|
} reg_mdf_dflt3cicr_t;
|
|
|
|
typedef struct {
|
|
uint32_t datsrc : 2; // 0 Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t cicmod : 3; // 4 Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 1; // 7 Reserve
|
|
uint32_t mcicd : 9; // 8 CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 3; // 17 Reserve
|
|
uint32_t scale : 6; // 20 Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits
|
|
uint32_t reserve3 : 6; // 26 Reserve
|
|
} reg_mdf_dflt4cicr_t;
|
|
|
|
typedef struct {
|
|
uint32_t datsrc : 2; // 0 Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t cicmod : 3; // 4 Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 1; // 7 Reserve
|
|
uint32_t mcicd : 9; // 8 CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 3; // 17 Reserve
|
|
uint32_t scale : 6; // 20 Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits
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|
uint32_t reserve3 : 6; // 26 Reserve
|
|
} reg_mdf_dflt5cicr_t;
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|
|
|
typedef struct {
|
|
uint32_t rsfltbyp : 1; // 0 Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 3; // 1 Reserve
|
|
uint32_t rsfltd : 1; // 4 Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 2; // 5 Reserve
|
|
uint32_t hpfbyp : 1; // 7 High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t hpfc : 2; // 8 High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 22; // 10 Reserve
|
|
} reg_mdf_dflt0rsfr_t;
|
|
|
|
typedef struct {
|
|
uint32_t rsfltbyp : 1; // 0 Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 3; // 1 Reserve
|
|
uint32_t rsfltd : 1; // 4 Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 2; // 5 Reserve
|
|
uint32_t hpfbyp : 1; // 7 High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t hpfc : 2; // 8 High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 22; // 10 Reserve
|
|
} reg_mdf_dflt1rsfr_t;
|
|
|
|
typedef struct {
|
|
uint32_t rsfltbyp : 1; // 0 Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 3; // 1 Reserve
|
|
uint32_t rsfltd : 1; // 4 Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 2; // 5 Reserve
|
|
uint32_t hpfbyp : 1; // 7 High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t hpfc : 2; // 8 High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 22; // 10 Reserve
|
|
} reg_mdf_dflt2rsfr_t;
|
|
|
|
typedef struct {
|
|
uint32_t rsfltbyp : 1; // 0 Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 3; // 1 Reserve
|
|
uint32_t rsfltd : 1; // 4 Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 2; // 5 Reserve
|
|
uint32_t hpfbyp : 1; // 7 High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t hpfc : 2; // 8 High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 22; // 10 Reserve
|
|
} reg_mdf_dflt3rsfr_t;
|
|
|
|
typedef struct {
|
|
uint32_t rsfltbyp : 1; // 0 Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 3; // 1 Reserve
|
|
uint32_t rsfltd : 1; // 4 Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 2; // 5 Reserve
|
|
uint32_t hpfbyp : 1; // 7 High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t hpfc : 2; // 8 High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 22; // 10 Reserve
|
|
} reg_mdf_dflt4rsfr_t;
|
|
|
|
typedef struct {
|
|
uint32_t rsfltbyp : 1; // 0 Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 3; // 1 Reserve
|
|
uint32_t rsfltd : 1; // 4 Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 2; // 5 Reserve
|
|
uint32_t hpfbyp : 1; // 7 High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t hpfc : 2; // 8 High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 22; // 10 Reserve
|
|
} reg_mdf_dflt5rsfr_t;
|
|
|
|
typedef struct {
|
|
uint32_t intdiv : 2; // 0 Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t intval : 7; // 4 Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 21; // 11 Reserve
|
|
} reg_mdf_dflt0intr_t;
|
|
|
|
typedef struct {
|
|
uint32_t intdiv : 2; // 0 Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t intval : 7; // 4 Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 21; // 11 Reserve
|
|
} reg_mdf_dflt1intr_t;
|
|
|
|
typedef struct {
|
|
uint32_t intdiv : 2; // 0 Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t intval : 7; // 4 Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 21; // 11 Reserve
|
|
} reg_mdf_dflt2intr_t;
|
|
|
|
typedef struct {
|
|
uint32_t intdiv : 2; // 0 Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t intval : 7; // 4 Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 21; // 11 Reserve
|
|
} reg_mdf_dflt3intr_t;
|
|
|
|
typedef struct {
|
|
uint32_t intdiv : 2; // 0 Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t intval : 7; // 4 Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 21; // 11 Reserve
|
|
} reg_mdf_dflt4intr_t;
|
|
|
|
typedef struct {
|
|
uint32_t intdiv : 2; // 0 Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t intval : 7; // 4 Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 21; // 11 Reserve
|
|
} reg_mdf_dflt5intr_t;
|
|
|
|
typedef struct {
|
|
uint32_t olden : 1; // 0 Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode.
|
|
uint32_t thinb : 1; // 1 Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t bkold : 4; // 4 Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 4; // 8 Reserve
|
|
uint32_t acicn : 2; // 12 OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 3; // 14 Reserve
|
|
uint32_t acicd : 5; // 17 OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve3 : 9; // 22 Reserve
|
|
uint32_t oldactive : 1; // 31 OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured.
|
|
} reg_mdf_old0cr_t;
|
|
|
|
typedef struct {
|
|
uint32_t olden : 1; // 0 Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode.
|
|
uint32_t thinb : 1; // 1 Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t bkold : 4; // 4 Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 4; // 8 Reserve
|
|
uint32_t acicn : 2; // 12 OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 3; // 14 Reserve
|
|
uint32_t acicd : 5; // 17 OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve3 : 9; // 22 Reserve
|
|
uint32_t oldactive : 1; // 31 OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured.
|
|
} reg_mdf_old1cr_t;
|
|
|
|
typedef struct {
|
|
uint32_t olden : 1; // 0 Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode.
|
|
uint32_t thinb : 1; // 1 Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t bkold : 4; // 4 Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 4; // 8 Reserve
|
|
uint32_t acicn : 2; // 12 OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 3; // 14 Reserve
|
|
uint32_t acicd : 5; // 17 OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve3 : 9; // 22 Reserve
|
|
uint32_t oldactive : 1; // 31 OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured.
|
|
} reg_mdf_old2cr_t;
|
|
|
|
typedef struct {
|
|
uint32_t olden : 1; // 0 Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode.
|
|
uint32_t thinb : 1; // 1 Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t bkold : 4; // 4 Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 4; // 8 Reserve
|
|
uint32_t acicn : 2; // 12 OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 3; // 14 Reserve
|
|
uint32_t acicd : 5; // 17 OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve3 : 9; // 22 Reserve
|
|
uint32_t oldactive : 1; // 31 OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured.
|
|
} reg_mdf_old3cr_t;
|
|
|
|
typedef struct {
|
|
uint32_t olden : 1; // 0 Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode.
|
|
uint32_t thinb : 1; // 1 Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t bkold : 4; // 4 Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 4; // 8 Reserve
|
|
uint32_t acicn : 2; // 12 OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 3; // 14 Reserve
|
|
uint32_t acicd : 5; // 17 OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve3 : 9; // 22 Reserve
|
|
uint32_t oldactive : 1; // 31 OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured.
|
|
} reg_mdf_old4cr_t;
|
|
|
|
typedef struct {
|
|
uint32_t olden : 1; // 0 Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode.
|
|
uint32_t thinb : 1; // 1 Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 2; // 2 Reserve
|
|
uint32_t bkold : 4; // 4 Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 4; // 8 Reserve
|
|
uint32_t acicn : 2; // 12 OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 3; // 14 Reserve
|
|
uint32_t acicd : 5; // 17 OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve3 : 9; // 22 Reserve
|
|
uint32_t oldactive : 1; // 31 OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured.
|
|
} reg_mdf_old5cr_t;
|
|
|
|
typedef struct {
|
|
uint32_t oldthl : 26; // 0 OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_old0thlr_t;
|
|
|
|
typedef struct {
|
|
uint32_t oldthl : 26; // 0 OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_old1thlr_t;
|
|
|
|
typedef struct {
|
|
uint32_t oldthl : 26; // 0 OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_old2thlr_t;
|
|
|
|
typedef struct {
|
|
uint32_t oldthl : 26; // 0 OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_old3thlr_t;
|
|
|
|
typedef struct {
|
|
uint32_t oldthl : 26; // 0 OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_old4thlr_t;
|
|
|
|
typedef struct {
|
|
uint32_t oldthl : 26; // 0 OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_old5thlr_t;
|
|
|
|
typedef struct {
|
|
uint32_t oldthh : 26; // 0 OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_old0thhr_t;
|
|
|
|
typedef struct {
|
|
uint32_t oldthh : 26; // 0 OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_old1thhr_t;
|
|
|
|
typedef struct {
|
|
uint32_t oldthh : 26; // 0 OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_old2thhr_t;
|
|
|
|
typedef struct {
|
|
uint32_t oldthh : 26; // 0 OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_old3thhr_t;
|
|
|
|
typedef struct {
|
|
uint32_t oldthh : 26; // 0 OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_old4thhr_t;
|
|
|
|
typedef struct {
|
|
uint32_t oldthh : 26; // 0 OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_old5thhr_t;
|
|
|
|
typedef struct {
|
|
uint32_t skpdly : 7; // 0 Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,
|
|
uint32_t reserve0 : 24; // 7 Reserve
|
|
uint32_t skpbf : 1; // 31 Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing.
|
|
} reg_mdf_dly0cr_t;
|
|
|
|
typedef struct {
|
|
uint32_t skpdly : 7; // 0 Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,
|
|
uint32_t reserve0 : 24; // 7 Reserve
|
|
uint32_t skpbf : 1; // 31 Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing.
|
|
} reg_mdf_dly1cr_t;
|
|
|
|
typedef struct {
|
|
uint32_t skpdly : 7; // 0 Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,
|
|
uint32_t reserve0 : 24; // 7 Reserve
|
|
uint32_t skpbf : 1; // 31 Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing.
|
|
} reg_mdf_dly2cr_t;
|
|
|
|
typedef struct {
|
|
uint32_t skpdly : 7; // 0 Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,
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|
uint32_t reserve0 : 24; // 7 Reserve
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|
uint32_t skpbf : 1; // 31 Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing.
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|
} reg_mdf_dly3cr_t;
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|
|
|
typedef struct {
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|
uint32_t skpdly : 7; // 0 Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,
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|
uint32_t reserve0 : 24; // 7 Reserve
|
|
uint32_t skpbf : 1; // 31 Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing.
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|
} reg_mdf_dly4cr_t;
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|
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|
typedef struct {
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|
uint32_t skpdly : 7; // 0 Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped,
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|
uint32_t reserve0 : 24; // 7 Reserve
|
|
uint32_t skpbf : 1; // 31 Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing.
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|
} reg_mdf_dly5cr_t;
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|
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|
typedef struct {
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|
uint32_t scden : 1; // 0 Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,
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uint32_t reserve0 : 3; // 1 Reserve
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|
uint32_t bkscd : 4; // 4 Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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|
uint32_t reserve1 : 4; // 8 Reserve
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|
uint32_t scdt : 8; // 12 Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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|
uint32_t reserve2 : 11; // 20 Reserve
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uint32_t scdactive : 1; // 31 SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured.
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|
} reg_mdf_scd0cr_t;
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|
|
|
typedef struct {
|
|
uint32_t scden : 1; // 0 Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,
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uint32_t reserve0 : 3; // 1 Reserve
|
|
uint32_t bkscd : 4; // 4 Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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|
uint32_t reserve1 : 4; // 8 Reserve
|
|
uint32_t scdt : 8; // 12 Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
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|
uint32_t reserve2 : 11; // 20 Reserve
|
|
uint32_t scdactive : 1; // 31 SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured.
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|
} reg_mdf_scd1cr_t;
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|
|
|
typedef struct {
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|
uint32_t scden : 1; // 0 Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,
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|
uint32_t reserve0 : 3; // 1 Reserve
|
|
uint32_t bkscd : 4; // 4 Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 4; // 8 Reserve
|
|
uint32_t scdt : 8; // 12 Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 11; // 20 Reserve
|
|
uint32_t scdactive : 1; // 31 SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured.
|
|
} reg_mdf_scd2cr_t;
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|
|
|
typedef struct {
|
|
uint32_t scden : 1; // 0 Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,
|
|
uint32_t reserve0 : 3; // 1 Reserve
|
|
uint32_t bkscd : 4; // 4 Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 4; // 8 Reserve
|
|
uint32_t scdt : 8; // 12 Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 11; // 20 Reserve
|
|
uint32_t scdactive : 1; // 31 SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured.
|
|
} reg_mdf_scd3cr_t;
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|
|
|
typedef struct {
|
|
uint32_t scden : 1; // 0 Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,
|
|
uint32_t reserve0 : 3; // 1 Reserve
|
|
uint32_t bkscd : 4; // 4 Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 4; // 8 Reserve
|
|
uint32_t scdt : 8; // 12 Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 11; // 20 Reserve
|
|
uint32_t scdactive : 1; // 31 SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured.
|
|
} reg_mdf_scd4cr_t;
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|
|
|
typedef struct {
|
|
uint32_t scden : 1; // 0 Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled,
|
|
uint32_t reserve0 : 3; // 1 Reserve
|
|
uint32_t bkscd : 4; // 4 Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve1 : 4; // 8 Reserve
|
|
uint32_t scdt : 8; // 12 Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details.
|
|
uint32_t reserve2 : 11; // 20 Reserve
|
|
uint32_t scdactive : 1; // 31 SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured.
|
|
} reg_mdf_scd5cr_t;
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|
|
|
typedef struct {
|
|
uint32_t fthie : 1; // 0 RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled
|
|
uint32_t dovrie : 1; // 1 Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled
|
|
uint32_t ssdrie : 1; // 2 Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled
|
|
uint32_t reserve0 : 1; // 3 Reserve
|
|
uint32_t oldie : 1; // 4 Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled
|
|
uint32_t reserve1 : 2; // 5 Reserve
|
|
uint32_t ssovrie : 1; // 7 Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled
|
|
uint32_t scdie : 1; // 8 Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled
|
|
uint32_t satie : 1; // 9 Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled
|
|
uint32_t ckabie : 1; // 10 Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled
|
|
uint32_t rfovrie : 1; // 11 Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled
|
|
uint32_t reserve2 : 20; // 12 Reserve
|
|
} reg_mdf_dflt0ier_t;
|
|
|
|
typedef struct {
|
|
uint32_t fthf : 1; // 0 FTHF
|
|
uint32_t dovrf : 1; // 1 Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag.
|
|
uint32_t ssdrf : 1; // 2 Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on , writing 0 has no effect. - 1: Reading 1 means that a new data is available on , writing 1 clears this flag.
|
|
uint32_t rxnef : 1; // 3 RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty.
|
|
uint32_t oldf : 1; // 4 Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags.
|
|
uint32_t thlf : 1; // 5 Low threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was higher than OLDTHL when the last OLD event occurred. - 1: The signal was lower than OLDTHL when the last OLD event occurred.
|
|
uint32_t thhf : 1; // 6 High threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH when the last OLD event occurred. - 1: The signal was higher than OLDTHH when the last OLD event occurred.
|
|
uint32_t ssovrf : 1; // 7 Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag.
|
|
uint32_t scdf : 1; // 8 Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag.
|
|
uint32_t satf : 1; // 9 Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag.
|
|
uint32_t ckabf : 1; // 10 Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag.
|
|
uint32_t rfovrf : 1; // 11 Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag.
|
|
uint32_t reserve0 : 20; // 12 Reserve
|
|
} reg_mdf_dflt0isr_t;
|
|
|
|
typedef struct {
|
|
uint32_t fthie : 1; // 0 RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled
|
|
uint32_t dovrie : 1; // 1 Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled
|
|
uint32_t ssdrie : 1; // 2 Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled
|
|
uint32_t reserve0 : 1; // 3 Reserve
|
|
uint32_t oldie : 1; // 4 Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled
|
|
uint32_t reserve1 : 2; // 5 Reserve
|
|
uint32_t ssovrie : 1; // 7 Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled
|
|
uint32_t scdie : 1; // 8 Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled
|
|
uint32_t satie : 1; // 9 Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled
|
|
uint32_t ckabie : 1; // 10 Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled
|
|
uint32_t rfovrie : 1; // 11 Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled
|
|
uint32_t reserve2 : 20; // 12 Reserve
|
|
} reg_mdf_dflt1ier_t;
|
|
|
|
typedef struct {
|
|
uint32_t fthie : 1; // 0 RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled
|
|
uint32_t dovrie : 1; // 1 Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled
|
|
uint32_t ssdrie : 1; // 2 Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled
|
|
uint32_t reserve0 : 1; // 3 Reserve
|
|
uint32_t oldie : 1; // 4 Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled
|
|
uint32_t reserve1 : 2; // 5 Reserve
|
|
uint32_t ssovrie : 1; // 7 Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled
|
|
uint32_t scdie : 1; // 8 Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled
|
|
uint32_t satie : 1; // 9 Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled
|
|
uint32_t ckabie : 1; // 10 Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled
|
|
uint32_t rfovrie : 1; // 11 Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled
|
|
uint32_t reserve2 : 20; // 12 Reserve
|
|
} reg_mdf_dflt2ier_t;
|
|
|
|
typedef struct {
|
|
uint32_t fthie : 1; // 0 RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled
|
|
uint32_t dovrie : 1; // 1 Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled
|
|
uint32_t ssdrie : 1; // 2 Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled
|
|
uint32_t reserve0 : 1; // 3 Reserve
|
|
uint32_t oldie : 1; // 4 Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled
|
|
uint32_t reserve1 : 2; // 5 Reserve
|
|
uint32_t ssovrie : 1; // 7 Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled
|
|
uint32_t scdie : 1; // 8 Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled
|
|
uint32_t satie : 1; // 9 Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled
|
|
uint32_t ckabie : 1; // 10 Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled
|
|
uint32_t rfovrie : 1; // 11 Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled
|
|
uint32_t reserve2 : 20; // 12 Reserve
|
|
} reg_mdf_dflt3ier_t;
|
|
|
|
typedef struct {
|
|
uint32_t fthie : 1; // 0 RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled
|
|
uint32_t dovrie : 1; // 1 Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled
|
|
uint32_t ssdrie : 1; // 2 Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled
|
|
uint32_t reserve0 : 1; // 3 Reserve
|
|
uint32_t oldie : 1; // 4 Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled
|
|
uint32_t reserve1 : 2; // 5 Reserve
|
|
uint32_t ssovrie : 1; // 7 Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled
|
|
uint32_t scdie : 1; // 8 Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled
|
|
uint32_t satie : 1; // 9 Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled
|
|
uint32_t ckabie : 1; // 10 Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled
|
|
uint32_t rfovrie : 1; // 11 Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled
|
|
uint32_t reserve2 : 20; // 12 Reserve
|
|
} reg_mdf_dflt4ier_t;
|
|
|
|
typedef struct {
|
|
uint32_t fthie : 1; // 0 RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled
|
|
uint32_t dovrie : 1; // 1 Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled
|
|
uint32_t ssdrie : 1; // 2 Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled
|
|
uint32_t reserve0 : 1; // 3 Reserve
|
|
uint32_t oldie : 1; // 4 Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled
|
|
uint32_t reserve1 : 2; // 5 Reserve
|
|
uint32_t ssovrie : 1; // 7 Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled
|
|
uint32_t scdie : 1; // 8 Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled
|
|
uint32_t satie : 1; // 9 Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled
|
|
uint32_t ckabie : 1; // 10 Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled
|
|
uint32_t rfovrie : 1; // 11 Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled
|
|
uint32_t reserve2 : 20; // 12 Reserve
|
|
} reg_mdf_dflt5ier_t;
|
|
|
|
typedef struct {
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|
uint32_t fthf : 1; // 0 RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag.
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|
uint32_t dovrf : 1; // 1 Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag.
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|
uint32_t ssdrf : 1; // 2 Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag.
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|
uint32_t rxnef : 1; // 3 RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty.
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|
uint32_t oldf : 1; // 4 Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags.
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|
uint32_t thlf : 1; // 5 Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred
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|
uint32_t thhf : 1; // 6 High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred
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|
uint32_t ssovrf : 1; // 7 Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag.
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|
uint32_t scdf : 1; // 8 Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag.
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uint32_t satf : 1; // 9 Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag.
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|
uint32_t ckabf : 1; // 10 Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag.
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|
uint32_t rfovrf : 1; // 11 Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag.
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|
uint32_t reserve0 : 20; // 12 Reserve
|
|
} reg_mdf_dflt1isr_t;
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|
|
|
typedef struct {
|
|
uint32_t fthf : 1; // 0 RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag.
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|
uint32_t dovrf : 1; // 1 Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag.
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|
uint32_t ssdrf : 1; // 2 Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag.
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uint32_t rxnef : 1; // 3 RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty.
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|
uint32_t oldf : 1; // 4 Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags.
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|
uint32_t thlf : 1; // 5 Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred
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|
uint32_t thhf : 1; // 6 High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred
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|
uint32_t ssovrf : 1; // 7 Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag.
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|
uint32_t scdf : 1; // 8 Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag.
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uint32_t satf : 1; // 9 Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag.
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|
uint32_t ckabf : 1; // 10 Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag.
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|
uint32_t rfovrf : 1; // 11 Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag.
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|
uint32_t reserve0 : 20; // 12 Reserve
|
|
} reg_mdf_dflt2isr_t;
|
|
|
|
typedef struct {
|
|
uint32_t fthf : 1; // 0 RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag.
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|
uint32_t dovrf : 1; // 1 Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag.
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|
uint32_t ssdrf : 1; // 2 Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag.
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|
uint32_t rxnef : 1; // 3 RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty.
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|
uint32_t oldf : 1; // 4 Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags.
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|
uint32_t thlf : 1; // 5 Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred
|
|
uint32_t thhf : 1; // 6 High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred
|
|
uint32_t ssovrf : 1; // 7 Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag.
|
|
uint32_t scdf : 1; // 8 Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag.
|
|
uint32_t satf : 1; // 9 Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag.
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|
uint32_t ckabf : 1; // 10 Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag.
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|
uint32_t rfovrf : 1; // 11 Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag.
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|
uint32_t reserve0 : 20; // 12 Reserve
|
|
} reg_mdf_dflt3isr_t;
|
|
|
|
typedef struct {
|
|
uint32_t fthf : 1; // 0 RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag.
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|
uint32_t dovrf : 1; // 1 Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag.
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|
uint32_t ssdrf : 1; // 2 Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag.
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|
uint32_t rxnef : 1; // 3 RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty.
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|
uint32_t oldf : 1; // 4 Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags.
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|
uint32_t thlf : 1; // 5 Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred
|
|
uint32_t thhf : 1; // 6 High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred
|
|
uint32_t ssovrf : 1; // 7 Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag.
|
|
uint32_t scdf : 1; // 8 Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag.
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|
uint32_t satf : 1; // 9 Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag.
|
|
uint32_t ckabf : 1; // 10 Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag.
|
|
uint32_t rfovrf : 1; // 11 Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag.
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|
uint32_t reserve0 : 20; // 12 Reserve
|
|
} reg_mdf_dflt4isr_t;
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|
|
|
typedef struct {
|
|
uint32_t fthf : 1; // 0 RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag.
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|
uint32_t dovrf : 1; // 1 Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag.
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|
uint32_t ssdrf : 1; // 2 Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag.
|
|
uint32_t rxnef : 1; // 3 RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty.
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|
uint32_t oldf : 1; // 4 Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags.
|
|
uint32_t thlf : 1; // 5 Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred
|
|
uint32_t thhf : 1; // 6 High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred
|
|
uint32_t ssovrf : 1; // 7 Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag.
|
|
uint32_t scdf : 1; // 8 Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag.
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uint32_t satf : 1; // 9 Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag.
|
|
uint32_t ckabf : 1; // 10 Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag.
|
|
uint32_t rfovrf : 1; // 11 Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag.
|
|
uint32_t reserve0 : 20; // 12 Reserve
|
|
} reg_mdf_dflt5isr_t;
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|
|
|
typedef struct {
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|
uint32_t offset : 26; // 0 Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE.
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uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_oec0cr_t;
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|
|
|
typedef struct {
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|
uint32_t offset : 26; // 0 Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE.
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_oec1cr_t;
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|
|
|
typedef struct {
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|
uint32_t offset : 26; // 0 Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE.
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|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_oec2cr_t;
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|
|
|
typedef struct {
|
|
uint32_t offset : 26; // 0 Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE.
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_oec3cr_t;
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|
|
|
typedef struct {
|
|
uint32_t offset : 26; // 0 Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE.
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_oec4cr_t;
|
|
|
|
typedef struct {
|
|
uint32_t offset : 26; // 0 Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE.
|
|
uint32_t reserve0 : 6; // 26 Reserve
|
|
} reg_mdf_oec5cr_t;
|
|
|
|
typedef struct {
|
|
uint32_t mcicdc : 9; // 0 Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)
|
|
uint32_t extsdr : 7; // 9 Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT).
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uint32_t sdr : 16; // 16 Contains the 16 MSB of the last valid data processed by the digital filter.
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|
} reg_mdf_snps0dr_t;
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|
|
|
typedef struct {
|
|
uint32_t mcicdc : 9; // 0 Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)
|
|
uint32_t extsdr : 7; // 9 Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT).
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uint32_t sdr : 16; // 16 Contains the 16 MSB of the last valid data processed by the digital filter.
|
|
} reg_mdf_snps1dr_t;
|
|
|
|
typedef struct {
|
|
uint32_t mcicdc : 9; // 0 Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)
|
|
uint32_t extsdr : 7; // 9 Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT).
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uint32_t sdr : 16; // 16 Contains the 16 MSB of the last valid data processed by the digital filter.
|
|
} reg_mdf_snps2dr_t;
|
|
|
|
typedef struct {
|
|
uint32_t mcicdc : 9; // 0 Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)
|
|
uint32_t extsdr : 7; // 9 Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT).
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|
uint32_t sdr : 16; // 16 Contains the 16 MSB of the last valid data processed by the digital filter.
|
|
} reg_mdf_snps3dr_t;
|
|
|
|
typedef struct {
|
|
uint32_t mcicdc : 9; // 0 Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)
|
|
uint32_t extsdr : 7; // 9 Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT).
|
|
uint32_t sdr : 16; // 16 Contains the 16 MSB of the last valid data processed by the digital filter.
|
|
} reg_mdf_snps4dr_t;
|
|
|
|
typedef struct {
|
|
uint32_t mcicdc : 9; // 0 Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT)
|
|
uint32_t extsdr : 7; // 9 Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT).
|
|
uint32_t sdr : 16; // 16 Contains the 16 MSB of the last valid data processed by the digital filter.
|
|
} reg_mdf_snps5dr_t;
|
|
|
|
typedef struct {
|
|
uint32_t reserve0 : 8; // 0 Reserve
|
|
uint32_t dr : 24; // 8 Data processed by digital filter.
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|
} reg_mdf_dflt0dr_t;
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typedef struct {
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uint32_t reserve0 : 8; // 0 Reserve
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uint32_t dr : 24; // 8 Data processed by digital filter.
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} reg_mdf_dflt1dr_t;
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typedef struct {
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uint32_t reserve0 : 8; // 0 Reserve
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uint32_t dr : 24; // 8 Data processed by digital filter.
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} reg_mdf_dflt2dr_t;
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|
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typedef struct {
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uint32_t reserve0 : 8; // 0 Reserve
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uint32_t dr : 24; // 8 Data processed by digital filter.
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} reg_mdf_dflt3dr_t;
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|
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typedef struct {
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uint32_t reserve0 : 8; // 0 Reserve
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uint32_t dr : 24; // 8 Data processed by digital filter.
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} reg_mdf_dflt4dr_t;
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|
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typedef struct {
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uint32_t reserve0 : 8; // 0 Reserve
|
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uint32_t dr : 24; // 8 Data processed by digital filter.
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} reg_mdf_dflt5dr_t;
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typedef struct {
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volatile reg_mdf_gcr_t gcr;
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volatile reg_mdf_ckgcr_t ckgcr;
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volatile uint32_t reserve0[30];
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volatile reg_mdf_sitf0cr_t sitf0cr;
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volatile uint32_t reserve1[31];
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volatile reg_mdf_sitf1cr_t sitf1cr;
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volatile uint32_t reserve2[31];
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volatile reg_mdf_sitf2cr_t sitf2cr;
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volatile uint32_t reserve3[31];
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volatile reg_mdf_sitf3cr_t sitf3cr;
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volatile uint32_t reserve4[31];
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volatile reg_mdf_sitf4cr_t sitf4cr;
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volatile uint32_t reserve5[31];
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volatile reg_mdf_sitf5cr_t sitf5cr;
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volatile uint32_t reserve6[-160];
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volatile reg_mdf_bsmx0cr_t bsmx0cr;
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volatile uint32_t reserve7[31];
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volatile reg_mdf_bsmx1cr_t bsmx1cr;
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volatile uint32_t reserve8[31];
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volatile reg_mdf_bsmx2cr_t bsmx2cr;
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volatile uint32_t reserve9[31];
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volatile reg_mdf_bsmx3cr_t bsmx3cr;
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volatile uint32_t reserve10[31];
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volatile reg_mdf_bsmx4cr_t bsmx4cr;
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volatile uint32_t reserve11[31];
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volatile reg_mdf_bsmx5cr_t bsmx5cr;
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volatile uint32_t reserve12[-160];
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volatile reg_mdf_dflt0cr_t dflt0cr;
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volatile uint32_t reserve13[31];
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volatile reg_mdf_dflt1cr_t dflt1cr;
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volatile uint32_t reserve14[31];
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volatile reg_mdf_dflt2cr_t dflt2cr;
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volatile uint32_t reserve15[31];
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volatile reg_mdf_dflt3cr_t dflt3cr;
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volatile uint32_t reserve16[31];
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volatile reg_mdf_dflt4cr_t dflt4cr;
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volatile uint32_t reserve17[31];
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volatile reg_mdf_dflt5cr_t dflt5cr;
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volatile uint32_t reserve18[-160];
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volatile reg_mdf_dflt0cicr_t dflt0cicr;
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volatile uint32_t reserve19[31];
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volatile reg_mdf_dflt1cicr_t dflt1cicr;
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volatile uint32_t reserve20[31];
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volatile reg_mdf_dflt2cicr_t dflt2cicr;
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volatile uint32_t reserve21[31];
|
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volatile reg_mdf_dflt3cicr_t dflt3cicr;
|
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volatile uint32_t reserve22[31];
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volatile reg_mdf_dflt4cicr_t dflt4cicr;
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volatile uint32_t reserve23[31];
|
|
volatile reg_mdf_dflt5cicr_t dflt5cicr;
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volatile uint32_t reserve24[-160];
|
|
volatile reg_mdf_dflt0rsfr_t dflt0rsfr;
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volatile uint32_t reserve25[31];
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|
volatile reg_mdf_dflt1rsfr_t dflt1rsfr;
|
|
volatile uint32_t reserve26[31];
|
|
volatile reg_mdf_dflt2rsfr_t dflt2rsfr;
|
|
volatile uint32_t reserve27[31];
|
|
volatile reg_mdf_dflt3rsfr_t dflt3rsfr;
|
|
volatile uint32_t reserve28[31];
|
|
volatile reg_mdf_dflt4rsfr_t dflt4rsfr;
|
|
volatile uint32_t reserve29[31];
|
|
volatile reg_mdf_dflt5rsfr_t dflt5rsfr;
|
|
volatile uint32_t reserve30[-160];
|
|
volatile reg_mdf_dflt0intr_t dflt0intr;
|
|
volatile uint32_t reserve31[31];
|
|
volatile reg_mdf_dflt1intr_t dflt1intr;
|
|
volatile uint32_t reserve32[31];
|
|
volatile reg_mdf_dflt2intr_t dflt2intr;
|
|
volatile uint32_t reserve33[31];
|
|
volatile reg_mdf_dflt3intr_t dflt3intr;
|
|
volatile uint32_t reserve34[31];
|
|
volatile reg_mdf_dflt4intr_t dflt4intr;
|
|
volatile uint32_t reserve35[31];
|
|
volatile reg_mdf_dflt5intr_t dflt5intr;
|
|
volatile uint32_t reserve36[-160];
|
|
volatile reg_mdf_old0cr_t old0cr;
|
|
volatile uint32_t reserve37[31];
|
|
volatile reg_mdf_old1cr_t old1cr;
|
|
volatile uint32_t reserve38[31];
|
|
volatile reg_mdf_old2cr_t old2cr;
|
|
volatile uint32_t reserve39[31];
|
|
volatile reg_mdf_old3cr_t old3cr;
|
|
volatile uint32_t reserve40[31];
|
|
volatile reg_mdf_old4cr_t old4cr;
|
|
volatile uint32_t reserve41[31];
|
|
volatile reg_mdf_old5cr_t old5cr;
|
|
volatile uint32_t reserve42[-160];
|
|
volatile reg_mdf_old0thlr_t old0thlr;
|
|
volatile uint32_t reserve43[31];
|
|
volatile reg_mdf_old1thlr_t old1thlr;
|
|
volatile uint32_t reserve44[31];
|
|
volatile reg_mdf_old2thlr_t old2thlr;
|
|
volatile uint32_t reserve45[31];
|
|
volatile reg_mdf_old3thlr_t old3thlr;
|
|
volatile uint32_t reserve46[31];
|
|
volatile reg_mdf_old4thlr_t old4thlr;
|
|
volatile uint32_t reserve47[31];
|
|
volatile reg_mdf_old5thlr_t old5thlr;
|
|
volatile uint32_t reserve48[-160];
|
|
volatile reg_mdf_old0thhr_t old0thhr;
|
|
volatile uint32_t reserve49[31];
|
|
volatile reg_mdf_old1thhr_t old1thhr;
|
|
volatile uint32_t reserve50[31];
|
|
volatile reg_mdf_old2thhr_t old2thhr;
|
|
volatile uint32_t reserve51[31];
|
|
volatile reg_mdf_old3thhr_t old3thhr;
|
|
volatile uint32_t reserve52[31];
|
|
volatile reg_mdf_old4thhr_t old4thhr;
|
|
volatile uint32_t reserve53[31];
|
|
volatile reg_mdf_old5thhr_t old5thhr;
|
|
volatile uint32_t reserve54[-160];
|
|
volatile reg_mdf_dly0cr_t dly0cr;
|
|
volatile uint32_t reserve55[31];
|
|
volatile reg_mdf_dly1cr_t dly1cr;
|
|
volatile uint32_t reserve56[31];
|
|
volatile reg_mdf_dly2cr_t dly2cr;
|
|
volatile uint32_t reserve57[31];
|
|
volatile reg_mdf_dly3cr_t dly3cr;
|
|
volatile uint32_t reserve58[31];
|
|
volatile reg_mdf_dly4cr_t dly4cr;
|
|
volatile uint32_t reserve59[31];
|
|
volatile reg_mdf_dly5cr_t dly5cr;
|
|
volatile uint32_t reserve60[-160];
|
|
volatile reg_mdf_scd0cr_t scd0cr;
|
|
volatile uint32_t reserve61[31];
|
|
volatile reg_mdf_scd1cr_t scd1cr;
|
|
volatile uint32_t reserve62[31];
|
|
volatile reg_mdf_scd2cr_t scd2cr;
|
|
volatile uint32_t reserve63[31];
|
|
volatile reg_mdf_scd3cr_t scd3cr;
|
|
volatile uint32_t reserve64[31];
|
|
volatile reg_mdf_scd4cr_t scd4cr;
|
|
volatile uint32_t reserve65[31];
|
|
volatile reg_mdf_scd5cr_t scd5cr;
|
|
volatile uint32_t reserve66[-160];
|
|
volatile reg_mdf_dflt0ier_t dflt0ier;
|
|
volatile reg_mdf_dflt0isr_t dflt0isr;
|
|
volatile uint32_t reserve67[30];
|
|
volatile reg_mdf_dflt1ier_t dflt1ier;
|
|
volatile uint32_t reserve68[31];
|
|
volatile reg_mdf_dflt2ier_t dflt2ier;
|
|
volatile uint32_t reserve69[31];
|
|
volatile reg_mdf_dflt3ier_t dflt3ier;
|
|
volatile uint32_t reserve70[31];
|
|
volatile reg_mdf_dflt4ier_t dflt4ier;
|
|
volatile uint32_t reserve71[31];
|
|
volatile reg_mdf_dflt5ier_t dflt5ier;
|
|
volatile uint32_t reserve72[-128];
|
|
volatile reg_mdf_dflt1isr_t dflt1isr;
|
|
volatile uint32_t reserve73[31];
|
|
volatile reg_mdf_dflt2isr_t dflt2isr;
|
|
volatile uint32_t reserve74[31];
|
|
volatile reg_mdf_dflt3isr_t dflt3isr;
|
|
volatile uint32_t reserve75[31];
|
|
volatile reg_mdf_dflt4isr_t dflt4isr;
|
|
volatile uint32_t reserve76[31];
|
|
volatile reg_mdf_dflt5isr_t dflt5isr;
|
|
volatile uint32_t reserve77[-160];
|
|
volatile reg_mdf_oec0cr_t oec0cr;
|
|
volatile uint32_t reserve78[31];
|
|
volatile reg_mdf_oec1cr_t oec1cr;
|
|
volatile uint32_t reserve79[31];
|
|
volatile reg_mdf_oec2cr_t oec2cr;
|
|
volatile uint32_t reserve80[31];
|
|
volatile reg_mdf_oec3cr_t oec3cr;
|
|
volatile uint32_t reserve81[31];
|
|
volatile reg_mdf_oec4cr_t oec4cr;
|
|
volatile uint32_t reserve82[31];
|
|
volatile reg_mdf_oec5cr_t oec5cr;
|
|
volatile uint32_t reserve83[-147];
|
|
volatile reg_mdf_snps0dr_t snps0dr;
|
|
volatile uint32_t reserve84[31];
|
|
volatile reg_mdf_snps1dr_t snps1dr;
|
|
volatile uint32_t reserve85[31];
|
|
volatile reg_mdf_snps2dr_t snps2dr;
|
|
volatile uint32_t reserve86[31];
|
|
volatile reg_mdf_snps3dr_t snps3dr;
|
|
volatile uint32_t reserve87[31];
|
|
volatile reg_mdf_snps4dr_t snps4dr;
|
|
volatile uint32_t reserve88[31];
|
|
volatile reg_mdf_snps5dr_t snps5dr;
|
|
volatile uint32_t reserve89[-160];
|
|
volatile reg_mdf_dflt0dr_t dflt0dr;
|
|
volatile uint32_t reserve90[31];
|
|
volatile reg_mdf_dflt1dr_t dflt1dr;
|
|
volatile uint32_t reserve91[31];
|
|
volatile reg_mdf_dflt2dr_t dflt2dr;
|
|
volatile uint32_t reserve92[31];
|
|
volatile reg_mdf_dflt3dr_t dflt3dr;
|
|
volatile uint32_t reserve93[31];
|
|
volatile reg_mdf_dflt4dr_t dflt4dr;
|
|
volatile uint32_t reserve94[31];
|
|
volatile reg_mdf_dflt5dr_t dflt5dr;
|
|
} reg_mdf_t;
|
|
|