202 lines
6.0 KiB
C
Executable File
202 lines
6.0 KiB
C
Executable File
#ifndef REG_DMA_H
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#define REG_DMA_H
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#include <stm32u5xx.h>
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typedef __PACKED_STRUCT {
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uint32_t BR1;
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uint32_t SAR;
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uint32_t DAR;
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uint32_t LLR;
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} list_node_s;
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typedef enum {
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DMA_DATA_WIDTH_8_BITS = 0, // 1 byte
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DMA_DATA_WIDTH_16_BITS = 1, // 2 bytes
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DMA_DATA_WIDTH_32_BITS = 2, // 4 bytes
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} dma_data_width_e;
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typedef enum {
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DMA_ADDR_FIX = 0, // address fixed
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DMA_ADDR_INC = 1, // address increment
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} dma_addr_inc_e;
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typedef enum {
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DMA_TYPE_PREPHERIAL = 0,
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DMA_TYPE_MEMORY = 1,
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} dma_type_e;
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typedef enum {
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DMA_EVENT_TRANSFER_COMPLETE = DMA_CFCR_TCF,
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} dma_event_e;
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typedef enum {
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DMA_ERROR_TRANSFER_ERROR = DMA_CFCR_DTEF,
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} dma_error_e;
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static dma_data_width_e get_max_data_width(dma_data_width_e width, dma_data_width_e width1) {
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if (width > width1)
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return width;
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else
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return width1;
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}
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typedef struct {
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uint32_t seccfgr; // secure configuration register
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uint32_t privcfgr; // priviledged configuration register
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uint32_t rcfglockr; // configuration lock register
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uint32_t misr; // interrupt status register
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uint32_t smisr; // secure interrupt status register
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} reg_dma_s;
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typedef struct {
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uint32_t resv: 16;
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uint32_t lba: 16;
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} reg_dma_lba_t; // channel linked list base address
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typedef struct {
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uint32_t resv: 8;
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uint32_t tcf: 1; // transfer complete flag
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uint32_t htf: 1; // half transfer flag
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uint32_t dtef: 1; // data transfer error flag
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uint32_t ulef: 1; // update linked list error flag
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uint32_t usef: 1; // update secure error flag
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uint32_t suspf: 1; // suspend flag
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uint32_t tof: 1; // timeout flag
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uint32_t resv1: 17;
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} reg_dma_fcr_t; // channel flag clear register
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// tcf htf dtef ulef usef suspf tof
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typedef struct {
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uint32_t idlef: 1; // idle flag
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uint32_t resv: 7;
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uint32_t tcf: 1; // transfer complete flag
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uint32_t htf: 1; // half transfer flag
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uint32_t dtef: 1; // data transfer error flag
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uint32_t ulef: 1; // update linked list error flag
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uint32_t usef: 1; // update secure error flag
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uint32_t suspf: 1; // suspend flag
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uint32_t tof: 1; // timeout flag
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uint32_t resv1: 1;
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uint32_t fifol: 8; // fifo level
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uint32_t resv2: 8;
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} reg_dma_sr_t; // channel status register
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// en 1 reset 1 susp 1 resv 5
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// tcie 1 htie 1 dteie 1 uleie 1 useie 1 suspie 1 toie 1 resv 1
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// lsm 1 lap 1 resv 4 prio 2 resv 8
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typedef struct {
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uint32_t en: 1; // channel enable
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uint32_t reset: 1; // channel reset
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uint32_t susp: 1; // channel suspend
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uint32_t resv: 5;
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uint32_t tcie: 1; // transfer complete interrupt enable
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uint32_t htie: 1; // half transfer interrupt enable
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uint32_t dteie: 1; // data transfer error interrupt enable
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uint32_t uleie: 1; // update linked list error interrupt enable
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uint32_t useie: 1; // update secure error interrupt enable
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uint32_t suspie: 1; // suspend interrupt enable
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uint32_t toie: 1; // timeout interrupt enable
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uint32_t resv1: 1;
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uint32_t lsm: 1; // lock secure mode
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uint32_t lap: 1; // lock access protection
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uint32_t resv2: 4;
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uint32_t prio: 2; // channel priority level
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uint32_t resv3: 8;
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} reg_dma_cr_t; // channel configuration register
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typedef struct {
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uint32_t sdw_log2: 2; // source data width
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uint32_t resv: 1;
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uint32_t sinc: 1; // source increment mode
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uint32_t sbl_1: 6; // source burst length
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uint32_t resv1: 1;
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uint32_t pam: 2; // peripheral address mode
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uint32_t sbx: 1; // source burst length
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uint32_t sap: 1; // source address protection
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uint32_t ssec: 1; // source secure mode
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uint32_t ddw_log2: 2; // destination data width
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uint32_t resv2: 1;
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uint32_t dinc: 1; // destination increment mode
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uint32_t dbl_1: 6; // destination burst length
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uint32_t dbx: 1; // destination burst length
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uint32_t dhx: 1; // destination handshake
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uint32_t resv3: 2;
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uint32_t dap: 1; // destination address protection
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uint32_t dsec: 1; // destination secure mode
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} reg_dma_tr1_t; // channel transfer register
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typedef struct {
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uint32_t reqsel: 7; // request selection
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uint32_t resv: 2;
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uint32_t swreq: 1; // software request
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uint32_t dreq: 1; // DMA request
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uint32_t breq: 1; // block request
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uint32_t resv1: 2;
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uint32_t trigm: 2; // trigger mode
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uint32_t trigsel: 7; // trigger selection
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uint32_t resv2: 1;
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uint32_t trigpol: 2; // trigger polarity
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uint32_t resv3: 4;
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uint32_t tcem: 2; // transfer complete event mode
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} reg_dma_tr2_t; // channel transfer register
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typedef struct {
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uint32_t bndt: 16; // block number
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uint32_t resv: 16;
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} reg_dma_br1_t; // channel block register
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typedef struct {
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uint32_t sao: 13; // source address offset
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uint32_t resv: 3;
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uint32_t dao: 13; // destination address offset
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uint32_t resv1: 3;
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} reg_dma_tr3_t; // channel transfer register
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typedef struct {
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uint32_t brsao: 16; // block repeat source address offset
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uint32_t brdao: 16; // block repeat destination address offset
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} reg_dma_br2_t; // channel block register
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typedef struct {
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uint32_t resv: 2;
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uint32_t la: 14; // linked list address
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uint32_t ull: 1;
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uint32_t resv1: 10;
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uint32_t uda: 1;
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uint32_t usa: 2;
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uint32_t ub1: 1;
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uint32_t ut2: 1;
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uint32_t ut1: 1;
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} reg_dma_llr_t; // channel linked list register
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typedef struct {
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volatile reg_dma_lba_t clbar;
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volatile uint32_t reserved1[2];
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volatile reg_dma_fcr_t cfcr;
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volatile reg_dma_sr_t csr;
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volatile reg_dma_cr_t ccr;
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volatile uint32_t reserved2[10];
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volatile reg_dma_tr1_t ctr1;
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volatile reg_dma_tr2_t ctr2;
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volatile reg_dma_br1_t cbr1;
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volatile uint32_t csar;
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volatile uint32_t cdar;
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volatile reg_dma_tr3_t ctr3;
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volatile reg_dma_br2_t cbr2;
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volatile uint32_t reserved3[8];
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volatile reg_dma_llr_t cllr;
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} reg_dma_ch_s;
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#endif
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