371 lines
17 KiB
C
Executable File
371 lines
17 KiB
C
Executable File
#ifndef LL_UART_H
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#define LL_UART_H
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#include <stm32u575xx.h>
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#include <stm32u5xx.h>
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/// @brief enable uart transmit
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/// @param[in] uart: uart instance
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static inline void ll_uart_enable_tx(USART_TypeDef *uart) { SET_BIT(uart->CR1, USART_CR1_TE); }
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/// @brief enable uart receive
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/// @param[in] uart: uart instance
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static inline void ll_uart_enable_rx(USART_TypeDef *uart) { SET_BIT(uart->CR1, USART_CR1_RE); }
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/// @brief enable uart transmit empty interrupt
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/// @param[in] uart: uart instance
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static inline void ll_uart_enable_tx_empty_interrupt(USART_TypeDef *uart) {
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SET_BIT(uart->CR1, USART_CR1_TXEIE);
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}
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/// @brief disable uart transmit empty interrupt
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/// @param[in] uart: uart instance
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static inline void ll_uart_disable_tx_empty_interrupt(USART_TypeDef *uart) {
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CLEAR_BIT(uart->CR1, USART_CR1_TXEIE);
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}
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/// @brief enable uart transmit complete interrupt
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/// @param[in] uart: uart instance
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static inline void ll_uart_enable_tx_complete_interrupt(USART_TypeDef *uart) {
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SET_BIT(uart->CR1, USART_CR1_TCIE);
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}
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/// @brief disable uart transmit complete interrupt
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/// @param[in] uart: uart instance
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static inline void ll_uart_disable_tx_complete_interrupt(USART_TypeDef *uart) {
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CLEAR_BIT(uart->CR1, USART_CR1_TCIE);
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}
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/// @brief enable uart receive not empty interrupt
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/// @param[in] uart: uart instance
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static inline void ll_uart_enable_rx_interrupt(USART_TypeDef *uart) {
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SET_BIT(uart->CR1, USART_CR1_RXNEIE);
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}
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/// @brief set uart baudrate
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/// @todo: this function may not work correctly if the settings is different.
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static inline void ll_uart_set_baudrate(USART_TypeDef *uart, uint32_t systemclk,
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uint32_t baudrate) {
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uint16_t USARTDIV = 2 * systemclk / baudrate; // calculate USARTDIV for baudrate
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WRITE_REG(uart->BRR, USARTDIV); // set baudrate
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}
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typedef enum {
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LL_UART_DATA_LENGTH_7 = 2, ///< @brief 7 data bits
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LL_UART_DATA_LENGTH_8 = 0, ///< @brief 8 data bits
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LL_UART_DATA_LENGTH_9 = 1, ///< @brief 9 data bits
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} LL_UART_DATA_LENGTH; ///< @brief uart data length
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/// @brief uart set word length
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/// @param[in] uart: uart instance
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/// @param[in] data_length: uart data length
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static inline void ll_uart_set_word_length(USART_TypeDef *uart, LL_UART_DATA_LENGTH data_length) {
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MODIFY_REG(uart->CR1, USART_CR1_M, (data_length&1) << USART_CR1_M_Pos);
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MODIFY_REG(uart->CR2, USART_CR1_M1, (data_length>>1) << USART_CR1_M1_Pos);
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}
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typedef enum {
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LL_UART_STOP_BITS_1 = 0, ///< @brief 1 stop bit
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LL_UART_STOP_BITS_0_5 = 1, ///< @brief 0.5 stop bit
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LL_UART_STOP_BITS_2 = 2, ///< @brief 2 stop bits
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LL_UART_STOP_BITS_1_5 = 3, ///< @brief 1.5 stop bits
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} LL_UART_STOP_BITS; ///< @brief uart stop bits
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/// @brief uart set stop bits
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/// @param[in] uart: uart instance
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/// @param[in] stop_bits: uart stop bits
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static inline void ll_uart_set_stop_bits(USART_TypeDef *uart, LL_UART_STOP_BITS stop_bits) {
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MODIFY_REG(uart->CR2, USART_CR2_STOP, stop_bits << USART_CR2_STOP_Pos);
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}
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typedef enum {
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LL_UART_OVERSAMPLING_16 = 0, ///< @brief 16 over sampling
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LL_UART_OVERSAMPLING_8 = 1, ///< @brief 8 over sampling
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} LL_UART_OVERSAMPLING; ///< @brief uart over sampling
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/// @brief uart set over sampling
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/// @param[in] uart: uart instance
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/// @param[in] over_sampling: uart over sampling
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static inline void ll_uart_set_oversampling(USART_TypeDef *uart,
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LL_UART_OVERSAMPLING over_sampling) {
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MODIFY_REG(uart->CR1, USART_CR1_OVER8, over_sampling << USART_CR1_OVER8_Pos);
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}
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/// @brief uart set parity
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/// @note: this is for Usart parity, in cr1 bit 9 and bit 10.
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/// Bit 9 is parity selection, bit 10 is parity enable.
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typedef enum {
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LL_UART_PARITY_NONE = 0, ///< @brief no parity
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LL_UART_PARITY_EVEN = 2, ///< @brief even parity
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LL_UART_PARITY_ODD = 3, ///< @brief odd parity
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} LL_UART_PARITY;
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/// @brief uart set parity
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/// @param[in] uart: uart instance
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/// @param[in] parity: uart parity
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static inline void ll_uart_set_parity(USART_TypeDef *uart, LL_UART_PARITY parity) {
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MODIFY_REG(uart->CR1, USART_CR1_PCE | USART_CR1_PS, parity << USART_CR1_PS_Pos);
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}
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/// @brief uart enable
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/// @param[in] uart: uart instance
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static inline void ll_uart_enable(USART_TypeDef *uart) { SET_BIT(uart->CR1, USART_CR1_UE); }
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/// @brief uart disable
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/// @param[in] uart: uart instance
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static inline void ll_uart_disable(USART_TypeDef *uart) { CLEAR_BIT(uart->CR1, USART_CR1_UE); }
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//typedef struct {
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// uint32_t ue : 1; ///< @brief USART enable
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// uint32_t uesm : 1; ///< @brief USART enable in Stop mode
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// uint32_t re : 1; ///< @brief Receiver enable
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// uint32_t te : 1; ///< @brief Transmitter enable
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// uint32_t idleie : 1; ///< @brief IDLE interrupt enable
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// uint32_t rxfneie : 1; ///< @brief RX FIFO not empty interrupt enable
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// uint32_t tcie : 1; ///< @brief Transmission complete interrupt enable
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// uint32_t txfneie : 1; ///< @brief TX FIFO not empty interrupt enable
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// uint32_t peie : 1; ///< @brief Parity error interrupt enable
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// uint32_t ps : 1; ///< @brief Parity selection
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// uint32_t pce : 1; ///< @brief Parity control enable
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// uint32_t wake : 1; ///< @brief Receiver wakeup method
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// uint32_t m0 : 1; ///< @brief Word length
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// uint32_t mme : 1; ///< @brief Mute mode enable
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// uint32_t cmie : 1; ///< @brief Character match interrupt enable
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// uint32_t over8 : 1; ///< @brief Oversampling mode
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// uint32_t dedt : 5; ///< @brief Driver Enable deassertion time
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// uint32_t deat : 5; ///< @brief Driver Enable assertion time
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// uint32_t rtoie : 1; ///< @brief Receiver timeout interrupt enable
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// uint32_t eobie : 1; ///< @brief End of Block interrupt enable
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// uint32_t m1 : 1; ///< @brief Word length
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// uint32_t fifo_en : 1; ///< @brief FIFO mode enable
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// uint32_t txfeie : 1; ///< @brief TXFIFO empty interrupt enable
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// uint32_t rxffie : 1; ///< @brief RXFIFO full interrupt enable
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//}reg_uart_cr1_t; // fifo mode enabled
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typedef struct {
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uint32_t ue: 1; ///< @brief USART enable
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uint32_t uesm: 1; ///< @brief USART enable in Stop mode
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uint32_t re: 1; ///< @brief Receiver enable
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uint32_t te: 1; ///< @brief Transmitter enable
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uint32_t idleie: 1; ///< @brief IDLE interrupt enable
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uint32_t rxneie: 1; ///< @brief RX not empty interrupt enable
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uint32_t tcie: 1; ///< @brief Transmission complete interrupt enable
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uint32_t txeie: 1; ///< @brief TX empty interrupt enable
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uint32_t peie: 1; ///< @brief Parity error interrupt enable
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uint32_t ps: 1; ///< @brief Parity selection
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uint32_t pce: 1; ///< @brief Parity control enable
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uint32_t wake: 1; ///< @brief Receiver wakeup method
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uint32_t m0: 1; ///< @brief Word length
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uint32_t mme: 1; ///< @brief Mute mode enable
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uint32_t cmie: 1; ///< @brief Character match interrupt enable
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uint32_t over8: 1; ///< @brief Oversampling mode
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uint32_t dedt: 5; ///< @brief Driver Enable deassertion time
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uint32_t deat: 5; ///< @brief Driver Enable assertion time
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uint32_t rtoie: 1; ///< @brief Receiver timeout interrupt enable
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uint32_t eobie: 1; ///< @brief End of Block interrupt enable
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uint32_t m1: 1; ///< @brief Word length
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uint32_t fifo_en: 1; ///< @brief FIFO mode enable
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uint32_t reserved: 2; ///< @brief reserved
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} reg_uart_cr1_t; // fifo mode disabled
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typedef struct {
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uint32_t slven : 1; ///< @brief Slave mode enabled
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uint32_t reserverd1 : 2; ///< @brief Reserved
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uint32_t dis_nss : 1; ///< @brief Disable slave select (NSS) signal output
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uint32_t addm7 : 1; ///< @brief Address bit 7 (for data frame formats)
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uint32_t lbdl : 1; ///< @brief LIN break detection length
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uint32_t lbdie : 1; ///< @brief LIN break detection interrupt enable
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uint32_t reserverd2 : 1; ///< @brief Reserved
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uint32_t lbcl : 1; ///< @brief Last bit clock pulse
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uint32_t cpha : 1; ///< @brief Clock phase
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uint32_t cpol : 1; ///< @brief Clock polarity
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uint32_t clken : 1; ///< @brief Clock enable
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uint32_t stop : 2; ///< @brief STOP bits
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uint32_t linen : 1; ///< @brief LIN mode enable
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uint32_t swap : 1; ///< @brief Swap TX/RX pins
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uint32_t rxinv : 1; ///< @brief RX pin active level inversion
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uint32_t txinv : 1; ///< @brief TX pin active level inversion
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uint32_t datainv : 1; ///< @brief Binary data inversion
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uint32_t msbfirst : 1; ///< @brief Most significant bit first
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uint32_t abren : 1; ///< @brief Auto baud rate enable
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uint32_t abrmod : 2; ///< @brief Auto baud rate mode
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uint32_t rtoen : 1; ///< @brief Receiver timeout enable
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uint32_t add : 8; ///< @brief Address of the USART node
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}reg_uart_cr2_t;
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typedef struct {
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uint32_t eie : 1; ///< @brief Error interrupt enable
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uint32_t iren : 1; ///< @brief IrDA mode enable
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uint32_t irlp : 1; ///< @brief IrDA low-power
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uint32_t hdsel : 1; ///< @brief Half-duplex selection
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uint32_t nack : 1; ///< @brief Smartcard NACK enable
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uint32_t scen : 1; ///< @brief Smartcard mode enable
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uint32_t dmar : 1; ///< @brief DMA enable receiver
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uint32_t dmat : 1; ///< @brief DMA enable transmitter
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uint32_t rtse : 1; ///< @brief RTS enable
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uint32_t ctse : 1; ///< @brief CTS enable
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uint32_t ctsie : 1; ///< @brief CTS interrupt enable
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uint32_t onebit : 1; ///< @brief One sample bit method enable
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uint32_t ovrdis : 1; ///< @brief Overrun Disable
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uint32_t ddre : 1; ///< @brief DMA Disable on Reception Error
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uint32_t dem : 1; ///< @brief Driver enable mode
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uint32_t dep : 1; ///< @brief Driver enable polarity selection
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uint32_t reserverd1 : 1; ///< @brief Reserved
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uint32_t scarcnt : 3; ///< @brief Smartcard auto-retry count
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uint32_t reserverd2 : 3; ///< @brief Reserved
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uint32_t txftie : 1; ///< @brief TXFIFO threshold interrupt enable
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uint32_t tcbgtie : 1; ///< @brief Transmission complete before guard time interrupt enable
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uint32_t rxftcfg : 3; ///< @brief RXFIFO threshold configuration
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uint32_t rxftie : 1; ///< @brief RXFIFO threshold interrupt enable
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uint32_t txftcfg : 3; ///< @brief TXFIFO threshold configuration
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}reg_uart_cr3_t;
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typedef struct {
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uint32_t brr: 16; ///< @brief BRR[15:0] = USARTDIV
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uint32_t reserverd1: 16; ///< @brief Reserved
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}reg_uart_brr_t;
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typedef struct {
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uint32_t psc: 8; ///< @brief PSC[7:0] = USART prescaler
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uint32_t gt: 8; ///< @brief GT[7:0] = Guard time value
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uint32_t reserverd1: 16; ///< @brief Reserved
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}reg_uart_gtpr_t;
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typedef struct {
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uint32_t rto: 24; ///< @brief Receiver timeout value
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uint32_t blen: 8; ///< @brief Block length
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}reg_uart_rtor_t;
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typedef struct {
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uint32_t abrrq: 1; ///< @brief Auto baud rate request
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uint32_t sbkrq: 1; ///< @brief Send break request
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uint32_t mmrq: 1; ///< @brief Mute mode request
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uint32_t rxfrq: 1; ///< @brief Receive data flush request
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uint32_t txfrq: 1; ///< @brief Transmit data flush request
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uint32_t reserverd1: 27; ///< @brief Reserved
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}reg_uart_rqr_t;
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//typedef struct {
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// uint32_t pe: 1; ///< @brief Parity error
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// uint32_t fe: 1; ///< @brief Framing error
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// uint32_t ne: 1; ///< @brief Noise detected flag
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// uint32_t ore: 1; ///< @brief Overrun error
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// uint32_t idle: 1; ///< @brief IDLE line detected
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// uint32_t rxfne: 1; ///< @brief Read data register not empty
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// uint32_t tc: 1; ///< @brief Transmission complete
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// uint32_t txfnf: 1; ///< @brief TXFIFO not full
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// uint32_t lbdf: 1; ///< @brief LIN break detection flag
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// uint32_t ctsif: 1; ///< @brief CTS interrupt flag
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// uint32_t cts: 1; ///< @brief CTS flag
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// uint32_t rtof: 1; ///< @brief Receiver timeout
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// uint32_t eobf: 1; ///< @brief End of block flag
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// uint32_t udr: 1; ///< @brief SPI slave underrun error flag
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// uint32_t abre: 1; ///< @brief Auto baud rate error
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// uint32_t abrf: 1; ///< @brief Auto baud rate flag
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// uint32_t busy: 1; ///< @brief Busy flag
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// uint32_t cmf: 1; ///< @brief Character match flag
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// uint32_t sbkf: 1; ///< @brief Send break flag
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// uint32_t rwu: 1; ///< @brief Receiver wakeup from Mute mode
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// uint32_t reserverd1: 1; ///< @brief Reserved
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// uint32_t teack: 1; ///< @brief Transmit enable acknowledge flag
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// uint32_t reack: 1; ///< @brief Receive enable acknowledge flag
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// uint32_t txfe: 1; ///< @brief TXFIFO empty
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// uint32_t rxff: 1; ///< @brief RXFIFO full
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// uint32_t tcbgt: 1; ///< @brief Transmission complete before guard time completion
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// uint32_t rxft: 1; ///< @brief RXFIFO threshold flag
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// uint32_t txft: 1; ///< @brief TXFIFO threshold flag
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// uint32_t reserverd2: 4; ///< @brief Reserved
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//}reg_uart_isr_t; // fifo mode enabled
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typedef struct {
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uint32_t pe: 1; ///< @brief Parity error
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uint32_t fe: 1; ///< @brief Framing error
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uint32_t ne: 1; ///< @brief Noise detected flag
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uint32_t ore: 1; ///< @brief Overrun error
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uint32_t idle: 1; ///< @brief IDLE line detected
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uint32_t rxne: 1; ///< @brief Read data register not empty
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uint32_t tc: 1; ///< @brief Transmission complete
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uint32_t txe: 1; ///< @brief Transmit data register empty
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uint32_t lbdf: 1; ///< @brief LIN break detection flag
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uint32_t ctsif: 1; ///< @brief CTS interrupt flag
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uint32_t cts: 1; ///< @brief CTS flag
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uint32_t rtof: 1; ///< @brief Receiver timeout
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uint32_t eobf: 1; ///< @brief End of block flag
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uint32_t udr: 1; ///< @brief SPI slave underrun error flag
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uint32_t abre: 1; ///< @brief Auto baud rate error
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uint32_t abrf: 1; ///< @brief Auto baud rate flag
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uint32_t busy: 1; ///< @brief Busy flag
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uint32_t cmf: 1; ///< @brief Character match flag
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uint32_t sbkf: 1; ///< @brief Send break flag
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uint32_t rwu: 1; ///< @brief Receiver wakeup from Mute mode
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uint32_t reserverd1: 1; ///< @brief Reserved
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uint32_t teack: 1; ///< @brief Transmit enable acknowledge flag
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uint32_t reack: 1; ///< @brief Receive enable acknowledge flag
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uint32_t reserverd2: 2; ///< @brief Reserved
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uint32_t tcbgt: 1; ///< @brief Transmission complete before guard time completion
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uint32_t reserverd3: 6; ///< @brief Reserved
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}reg_uart_isr_t; // fifo mode disabled
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typedef struct {
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uint32_t pecf: 1; ///< @brief Parity error clear flag
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uint32_t fecf: 1; ///< @brief Framing error clear flag
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uint32_t necf: 1; ///< @brief Noise detected clear flag
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uint32_t orecf: 1; ///< @brief Overrun error clear flag
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uint32_t idlecf: 1; ///< @brief IDLE line detected clear flag
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uint32_t txfecf: 1; ///< @brief TXFIFO empty clear flag
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uint32_t tccf: 1; ///< @brief Transmission complete clear flag
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uint32_t tcbgtcf: 1; ///< @brief Transmission complete before guard time clear flag
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uint32_t lbdcf: 1; ///< @brief LIN break detection clear flag
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uint32_t ctscf: 1; ///< @brief CTS clear flag
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uint32_t reserverd1: 1; ///< @brief Reserved
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uint32_t rtofcf: 1; ///< @brief Receiver timeout clear flag
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uint32_t eobcf: 1; ///< @brief End of block clear flag
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uint32_t udrcf: 1; ///< @brief SPI slave underrun clear flag
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uint32_t reserverd2: 1; ///< @brief Reserved
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uint32_t cmcf: 1; ///< @brief Character match clear flag
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uint32_t reserverd3: 14; ///< @brief Reserved
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}reg_uart_icr_t;
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typedef struct {
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uint32_t rd: 8; ///< @brief Receive data value
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uint32_t reserverd1: 24; ///< @brief Reserved
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}reg_uart_rdr_t;
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typedef struct {
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uint32_t tdr: 8; ///< @brief Transmit data value
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uint32_t reserverd1: 24; ///< @brief Reserved
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}reg_uart_tdr_t;
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typedef struct {
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uint32_t prescaler: 4; ///< @brief Prescaler value
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uint32_t reserverd1: 28; ///< @brief Reserved
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}reg_uart_presc_t;
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typedef struct {
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uint32_t tdn: 16;
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uint32_t trigpol: 1;
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uint32_t trigen: 1;
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uint32_t idledis: 1;
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uint32_t trigsel: 4;
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uint32_t reserverd1: 9;
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}reg_uart_autocr_t;
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typedef struct {
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reg_uart_cr1_t cr1; ///< @brief Control register 1
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reg_uart_cr2_t cr2; ///< @brief Control register 2
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reg_uart_cr3_t cr3; ///< @brief Control register 3
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reg_uart_brr_t brr; ///< @brief Baud rate register
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reg_uart_gtpr_t gtpr; ///< @brief Guard time and prescaler register
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reg_uart_rtor_t rtor; ///< @brief Receiver timeout register
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reg_uart_rqr_t rqr; ///< @brief Request register
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reg_uart_isr_t isr; ///< @brief Interrupt and status register
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reg_uart_icr_t icr; ///< @brief Interrupt flag clear register
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reg_uart_rdr_t rdr; ///< @brief Receive data register
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reg_uart_tdr_t tdr; ///< @brief Transmit data register
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reg_uart_presc_t presc; ///< @brief Prescaler register
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reg_uart_autocr_t autocr; ///< @brief Auto baud rate control register
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}reg_uart_t;
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#endif // LL_UART_H
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