Eli Orona e3a6144275

Modify TIM(2)SW Clock Selection to use the new PLL1_P_MUL_2 name

2024-02-25 16:01:15 -08:00

..

dmamux

Rename G4 DMAMUX DACn_CHANNELm to DACn_CHm to match all other families.

2024-01-05 00:25:14 +00:00

extra/family

opamp: add other pins for f3 and g4

2023-10-03 20:38:38 -05:00

registers

Modify TIM(2)SW Clock Selection to use the new PLL1_P_MUL_2 name

2024-02-25 16:01:15 -08:00

header_map.yaml

Update headers.

2023-12-08 23:19:12 +01:00