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Modify TIM(2)SW Clock Selection to use the new PLL1_P_MUL_2 name

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Eli Orona 2024-02-25 16:01:15 -08:00 committed by GitHub
parent d492f504e7
commit e3a6144275
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1 changed files with 2 additions and 2 deletions
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data/registers/rcc_f3v3.yaml
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@ -1191,7 +1191,7 @@ enum/TIM2SW:
- name: PCLK1_TIM
description: PCLK2 clock (doubled frequency when prescaled)
value: 0
- name: PLL1_P
- name: PLL1_P_MUL_2
description: PLL vco output (running up to 144 MHz)
value: 1
enum/TIMSW:
@ -1200,7 +1200,7 @@ enum/TIMSW:
- name: PCLK2_TIM
description: PCLK2 clock (doubled frequency when prescaled)
value: 0
- name: PLL1_P
- name: PLL1_P_MUL_2
description: PLL vco output (running up to 144 MHz)
value: 1
enum/USART1SW: