From e3a61442754eef58eea84edaececc0478365c10f Mon Sep 17 00:00:00 2001 From: Eli Orona Date: Sun, 25 Feb 2024 16:01:15 -0800 Subject: [PATCH] Modify TIM(2)SW Clock Selection to use the new PLL1_P_MUL_2 name --- data/registers/rcc_f3v3.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/data/registers/rcc_f3v3.yaml b/data/registers/rcc_f3v3.yaml index 77b1581..f3c378b 100644 --- a/data/registers/rcc_f3v3.yaml +++ b/data/registers/rcc_f3v3.yaml @@ -1191,7 +1191,7 @@ enum/TIM2SW: - name: PCLK1_TIM description: PCLK2 clock (doubled frequency when prescaled) value: 0 - - name: PLL1_P + - name: PLL1_P_MUL_2 description: PLL vco output (running up to 144 MHz) value: 1 enum/TIMSW: @@ -1200,7 +1200,7 @@ enum/TIMSW: - name: PCLK2_TIM description: PCLK2 clock (doubled frequency when prescaled) value: 0 - - name: PLL1_P + - name: PLL1_P_MUL_2 description: PLL vco output (running up to 144 MHz) value: 1 enum/USART1SW: