2382 lines
54 KiB
YAML
2382 lines
54 KiB
YAML
block/RCC:
|
|
description: Reset and clock control
|
|
items:
|
|
- name: CR
|
|
description: Clock control register
|
|
byte_offset: 0
|
|
fieldset: CR
|
|
- name: ICSCR
|
|
description: Internal clock sources calibration register
|
|
byte_offset: 4
|
|
fieldset: ICSCR
|
|
- name: CFGR
|
|
description: Clock configuration register
|
|
byte_offset: 8
|
|
fieldset: CFGR
|
|
- name: PLLCFGR
|
|
description: PLLSYS configuration register
|
|
byte_offset: 12
|
|
fieldset: PLLCFGR
|
|
- name: PLLSAI1CFGR
|
|
description: PLLSAI1 configuration register
|
|
byte_offset: 16
|
|
fieldset: PLLSAI1CFGR
|
|
- name: CIER
|
|
description: Clock interrupt enable register
|
|
byte_offset: 24
|
|
fieldset: CIER
|
|
- name: CIFR
|
|
description: Clock interrupt flag register
|
|
byte_offset: 28
|
|
access: Read
|
|
fieldset: CIFR
|
|
- name: CICR
|
|
description: Clock interrupt clear register
|
|
byte_offset: 32
|
|
access: Write
|
|
fieldset: CICR
|
|
- name: SMPSCR
|
|
description: Step Down converter control register
|
|
byte_offset: 36
|
|
fieldset: SMPSCR
|
|
- name: AHB1RSTR
|
|
description: AHB1 peripheral reset register
|
|
byte_offset: 40
|
|
fieldset: AHB1RSTR
|
|
- name: AHB2RSTR
|
|
description: AHB2 peripheral reset register
|
|
byte_offset: 44
|
|
fieldset: AHB2RSTR
|
|
- name: AHB3RSTR
|
|
description: AHB3 peripheral reset register
|
|
byte_offset: 48
|
|
fieldset: AHB3RSTR
|
|
- name: APB1RSTR1
|
|
description: APB1 peripheral reset register 1
|
|
byte_offset: 56
|
|
fieldset: APB1RSTR1
|
|
- name: APB1RSTR2
|
|
description: APB1 peripheral reset register 2
|
|
byte_offset: 60
|
|
fieldset: APB1RSTR2
|
|
- name: APB2RSTR
|
|
description: APB2 peripheral reset register
|
|
byte_offset: 64
|
|
fieldset: APB2RSTR
|
|
- name: APB3RSTR
|
|
description: APB3 peripheral reset register
|
|
byte_offset: 68
|
|
fieldset: APB3RSTR
|
|
- name: AHB1ENR
|
|
description: AHB1 peripheral clock enable register
|
|
byte_offset: 72
|
|
fieldset: AHB1ENR
|
|
- name: AHB2ENR
|
|
description: AHB2 peripheral clock enable register
|
|
byte_offset: 76
|
|
fieldset: AHB2ENR
|
|
- name: AHB3ENR
|
|
description: AHB3 peripheral clock enable register
|
|
byte_offset: 80
|
|
fieldset: AHB3ENR
|
|
- name: APB1ENR1
|
|
description: APB1ENR1
|
|
byte_offset: 88
|
|
fieldset: APB1ENR1
|
|
- name: APB1ENR2
|
|
description: APB1 peripheral clock enable register 2
|
|
byte_offset: 92
|
|
fieldset: APB1ENR2
|
|
- name: APB2ENR
|
|
description: APB2ENR
|
|
byte_offset: 96
|
|
fieldset: APB2ENR
|
|
- name: AHB1SMENR
|
|
description: AHB1 peripheral clocks enable in Sleep and Stop modes register
|
|
byte_offset: 104
|
|
fieldset: AHB1SMENR
|
|
- name: AHB2SMENR
|
|
description: AHB2 peripheral clocks enable in Sleep and Stop modes register
|
|
byte_offset: 108
|
|
fieldset: AHB2SMENR
|
|
- name: AHB3SMENR
|
|
description: AHB3 peripheral clocks enable in Sleep and Stop modes register
|
|
byte_offset: 112
|
|
fieldset: AHB3SMENR
|
|
- name: APB1SMENR1
|
|
description: APB1SMENR1
|
|
byte_offset: 120
|
|
fieldset: APB1SMENR1
|
|
- name: APB1SMENR2
|
|
description: APB1 peripheral clocks enable in Sleep and Stop modes register 2
|
|
byte_offset: 124
|
|
fieldset: APB1SMENR2
|
|
- name: APB2SMENR
|
|
description: APB2SMENR
|
|
byte_offset: 128
|
|
fieldset: APB2SMENR
|
|
- name: CCIPR
|
|
description: CCIPR
|
|
byte_offset: 136
|
|
fieldset: CCIPR
|
|
- name: BDCR
|
|
description: BDCR
|
|
byte_offset: 144
|
|
fieldset: BDCR
|
|
- name: CSR
|
|
description: CSR
|
|
byte_offset: 148
|
|
fieldset: CSR
|
|
- name: CRRCR
|
|
description: Clock recovery RC register
|
|
byte_offset: 152
|
|
fieldset: CRRCR
|
|
- name: HSECR
|
|
description: Clock HSE register
|
|
byte_offset: 156
|
|
fieldset: HSECR
|
|
- name: EXTCFGR
|
|
description: Extended clock recovery register
|
|
byte_offset: 264
|
|
fieldset: EXTCFGR
|
|
- name: C2AHB1ENR
|
|
description: CPU2 AHB1 peripheral clock enable register
|
|
byte_offset: 328
|
|
fieldset: C2AHB1ENR
|
|
- name: C2AHB2ENR
|
|
description: CPU2 AHB2 peripheral clock enable register
|
|
byte_offset: 332
|
|
fieldset: C2AHB2ENR
|
|
- name: C2AHB3ENR
|
|
description: CPU2 AHB3 peripheral clock enable register
|
|
byte_offset: 336
|
|
fieldset: C2AHB3ENR
|
|
- name: C2APB1ENR1
|
|
description: CPU2 APB1ENR1
|
|
byte_offset: 344
|
|
fieldset: C2APB1ENR1
|
|
- name: C2APB1ENR2
|
|
description: CPU2 APB1 peripheral clock enable register 2
|
|
byte_offset: 348
|
|
fieldset: C2APB1ENR2
|
|
- name: C2APB2ENR
|
|
description: CPU2 APB2ENR
|
|
byte_offset: 352
|
|
fieldset: C2APB2ENR
|
|
- name: C2APB3ENR
|
|
description: CPU2 APB3ENR
|
|
byte_offset: 356
|
|
fieldset: C2APB3ENR
|
|
- name: C2AHB1SMENR
|
|
description: CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register
|
|
byte_offset: 360
|
|
fieldset: C2AHB1SMENR
|
|
- name: C2AHB2SMENR
|
|
description: CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register
|
|
byte_offset: 364
|
|
fieldset: C2AHB2SMENR
|
|
- name: C2AHB3SMENR
|
|
description: CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register
|
|
byte_offset: 368
|
|
fieldset: C2AHB3SMENR
|
|
- name: C2APB1SMENR1
|
|
description: CPU2 APB1SMENR1
|
|
byte_offset: 376
|
|
fieldset: C2APB1SMENR1
|
|
- name: C2APB1SMENR2
|
|
description: CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2
|
|
byte_offset: 380
|
|
fieldset: C2APB1SMENR2
|
|
- name: C2APB2SMENR
|
|
description: CPU2 APB2SMENR
|
|
byte_offset: 384
|
|
fieldset: C2APB2SMENR
|
|
- name: C2APB3SMENR
|
|
description: CPU2 APB3SMENR
|
|
byte_offset: 388
|
|
fieldset: C2APB3SMENR
|
|
fieldset/AHB1ENR:
|
|
description: AHB1 peripheral clock enable register
|
|
fields:
|
|
- name: DMA1EN
|
|
description: DMA1 clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: DMA2EN
|
|
description: DMA2 clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: DMAMUX1EN
|
|
description: DMAMUX clock enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: CRCEN
|
|
description: CPU1 CRC clock enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: TSCEN
|
|
description: Touch Sensing Controller clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/AHB1RSTR:
|
|
description: AHB1 peripheral reset register
|
|
fields:
|
|
- name: DMA1RST
|
|
description: DMA1 reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: DMA2RST
|
|
description: DMA2 reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: DMAMUX1RST
|
|
description: DMAMUX reset
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: CRCRST
|
|
description: CRC reset
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: TSCRST
|
|
description: Touch Sensing Controller reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/AHB1SMENR:
|
|
description: AHB1 peripheral clocks enable in Sleep and Stop modes register
|
|
fields:
|
|
- name: DMA1SMEN
|
|
description: CPU1 DMA1 clocks enable during Sleep and Stop modes
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: DMA2SMEN
|
|
description: CPU1 DMA2 clocks enable during Sleep and Stop modes
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: DMAMUX1SMEN
|
|
description: CPU1 DMAMUX clocks enable during Sleep and Stop modes
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: SRAM1SMEN
|
|
description: CPU1 SRAM1 interface clocks enable during Sleep and Stop modes
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: CRCSMEN
|
|
description: CPU1 CRCSMEN
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: TSCSMEN
|
|
description: CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/AHB2ENR:
|
|
description: AHB2 peripheral clock enable register
|
|
fields:
|
|
- name: GPIOAEN
|
|
description: IO port A clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBEN
|
|
description: IO port B clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCEN
|
|
description: IO port C clock enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODEN
|
|
description: IO port D clock enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOEEN
|
|
description: IO port E clock enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: GPIOHEN
|
|
description: IO port H clock enable
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: ADCEN
|
|
description: ADC clock enable
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: AES1EN
|
|
description: AES1 accelerator clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/AHB2RSTR:
|
|
description: AHB2 peripheral reset register
|
|
fields:
|
|
- name: GPIOARST
|
|
description: IO port A reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBRST
|
|
description: IO port B reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCRST
|
|
description: IO port C reset
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODRST
|
|
description: IO port D reset
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOERST
|
|
description: IO port E reset
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: GPIOHRST
|
|
description: IO port H reset
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: ADCRST
|
|
description: ADC reset
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: AES1RST
|
|
description: AES1 hardware accelerator reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/AHB2SMENR:
|
|
description: AHB2 peripheral clocks enable in Sleep and Stop modes register
|
|
fields:
|
|
- name: GPIOASMEN
|
|
description: CPU1 IO port A clocks enable during Sleep and Stop modes
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBSMEN
|
|
description: CPU1 IO port B clocks enable during Sleep and Stop modes
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCSMEN
|
|
description: CPU1 IO port C clocks enable during Sleep and Stop modes
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODSMEN
|
|
description: CPU1 IO port D clocks enable during Sleep and Stop modes
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOESMEN
|
|
description: CPU1 IO port E clocks enable during Sleep and Stop modes
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: GPIOHSMEN
|
|
description: CPU1 IO port H clocks enable during Sleep and Stop modes
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: ADCFSSMEN
|
|
description: CPU1 ADC clocks enable during Sleep and Stop modes
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: AES1SMEN
|
|
description: CPU1 AES1 accelerator clocks enable during Sleep and Stop modes
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/AHB3ENR:
|
|
description: AHB3 peripheral clock enable register
|
|
fields:
|
|
- name: QUADSPIEN
|
|
description: QUADSPIEN
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: PKAEN
|
|
description: PKAEN
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: AES2EN
|
|
description: AES2EN
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: RNGEN
|
|
description: RNGEN
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: HSEMEN
|
|
description: HSEMEN
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: IPCCEN
|
|
description: IPCCEN
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: FLASHEN
|
|
description: FLASHEN
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/AHB3RSTR:
|
|
description: AHB3 peripheral reset register
|
|
fields:
|
|
- name: QSPIRST
|
|
description: Quad SPI memory interface reset
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: PKARST
|
|
description: PKA interface reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: AES2RST
|
|
description: AES2 interface reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: RNGRST
|
|
description: RNG interface reset
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: HSEMRST
|
|
description: HSEM interface reset
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: IPCCRST
|
|
description: IPCC interface reset
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: FLASHRST
|
|
description: Flash interface reset
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/AHB3SMENR:
|
|
description: AHB3 peripheral clocks enable in Sleep and Stop modes register
|
|
fields:
|
|
- name: QSPISMEN
|
|
description: QSPISMEN
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: PKASMEN
|
|
description: PKA accelerator clocks enable during CPU1 sleep mode
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: AES2SMEN
|
|
description: AES2 accelerator clocks enable during CPU1 sleep mode
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: RNGSMEN
|
|
description: True RNG clocks enable during CPU1 sleep mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SRAM2SMEN
|
|
description: SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: FLASHSMEN
|
|
description: Flash interface clocks enable during CPU1 sleep mode
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/APB1ENR1:
|
|
description: APB1ENR1
|
|
fields:
|
|
- name: TIM2EN
|
|
description: CPU1 TIM2 timer clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LCDEN
|
|
description: CPU1 LCD clock enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: RTCAPBEN
|
|
description: CPU1 RTC APB clock enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: WWDGEN
|
|
description: CPU1 Window watchdog clock enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI2EN
|
|
description: CPU1 SPI2 clock enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: I2C1EN
|
|
description: CPU1 I2C1 clock enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C3EN
|
|
description: CPU1 I2C3 clock enable
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CRSEN
|
|
description: CPU1 CRS clock enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: USBEN
|
|
description: CPU1 USB clock enable
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: LPTIM1EN
|
|
description: CPU1 Low power timer 1 clock enable
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/APB1ENR2:
|
|
description: APB1 peripheral clock enable register 2
|
|
fields:
|
|
- name: LPUART1EN
|
|
description: CPU1 Low power UART 1 clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LPTIM2EN
|
|
description: CPU1 LPTIM2EN
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
fieldset/APB1RSTR1:
|
|
description: APB1 peripheral reset register 1
|
|
fields:
|
|
- name: TIM2RST
|
|
description: TIM2 timer reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LCDRST
|
|
description: LCD interface reset
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: SPI2RST
|
|
description: SPI2 reset
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: I2C1RST
|
|
description: I2C1 reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C3RST
|
|
description: I2C3 reset
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CRSRST
|
|
description: CRS reset
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: USBRST
|
|
description: USB FS reset
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: LPTIM1RST
|
|
description: Low Power Timer 1 reset
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/APB1RSTR2:
|
|
description: APB1 peripheral reset register 2
|
|
fields:
|
|
- name: LPUART1RST
|
|
description: Low-power UART 1 reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LPTIM2RST
|
|
description: Low-power timer 2 reset
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
fieldset/APB1SMENR1:
|
|
description: APB1SMENR1
|
|
fields:
|
|
- name: TIM2SMEN
|
|
description: TIM2 timer clocks enable during CPU1 Sleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LCDSMEN
|
|
description: LCD clocks enable during CPU1 Sleep mode
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: RTCAPBSMEN
|
|
description: RTC APB clocks enable during CPU1 Sleep mode
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: WWDGSMEN
|
|
description: Window watchdog clocks enable during CPU1 Sleep mode
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI2SMEN
|
|
description: SPI2 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: I2C1SMEN
|
|
description: I2C1 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C3SMEN
|
|
description: I2C3 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CRSMEN
|
|
description: CRS clocks enable during CPU1 Sleep mode
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: USBSMEN
|
|
description: USB FS clocks enable during CPU1 Sleep mode
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: LPTIM1SMEN
|
|
description: Low power timer 1 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/APB1SMENR2:
|
|
description: APB1 peripheral clocks enable in Sleep and Stop modes register 2
|
|
fields:
|
|
- name: LPUART1SMEN
|
|
description: Low power UART 1 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LPTIM2SMEN
|
|
description: Low power timer 2 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
fieldset/APB2ENR:
|
|
description: APB2ENR
|
|
fields:
|
|
- name: TIM1EN
|
|
description: CPU1 TIM1 timer clock enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1EN
|
|
description: CPU1 SPI1 clock enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1EN
|
|
description: CPU1 USART1clock enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16EN
|
|
description: CPU1 TIM16 timer clock enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17EN
|
|
description: CPU1 TIM17 timer clock enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SAI1EN
|
|
description: CPU1 SAI1 clock enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
fieldset/APB2RSTR:
|
|
description: APB2 peripheral reset register
|
|
fields:
|
|
- name: TIM1RST
|
|
description: TIM1 timer reset
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1RST
|
|
description: SPI1 reset
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1RST
|
|
description: USART1 reset
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16RST
|
|
description: TIM16 timer reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17RST
|
|
description: TIM17 timer reset
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SAI1RST
|
|
description: Serial audio interface 1 (SAI1) reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
fieldset/APB2SMENR:
|
|
description: APB2SMENR
|
|
fields:
|
|
- name: TIM1SMEN
|
|
description: TIM1 timer clocks enable during CPU1 Sleep mode
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1SMEN
|
|
description: SPI1 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1SMEN
|
|
description: USART1clocks enable during CPU1 Sleep mode
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16SMEN
|
|
description: TIM16 timer clocks enable during CPU1 Sleep mode
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17SMEN
|
|
description: TIM17 timer clocks enable during CPU1 Sleep mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SAI1SMEN
|
|
description: SAI1 clocks enable during CPU1 Sleep mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
fieldset/APB3RSTR:
|
|
description: APB3 peripheral reset register
|
|
fields:
|
|
- name: RFRST
|
|
description: Radio system BLE reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
fieldset/BDCR:
|
|
description: BDCR
|
|
fields:
|
|
- name: LSEON
|
|
description: LSE oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDY
|
|
description: LSE oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LSEBYP
|
|
description: LSE oscillator bypass
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: LSEDRV
|
|
description: SE oscillator drive capability
|
|
bit_offset: 3
|
|
bit_size: 2
|
|
enum: LSEDRV
|
|
- name: LSECSSON
|
|
description: LSECSSON
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LSECSSD_
|
|
description: CSS on LSE failure detection
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: RTCSEL
|
|
description: RTC clock source selection
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
enum: RTCSEL
|
|
- name: RTCEN
|
|
description: RTC clock enable
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: BDRST
|
|
description: Backup domain software reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: LSCOEN
|
|
description: Low speed clock output enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: LSCOSEL
|
|
description: Low speed clock output selection
|
|
bit_offset: 25
|
|
bit_size: 2
|
|
fieldset/C2AHB1ENR:
|
|
description: CPU2 AHB1 peripheral clock enable register
|
|
fields:
|
|
- name: DMA1EN
|
|
description: CPU2 DMA1 clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: DMA2EN
|
|
description: CPU2 DMA2 clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: DMAMUX1EN
|
|
description: CPU2 DMAMUX clock enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: SRAM1EN
|
|
description: CPU2 SRAM1 clock enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: CRCEN
|
|
description: CPU2 CRC clock enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: TSCEN
|
|
description: CPU2 Touch Sensing Controller clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/C2AHB1SMENR:
|
|
description: CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register
|
|
fields:
|
|
- name: DMA1SMEN
|
|
description: CPU2 DMA1 clocks enable during Sleep and Stop modes
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: DMA2SMEN
|
|
description: CPU2 DMA2 clocks enable during Sleep and Stop modes
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: DMAMUX1SMEN
|
|
description: CPU2 DMAMUX clocks enable during Sleep and Stop modes
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: SRAM1SMEN
|
|
description: SRAM1 interface clock enable during CPU1 CSleep mode
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: CRCSMEN
|
|
description: CPU2 CRCSMEN
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: TSCSMEN
|
|
description: CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/C2AHB2ENR:
|
|
description: CPU2 AHB2 peripheral clock enable register
|
|
fields:
|
|
- name: GPIOAEN
|
|
description: CPU2 IO port A clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBEN
|
|
description: CPU2 IO port B clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCEN
|
|
description: CPU2 IO port C clock enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODEN
|
|
description: CPU2 IO port D clock enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOEEN
|
|
description: CPU2 IO port E clock enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: GPIOHEN
|
|
description: CPU2 IO port H clock enable
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: ADCEN
|
|
description: CPU2 ADC clock enable
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: AES1EN
|
|
description: CPU2 AES1 accelerator clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/C2AHB2SMENR:
|
|
description: CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register
|
|
fields:
|
|
- name: GPIOASMEN
|
|
description: CPU2 IO port A clocks enable during Sleep and Stop modes
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: GPIOBSMEN
|
|
description: CPU2 IO port B clocks enable during Sleep and Stop modes
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: GPIOCSMEN
|
|
description: CPU2 IO port C clocks enable during Sleep and Stop modes
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: GPIODSMEN
|
|
description: CPU2 IO port D clocks enable during Sleep and Stop modes
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: GPIOESMEN
|
|
description: CPU2 IO port E clocks enable during Sleep and Stop modes
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: GPIOHSMEN
|
|
description: CPU2 IO port H clocks enable during Sleep and Stop modes
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: ADCFSSMEN
|
|
description: CPU2 ADC clocks enable during Sleep and Stop modes
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: AES1SMEN
|
|
description: CPU2 AES1 accelerator clocks enable during Sleep and Stop modes
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
fieldset/C2AHB3ENR:
|
|
description: CPU2 AHB3 peripheral clock enable register
|
|
fields:
|
|
- name: PKAEN
|
|
description: CPU2 PKAEN
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: AES2EN
|
|
description: CPU2 AES2EN
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: RNGEN
|
|
description: CPU2 RNGEN
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: HSEMEN
|
|
description: CPU2 HSEMEN
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: IPCCEN
|
|
description: CPU2 IPCCEN
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: FLASHEN
|
|
description: CPU2 FLASHEN
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/C2AHB3SMENR:
|
|
description: CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register
|
|
fields:
|
|
- name: PKASMEN
|
|
description: PKA accelerator clocks enable during CPU2 sleep modes
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: AES2SMEN
|
|
description: AES2 accelerator clocks enable during CPU2 sleep modes
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: RNGSMEN
|
|
description: True RNG clocks enable during CPU2 sleep modes
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SRAM2SMEN
|
|
description: SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: FLASHSMEN
|
|
description: Flash interface clocks enable during CPU2 sleep modes
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/C2APB1ENR1:
|
|
description: CPU2 APB1ENR1
|
|
fields:
|
|
- name: TIM2EN
|
|
description: CPU2 TIM2 timer clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LCDEN
|
|
description: CPU2 LCD clock enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: RTCAPBEN
|
|
description: CPU2 RTC APB clock enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: SPI2EN
|
|
description: CPU2 SPI2 clock enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: I2C1EN
|
|
description: CPU2 I2C1 clock enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C3EN
|
|
description: CPU2 I2C3 clock enable
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CRSEN
|
|
description: CPU2 CRS clock enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: USBEN
|
|
description: CPU2 USB clock enable
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: LPTIM1EN
|
|
description: CPU2 Low power timer 1 clock enable
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/C2APB1ENR2:
|
|
description: CPU2 APB1 peripheral clock enable register 2
|
|
fields:
|
|
- name: LPUART1EN
|
|
description: CPU2 Low power UART 1 clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LPTIM2EN
|
|
description: CPU2 LPTIM2EN
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
fieldset/C2APB1SMENR1:
|
|
description: CPU2 APB1SMENR1
|
|
fields:
|
|
- name: TIM2SMEN
|
|
description: TIM2 timer clocks enable during CPU2 Sleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LCDSMEN
|
|
description: LCD clocks enable during CPU2 Sleep mode
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: RTCAPBSMEN
|
|
description: RTC APB clocks enable during CPU2 Sleep mode
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: SPI2SMEN
|
|
description: SPI2 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: I2C1SMEN
|
|
description: I2C1 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C3SMEN
|
|
description: I2C3 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CRSMEN
|
|
description: CRS clocks enable during CPU2 Sleep mode
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: USBSMEN
|
|
description: USB FS clocks enable during CPU2 Sleep mode
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: LPTIM1SMEN
|
|
description: Low power timer 1 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/C2APB1SMENR2:
|
|
description: CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2
|
|
fields:
|
|
- name: LPUART1SMEN
|
|
description: Low power UART 1 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LPTIM2SMEN
|
|
description: Low power timer 2 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
fieldset/C2APB2ENR:
|
|
description: CPU2 APB2ENR
|
|
fields:
|
|
- name: TIM1EN
|
|
description: CPU2 TIM1 timer clock enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1EN
|
|
description: CPU2 SPI1 clock enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1EN
|
|
description: CPU2 USART1clock enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16EN
|
|
description: CPU2 TIM16 timer clock enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17EN
|
|
description: CPU2 TIM17 timer clock enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SAI1EN
|
|
description: CPU2 SAI1 clock enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
fieldset/C2APB2SMENR:
|
|
description: CPU2 APB2SMENR
|
|
fields:
|
|
- name: TIM1SMEN
|
|
description: TIM1 timer clocks enable during CPU2 Sleep mode
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1SMEN
|
|
description: SPI1 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: USART1SMEN
|
|
description: USART1clocks enable during CPU2 Sleep mode
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM16SMEN
|
|
description: TIM16 timer clocks enable during CPU2 Sleep mode
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17SMEN
|
|
description: TIM17 timer clocks enable during CPU2 Sleep mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SAI1SMEN
|
|
description: SAI1 clocks enable during CPU2 Sleep mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
fieldset/C2APB3ENR:
|
|
description: CPU2 APB3ENR
|
|
fields:
|
|
- name: BLEEN
|
|
description: CPU2 BLE interface clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EN802
|
|
description: CPU2 802.15.4 interface clock enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
fieldset/C2APB3SMENR:
|
|
description: CPU2 APB3SMENR
|
|
fields:
|
|
- name: BLESMEN
|
|
description: BLE interface clocks enable during CPU2 Sleep mode
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: SMEN802
|
|
description: 802.15.4 interface clocks enable during CPU2 Sleep modes
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
fieldset/CCIPR:
|
|
description: CCIPR
|
|
fields:
|
|
- name: USART1SEL
|
|
description: USART1 clock source selection
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
enum: USART1SEL
|
|
- name: LPUART1SEL
|
|
description: LPUART1 clock source selection
|
|
bit_offset: 10
|
|
bit_size: 2
|
|
enum: LPUART1SEL
|
|
- name: I2C1SEL
|
|
description: I2C1 clock source selection
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
enum: I2C1SEL
|
|
- name: I2C3SEL
|
|
description: I2C3 clock source selection
|
|
bit_offset: 16
|
|
bit_size: 2
|
|
enum: I2C3SEL
|
|
- name: LPTIM1SEL
|
|
description: Low power timer 1 clock source selection
|
|
bit_offset: 18
|
|
bit_size: 2
|
|
enum: LPTIM1SEL
|
|
- name: LPTIM2SEL
|
|
description: Low power timer 2 clock source selection
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
enum: LPTIM2SEL
|
|
- name: SAI1SEL
|
|
description: SAI1 clock source selection
|
|
bit_offset: 22
|
|
bit_size: 2
|
|
enum: SAI1SEL
|
|
- name: CLK48SEL
|
|
description: 48 MHz clock source selection
|
|
bit_offset: 26
|
|
bit_size: 2
|
|
enum: CLK48SEL
|
|
- name: ADCSEL
|
|
description: ADCs clock source selection
|
|
bit_offset: 28
|
|
bit_size: 2
|
|
enum: ADCSEL
|
|
- name: RNGSEL
|
|
description: RNG clock source selection
|
|
bit_offset: 30
|
|
bit_size: 2
|
|
enum: RNGSEL
|
|
fieldset/CFGR:
|
|
description: Clock configuration register
|
|
fields:
|
|
- name: SW
|
|
description: System clock switch
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
enum: SW
|
|
- name: SWS
|
|
description: System clock switch status
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
enum: SW
|
|
- name: HPRE
|
|
description: AHB prescaler
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
enum: HPRE
|
|
- name: PPRE1
|
|
description: PB low-speed prescaler (APB1)
|
|
bit_offset: 8
|
|
bit_size: 3
|
|
enum: PPRE
|
|
- name: PPRE2
|
|
description: APB high-speed prescaler (APB2)
|
|
bit_offset: 11
|
|
bit_size: 3
|
|
enum: PPRE
|
|
- name: STOPWUCK
|
|
description: Wakeup from Stop and CSS backup clock selection
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: HPREF
|
|
description: AHB prescaler flag
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PPRE1F
|
|
description: APB1 prescaler flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: PPRE2F
|
|
description: APB2 prescaler flag
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: MCOSEL
|
|
description: Microcontroller clock output
|
|
bit_offset: 24
|
|
bit_size: 4
|
|
enum: MCOSEL
|
|
- name: MCOPRE
|
|
description: Microcontroller clock output prescaler
|
|
bit_offset: 28
|
|
bit_size: 3
|
|
enum: MCOPRE
|
|
fieldset/CICR:
|
|
description: Clock interrupt clear register
|
|
fields:
|
|
- name: LSI1RDYC
|
|
description: LSI1 ready interrupt clear
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYC
|
|
description: LSE ready interrupt clear
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIRDYC
|
|
description: MSI ready interrupt clear
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYC
|
|
description: HSI ready interrupt clear
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYC
|
|
description: HSE ready interrupt clear
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLRDYC
|
|
description: PLL ready interrupt clear
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PLLSAI1RDYC
|
|
description: PLLSAI1 ready interrupt clear
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: HSECSSC
|
|
description: HSE Clock security system interrupt clear
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSECSSC
|
|
description: LSE Clock security system interrupt clear
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSI48RDYC
|
|
description: HSI48 ready interrupt clear
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: LSI2RDYC
|
|
description: LSI2 ready interrupt clear
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
fieldset/CIER:
|
|
description: Clock interrupt enable register
|
|
fields:
|
|
- name: LSI1RDYIE
|
|
description: LSI1 ready interrupt enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYIE
|
|
description: LSE ready interrupt enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIRDYIE
|
|
description: MSI ready interrupt enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYIE
|
|
description: HSI ready interrupt enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYIE
|
|
description: HSE ready interrupt enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLRDYIE
|
|
description: PLLSYS ready interrupt enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PLLSAI1RDYIE
|
|
description: PLLSAI1 ready interrupt enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: LSECSSIE
|
|
description: LSE clock security system interrupt enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSI48RDYIE
|
|
description: HSI48 ready interrupt enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: LSI2RDYIE
|
|
description: LSI2 ready interrupt enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
fieldset/CIFR:
|
|
description: Clock interrupt flag register
|
|
fields:
|
|
- name: LSI1RDYF
|
|
description: LSI1 ready interrupt flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYF
|
|
description: LSE ready interrupt flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIRDYF
|
|
description: MSI ready interrupt flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYF
|
|
description: HSI ready interrupt flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYF
|
|
description: HSE ready interrupt flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLRDYF
|
|
description: PLL ready interrupt flag
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PLLSAI1RDYF
|
|
description: PLLSAI1 ready interrupt flag
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: HSECSSF
|
|
description: HSE Clock security system interrupt flag
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSECSSF
|
|
description: LSE Clock security system interrupt flag
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSI48RDYF
|
|
description: HSI48 ready interrupt flag
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: LSI2RDYF
|
|
description: LSI2 ready interrupt flag
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
fieldset/CR:
|
|
description: Clock control register
|
|
fields:
|
|
- name: MSION
|
|
description: MSI clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: MSIRDY
|
|
description: MSI clock ready flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MSIPLLEN
|
|
description: MSI clock PLL enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: MSIRANGE
|
|
description: MSI clock ranges
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
enum: MSIRANGE
|
|
- name: HSION
|
|
description: HSI clock enabled
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: HSIKERON
|
|
description: HSI always enable for peripheral kernels
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSIRDY
|
|
description: HSI clock ready flag
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: HSIASFS
|
|
description: HSI automatic start from Stop
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: HSIKERDY
|
|
description: HSI kernel clock ready flag for peripherals requests
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: HSEON
|
|
description: HSE clock enabled
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: HSERDY
|
|
description: HSE clock ready flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSEBYP
|
|
description: HSE crystal oscillator bypass
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: CSSON
|
|
description: HSE Clock security system enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: HSEPRE
|
|
description: HSE sysclk and PLL M divider prescaler
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: HSEPRE
|
|
- name: PLLON
|
|
description: Main PLL enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLRDY
|
|
description: Main PLL clock ready flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PLLSAI1ON
|
|
description: SAI1 PLL enable
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: PLLSAI1RDY
|
|
description: SAI1 PLL clock ready flag
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
fieldset/CRRCR:
|
|
description: Clock recovery RC register
|
|
fields:
|
|
- name: HSI48ON
|
|
description: HSI48 oscillator enabled
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HSI48RDY
|
|
description: HSI48 clock ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSI48CAL
|
|
description: HSI48 clock calibration
|
|
bit_offset: 7
|
|
bit_size: 9
|
|
fieldset/CSR:
|
|
description: CSR
|
|
fields:
|
|
- name: LSI1ON
|
|
description: LSI1 oscillator enabled
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSI1RDY
|
|
description: LSI1 oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LSI2ON
|
|
description: LSI2 oscillator enabled
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: LSI2RDY
|
|
description: LSI2 oscillator ready
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: LSI2TRIMEN
|
|
description: LSI2 oscillator trimming enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: LSI2TRIMOK
|
|
description: LSI2 oscillator trim OK
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LSI2BW
|
|
description: LSI2 oscillator bias configuration
|
|
bit_offset: 8
|
|
bit_size: 4
|
|
- name: RFWKPSEL
|
|
description: RF system wakeup clock source selection
|
|
bit_offset: 14
|
|
bit_size: 2
|
|
- name: RFRSTS
|
|
description: Radio system BLE and 802.15.4 reset status
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: RMVF
|
|
description: Remove reset flag
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: OBLRSTF
|
|
description: Option byte loader reset flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PINRSTF
|
|
description: Pin reset flag
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: BORRSTF
|
|
description: BOR flag
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: SFTRSTF
|
|
description: Software reset flag
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: IWDGRSTF
|
|
description: Independent window watchdog reset flag
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: WWDGRSTF
|
|
description: Window watchdog reset flag
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: LPWRRSTF
|
|
description: Low-power reset flag
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/EXTCFGR:
|
|
description: Extended clock recovery register
|
|
fields:
|
|
- name: SHDHPRE
|
|
description: Shared AHB prescaler
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
enum: HPRE
|
|
- name: C2HPRE
|
|
description: CPU2 AHB prescaler
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
enum: HPRE
|
|
- name: SHDHPREF
|
|
description: Shared AHB prescaler flag
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: C2HPREF
|
|
description: CPU2 AHB prescaler flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: RFCSS
|
|
description: RF clock source selected
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
fieldset/HSECR:
|
|
description: Clock HSE register
|
|
fields:
|
|
- name: UNLOCKED
|
|
description: Register lock system
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HSES
|
|
description: HSE Sense amplifier threshold
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSEGMC
|
|
description: HSE current control
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
- name: HSETUNE
|
|
description: HSE capacitor tuning
|
|
bit_offset: 8
|
|
bit_size: 6
|
|
fieldset/ICSCR:
|
|
description: Internal clock sources calibration register
|
|
fields:
|
|
- name: MSICAL
|
|
description: MSI clock calibration
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: MSITRIM
|
|
description: MSI clock trimming
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: HSICAL
|
|
description: HSI clock calibration
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
- name: HSITRIM
|
|
description: HSI clock trimming
|
|
bit_offset: 24
|
|
bit_size: 7
|
|
fieldset/PLLCFGR:
|
|
description: PLLSYS configuration register
|
|
fields:
|
|
- name: PLLSRC
|
|
description: Main PLL, PLLSAI1 and PLLSAI2 entry clock source
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
enum: PLLSRC
|
|
- name: PLLM
|
|
description: Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
enum: PLLM
|
|
- name: PLLN
|
|
description: Main PLLSYS multiplication factor N
|
|
bit_offset: 8
|
|
bit_size: 7
|
|
enum: PLLN
|
|
- name: PLLPEN
|
|
description: Main PLLSYSP output enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PLLP
|
|
description: Main PLL division factor P for PPLSYSSAICLK
|
|
bit_offset: 17
|
|
bit_size: 5
|
|
enum: PLLP
|
|
- name: PLLQEN
|
|
description: Main PLLSYSQ output enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLQ
|
|
description: Main PLLSYS division factor Q for PLLSYSUSBCLK
|
|
bit_offset: 25
|
|
bit_size: 3
|
|
enum: PLLQ
|
|
- name: PLLREN
|
|
description: Main PLLSYSR PLLCLK output enable
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: PLLR
|
|
description: Main PLLSYS division factor R for SYSCLK (system clock)
|
|
bit_offset: 29
|
|
bit_size: 3
|
|
enum: PLLR
|
|
fieldset/PLLSAI1CFGR:
|
|
description: PLLSAI1 configuration register
|
|
fields:
|
|
- name: PLLN
|
|
description: SAIPLL multiplication factor for VCO
|
|
bit_offset: 8
|
|
bit_size: 7
|
|
enum: PLLN
|
|
- name: PLLPEN
|
|
description: SAIPLL PLLSAI1CLK output enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PLLP
|
|
description: SAI1PLL division factor P for PLLSAICLK (SAI1clock)
|
|
bit_offset: 17
|
|
bit_size: 5
|
|
enum: PLLP
|
|
- name: PLLQEN
|
|
description: SAIPLL PLLSAIUSBCLK output enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLQ
|
|
description: SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)
|
|
bit_offset: 25
|
|
bit_size: 3
|
|
enum: PLLQ
|
|
- name: PLLREN
|
|
description: PLLSAI PLLADC1CLK output enable
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: PLLR
|
|
description: PLLSAI division factor R for PLLADC1CLK (ADC clock)
|
|
bit_offset: 29
|
|
bit_size: 3
|
|
enum: PLLR
|
|
fieldset/SMPSCR:
|
|
description: Step Down converter control register
|
|
fields:
|
|
- name: SMPSSEL
|
|
description: Step Down converter clock selection
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: SMPSDIV
|
|
description: Step Down converter clock prescaler
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
- name: SMPSSWS
|
|
description: Step Down converter clock switch status
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
enum/ADCSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: DISABLE
|
|
description: No clock selected
|
|
value: 0
|
|
- name: PLLSAI1_R
|
|
value: 1
|
|
- name: PLL1_P
|
|
value: 2
|
|
- name: SYS
|
|
description: SYSCLK clock selected
|
|
value: 3
|
|
enum/CLK48SEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HSI48
|
|
description: HSI48 clock selected
|
|
value: 0
|
|
- name: PLLSAI1_Q
|
|
description: PLLSAI1_Q aka PLL48M1CLK clock selected
|
|
value: 1
|
|
- name: PLL1_Q
|
|
description: PLL_Q aka PLL48M2CLK clock selected
|
|
value: 2
|
|
- name: MSI
|
|
description: MSI clock selected
|
|
value: 3
|
|
enum/HPRE:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Div1
|
|
description: DCLK not divided
|
|
value: 0
|
|
- name: Div3
|
|
description: hclk = SYSCLK divided by 3
|
|
value: 1
|
|
- name: Div5
|
|
description: hclk = SYSCLK divided by 5
|
|
value: 2
|
|
- name: Div6
|
|
description: hclk = SYSCLK divided by 6
|
|
value: 5
|
|
- name: Div10
|
|
description: hclk = SYSCLK divided by 8
|
|
value: 6
|
|
- name: Div32
|
|
description: hclk = SYSCLK divided by 32
|
|
value: 7
|
|
- name: Div2
|
|
description: hclk = SYSCLK divided by 2
|
|
value: 8
|
|
- name: Div4
|
|
description: hclk = SYSCLK divided by 4
|
|
value: 9
|
|
- name: Div8
|
|
description: hclk = SYSCLK divided by 8
|
|
value: 10
|
|
- name: Div16
|
|
description: hclk = SYSCLK divided by 16
|
|
value: 11
|
|
- name: Div64
|
|
description: hclk = SYSCLK divided by 64
|
|
value: 12
|
|
- name: Div128
|
|
description: hclk = SYSCLK divided by 128
|
|
value: 13
|
|
- name: Div256
|
|
description: hclk = SYSCLK divided by 256
|
|
value: 14
|
|
- name: Div512
|
|
description: hclk = SYSCLK divided by 256
|
|
value: 15
|
|
enum/HSEPRE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Div1
|
|
value: 0
|
|
- name: Div2
|
|
value: 1
|
|
enum/I2C1SEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: PCLK1
|
|
description: PCLK clock selected
|
|
value: 0
|
|
- name: SYS
|
|
description: SYSCLK clock selected
|
|
value: 1
|
|
- name: HSI
|
|
description: HSI clock selected
|
|
value: 2
|
|
enum/I2C3SEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: PCLK1
|
|
description: PCLK clock selected
|
|
value: 0
|
|
- name: SYS
|
|
description: SYSCLK clock selected
|
|
value: 1
|
|
- name: HSI
|
|
description: HSI clock selected
|
|
value: 2
|
|
enum/LPTIM1SEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: PCLK1
|
|
description: PCLK clock selected
|
|
value: 0
|
|
- name: LSI
|
|
description: LSI clock selected
|
|
value: 1
|
|
- name: HSI
|
|
description: HSI clock selected
|
|
value: 2
|
|
- name: LSE
|
|
description: LSE clock selected
|
|
value: 3
|
|
enum/LPTIM2SEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: PCLK1
|
|
description: PCLK clock selected
|
|
value: 0
|
|
- name: LSI
|
|
description: LSI clock selected
|
|
value: 1
|
|
- name: HSI
|
|
description: HSI clock selected
|
|
value: 2
|
|
- name: LSE
|
|
description: LSE clock selected
|
|
value: 3
|
|
enum/LPUART1SEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: PCLK1
|
|
description: PCLK clock selected
|
|
value: 0
|
|
- name: SYS
|
|
description: SYSCLK clock selected
|
|
value: 1
|
|
- name: HSI
|
|
description: HSI clock selected
|
|
value: 2
|
|
- name: HSE
|
|
value: 3
|
|
enum/LSEDRV:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Low
|
|
description: Low driving capability
|
|
value: 0
|
|
- name: MediumLow
|
|
description: Medium low driving capability
|
|
value: 1
|
|
- name: MediumHigh
|
|
description: Medium high driving capability
|
|
value: 2
|
|
- name: High
|
|
description: High driving capability
|
|
value: 3
|
|
enum/MCOPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: No division
|
|
value: 0
|
|
- name: Div2
|
|
description: Division by 2
|
|
value: 1
|
|
- name: Div4
|
|
description: Division by 4
|
|
value: 2
|
|
- name: Div8
|
|
description: Division by 8
|
|
value: 3
|
|
- name: Div16
|
|
description: Division by 16
|
|
value: 4
|
|
enum/MCOSEL:
|
|
bit_size: 4
|
|
variants:
|
|
- name: DISABLE
|
|
description: No clock
|
|
value: 0
|
|
- name: SYS
|
|
description: SYSCLK clock selected
|
|
value: 1
|
|
- name: MSI
|
|
description: MSI oscillator clock selected
|
|
value: 2
|
|
- name: HSI
|
|
description: HSI oscillator clock selected
|
|
value: 3
|
|
- name: HSE
|
|
description: HSE clock selected (after stabilization, after HSERDY = 1)
|
|
value: 4
|
|
- name: PLL_R
|
|
description: PLL clock selected
|
|
value: 5
|
|
- name: LSI1
|
|
description: LSI1 oscillator clock selected
|
|
value: 6
|
|
- name: LSI2
|
|
description: LSI2 oscillator clock selected
|
|
value: 7
|
|
- name: LSE
|
|
description: LSE oscillator clock selected
|
|
value: 8
|
|
- name: HSI48
|
|
description: HSI48 oscillator clock selected
|
|
value: 9
|
|
- name: HSE_UNSTABLE
|
|
description: HSE clock selected (before stabilization, after HSEON = 1)
|
|
value: 12
|
|
enum/MSIRANGE:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Range100K
|
|
description: range 0 around 100 kHz
|
|
value: 0
|
|
- name: Range200K
|
|
description: range 1 around 200 kHz
|
|
value: 1
|
|
- name: Range400K
|
|
description: range 2 around 400 kHz
|
|
value: 2
|
|
- name: Range800K
|
|
description: range 3 around 800 kHz
|
|
value: 3
|
|
- name: Range1M
|
|
description: range 4 around 1 MHz
|
|
value: 4
|
|
- name: Range2M
|
|
description: range 5 around 2 MHz
|
|
value: 5
|
|
- name: Range4M
|
|
description: range 6 around 4 MHz
|
|
value: 6
|
|
- name: Range8M
|
|
description: range 7 around 8 MHz
|
|
value: 7
|
|
- name: Range16M
|
|
description: range 8 around 16 MHz
|
|
value: 8
|
|
- name: Range24M
|
|
description: range 9 around 24 MHz
|
|
value: 9
|
|
- name: Range32M
|
|
description: range 10 around 32 MHz
|
|
value: 10
|
|
- name: Range48M
|
|
description: range 11 around 48 MHz
|
|
value: 11
|
|
enum/PLLM:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
value: 0
|
|
- name: Div2
|
|
value: 1
|
|
- name: Div3
|
|
value: 2
|
|
- name: Div4
|
|
value: 3
|
|
- name: Div5
|
|
value: 4
|
|
- name: Div6
|
|
value: 5
|
|
- name: Div7
|
|
value: 6
|
|
- name: Div8
|
|
value: 7
|
|
enum/PLLN:
|
|
bit_size: 7
|
|
variants:
|
|
- name: Mul6
|
|
value: 6
|
|
- name: Mul7
|
|
value: 7
|
|
- name: Mul8
|
|
value: 8
|
|
- name: Mul9
|
|
value: 9
|
|
- name: Mul10
|
|
value: 10
|
|
- name: Mul11
|
|
value: 11
|
|
- name: Mul12
|
|
value: 12
|
|
- name: Mul13
|
|
value: 13
|
|
- name: Mul14
|
|
value: 14
|
|
- name: Mul15
|
|
value: 15
|
|
- name: Mul16
|
|
value: 16
|
|
- name: Mul17
|
|
value: 17
|
|
- name: Mul18
|
|
value: 18
|
|
- name: Mul19
|
|
value: 19
|
|
- name: Mul20
|
|
value: 20
|
|
- name: Mul21
|
|
value: 21
|
|
- name: Mul22
|
|
value: 22
|
|
- name: Mul23
|
|
value: 23
|
|
- name: Mul24
|
|
value: 24
|
|
- name: Mul25
|
|
value: 25
|
|
- name: Mul26
|
|
value: 26
|
|
- name: Mul27
|
|
value: 27
|
|
- name: Mul28
|
|
value: 28
|
|
- name: Mul29
|
|
value: 29
|
|
- name: Mul30
|
|
value: 30
|
|
- name: Mul31
|
|
value: 31
|
|
- name: Mul32
|
|
value: 32
|
|
- name: Mul33
|
|
value: 33
|
|
- name: Mul34
|
|
value: 34
|
|
- name: Mul35
|
|
value: 35
|
|
- name: Mul36
|
|
value: 36
|
|
- name: Mul37
|
|
value: 37
|
|
- name: Mul38
|
|
value: 38
|
|
- name: Mul39
|
|
value: 39
|
|
- name: Mul40
|
|
value: 40
|
|
- name: Mul41
|
|
value: 41
|
|
- name: Mul42
|
|
value: 42
|
|
- name: Mul43
|
|
value: 43
|
|
- name: Mul44
|
|
value: 44
|
|
- name: Mul45
|
|
value: 45
|
|
- name: Mul46
|
|
value: 46
|
|
- name: Mul47
|
|
value: 47
|
|
- name: Mul48
|
|
value: 48
|
|
- name: Mul49
|
|
value: 49
|
|
- name: Mul50
|
|
value: 50
|
|
- name: Mul51
|
|
value: 51
|
|
- name: Mul52
|
|
value: 52
|
|
- name: Mul53
|
|
value: 53
|
|
- name: Mul54
|
|
value: 54
|
|
- name: Mul55
|
|
value: 55
|
|
- name: Mul56
|
|
value: 56
|
|
- name: Mul57
|
|
value: 57
|
|
- name: Mul58
|
|
value: 58
|
|
- name: Mul59
|
|
value: 59
|
|
- name: Mul60
|
|
value: 60
|
|
- name: Mul61
|
|
value: 61
|
|
- name: Mul62
|
|
value: 62
|
|
- name: Mul63
|
|
value: 63
|
|
- name: Mul64
|
|
value: 64
|
|
- name: Mul65
|
|
value: 65
|
|
- name: Mul66
|
|
value: 66
|
|
- name: Mul67
|
|
value: 67
|
|
- name: Mul68
|
|
value: 68
|
|
- name: Mul69
|
|
value: 69
|
|
- name: Mul70
|
|
value: 70
|
|
- name: Mul71
|
|
value: 71
|
|
- name: Mul72
|
|
value: 72
|
|
- name: Mul73
|
|
value: 73
|
|
- name: Mul74
|
|
value: 74
|
|
- name: Mul75
|
|
value: 75
|
|
- name: Mul76
|
|
value: 76
|
|
- name: Mul77
|
|
value: 77
|
|
- name: Mul78
|
|
value: 78
|
|
- name: Mul79
|
|
value: 79
|
|
- name: Mul80
|
|
value: 80
|
|
- name: Mul81
|
|
value: 81
|
|
- name: Mul82
|
|
value: 82
|
|
- name: Mul83
|
|
value: 83
|
|
- name: Mul84
|
|
value: 84
|
|
- name: Mul85
|
|
value: 85
|
|
- name: Mul86
|
|
value: 86
|
|
- name: Mul87
|
|
value: 87
|
|
- name: Mul88
|
|
value: 88
|
|
- name: Mul89
|
|
value: 89
|
|
- name: Mul90
|
|
value: 90
|
|
- name: Mul91
|
|
value: 91
|
|
- name: Mul92
|
|
value: 92
|
|
- name: Mul93
|
|
value: 93
|
|
- name: Mul94
|
|
value: 94
|
|
- name: Mul95
|
|
value: 95
|
|
- name: Mul96
|
|
value: 96
|
|
- name: Mul97
|
|
value: 97
|
|
- name: Mul98
|
|
value: 98
|
|
- name: Mul99
|
|
value: 99
|
|
- name: Mul100
|
|
value: 100
|
|
- name: Mul101
|
|
value: 101
|
|
- name: Mul102
|
|
value: 102
|
|
- name: Mul103
|
|
value: 103
|
|
- name: Mul104
|
|
value: 104
|
|
- name: Mul105
|
|
value: 105
|
|
- name: Mul106
|
|
value: 106
|
|
- name: Mul107
|
|
value: 107
|
|
- name: Mul108
|
|
value: 108
|
|
- name: Mul109
|
|
value: 109
|
|
- name: Mul110
|
|
value: 110
|
|
- name: Mul111
|
|
value: 111
|
|
- name: Mul112
|
|
value: 112
|
|
- name: Mul113
|
|
value: 113
|
|
- name: Mul114
|
|
value: 114
|
|
- name: Mul115
|
|
value: 115
|
|
- name: Mul116
|
|
value: 116
|
|
- name: Mul117
|
|
value: 117
|
|
- name: Mul118
|
|
value: 118
|
|
- name: Mul119
|
|
value: 119
|
|
- name: Mul120
|
|
value: 120
|
|
- name: Mul121
|
|
value: 121
|
|
- name: Mul122
|
|
value: 122
|
|
- name: Mul123
|
|
value: 123
|
|
- name: Mul124
|
|
value: 124
|
|
- name: Mul125
|
|
value: 125
|
|
- name: Mul126
|
|
value: 126
|
|
- name: Mul127
|
|
value: 127
|
|
enum/PLLP:
|
|
bit_size: 5
|
|
variants:
|
|
- name: Div2
|
|
value: 1
|
|
- name: Div3
|
|
value: 2
|
|
- name: Div4
|
|
value: 3
|
|
- name: Div5
|
|
value: 4
|
|
- name: Div6
|
|
value: 5
|
|
- name: Div7
|
|
value: 6
|
|
- name: Div8
|
|
value: 7
|
|
- name: Div9
|
|
value: 8
|
|
- name: Div10
|
|
value: 9
|
|
- name: Div11
|
|
value: 10
|
|
- name: Div12
|
|
value: 11
|
|
- name: Div13
|
|
value: 12
|
|
- name: Div14
|
|
value: 13
|
|
- name: Div15
|
|
value: 14
|
|
- name: Div16
|
|
value: 15
|
|
- name: Div17
|
|
value: 16
|
|
- name: Div18
|
|
value: 17
|
|
- name: Div19
|
|
value: 18
|
|
- name: Div20
|
|
value: 19
|
|
- name: Div21
|
|
value: 20
|
|
- name: Div22
|
|
value: 21
|
|
- name: Div23
|
|
value: 22
|
|
- name: Div24
|
|
value: 23
|
|
- name: Div25
|
|
value: 24
|
|
- name: Div26
|
|
value: 25
|
|
- name: Div27
|
|
value: 26
|
|
- name: Div28
|
|
value: 27
|
|
- name: Div29
|
|
value: 28
|
|
- name: Div30
|
|
value: 29
|
|
- name: Div31
|
|
value: 30
|
|
enum/PLLQ:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div2
|
|
value: 1
|
|
- name: Div3
|
|
value: 2
|
|
- name: Div4
|
|
value: 3
|
|
- name: Div5
|
|
value: 4
|
|
- name: Div6
|
|
value: 5
|
|
- name: Div7
|
|
value: 6
|
|
enum/PLLR:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div2
|
|
value: 1
|
|
- name: Div3
|
|
value: 2
|
|
- name: Div4
|
|
value: 3
|
|
- name: Div5
|
|
value: 4
|
|
- name: Div6
|
|
value: 5
|
|
- name: Div7
|
|
value: 6
|
|
enum/PLLSRC:
|
|
bit_size: 2
|
|
variants:
|
|
- name: DISABLE
|
|
description: No clock selected as PLL entry clock source
|
|
value: 0
|
|
- name: MSI
|
|
description: MSI selected as PLL entry clock source
|
|
value: 1
|
|
- name: HSI
|
|
description: HSI selected as PLL entry clock source
|
|
value: 2
|
|
- name: HSE
|
|
description: HSE selected as PLL entry clock source
|
|
value: 3
|
|
enum/PPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: HCLK not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: HCLK divided by 2
|
|
value: 4
|
|
- name: Div4
|
|
description: HCLK divided by 4
|
|
value: 5
|
|
- name: Div8
|
|
description: HCLK divided by 8
|
|
value: 6
|
|
- name: Div16
|
|
description: HCLK divided by 16
|
|
value: 7
|
|
enum/RNGSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: CLK48
|
|
description: CLK48
|
|
value: 0
|
|
- name: LSI
|
|
description: LSI clock selected
|
|
value: 1
|
|
- name: LSE
|
|
description: LSE clock selected
|
|
value: 2
|
|
enum/RTCSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: DISABLE
|
|
description: No clock selected
|
|
value: 0
|
|
- name: LSE
|
|
description: LSE oscillator clock selected
|
|
value: 1
|
|
- name: LSI
|
|
description: LSI oscillator clock selected
|
|
value: 2
|
|
- name: HSE
|
|
description: HSE oscillator clock divided by 32 selected
|
|
value: 3
|
|
enum/SAI1SEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: PLLSAI1_P
|
|
value: 0
|
|
- name: PLL1_P
|
|
value: 1
|
|
- name: HSI
|
|
value: 2
|
|
- name: SAI1_EXTCLK
|
|
value: 3
|
|
enum/SW:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MSI
|
|
value: 0
|
|
- name: HSI
|
|
value: 1
|
|
- name: HSE
|
|
value: 2
|
|
- name: PLL1_R
|
|
value: 3
|
|
enum/USART1SEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: PCLK1
|
|
description: PCLK clock selected
|
|
value: 0
|
|
- name: SYS
|
|
description: SYSCLK clock selected
|
|
value: 1
|
|
- name: HSI
|
|
description: HSI clock selected
|
|
value: 2
|
|
- name: HSE
|
|
value: 3
|