27c71ac451
this is a special case, as most data sources don't mention this as a separate peripheral at all, and those that do don't handle the offsets in the case of multiple FDCANS H7 chips have a single 10KB block shared between all FDCANs
46 lines
805 B
YAML
46 lines
805 B
YAML
block/FDCANRAM:
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description: FDCAN Message RAM
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items:
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- name: FLSSA
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description: 11-bit filter
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array:
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len: 28
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stride: 4
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byte_offset: 0
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bit_size: 32
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- name: FLESA
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description: 29-bit filter
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array:
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len: 16
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stride: 4
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byte_offset: 112
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bit_size: 32
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- name: RXFIFO0
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description: Rx FIFO 0
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array:
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len: 54
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stride: 4
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byte_offset: 176
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bit_size: 32
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- name: RXFIFO1
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description: Rx FIFO 1
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array:
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len: 54
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stride: 4
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byte_offset: 392
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bit_size: 32
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- name: TXEFIFO
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description: Tx event FIFO
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array:
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len: 6
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stride: 4
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byte_offset: 608
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bit_size: 32
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- name: TXBUF
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description: Tx buffer
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array:
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len: 54
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stride: 4
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byte_offset: 632
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bit_size: 32
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