1126 lines
25 KiB
YAML
1126 lines
25 KiB
YAML
block/RCC:
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|
description: Reset and clock control
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items:
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- byte_offset: 0
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description: Clock control register
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fieldset: CR
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name: CR
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- byte_offset: 4
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description: Clock configuration register (RCC_CFGR)
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fieldset: CFGR
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name: CFGR
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- byte_offset: 8
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description: Clock interrupt register (RCC_CIR)
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fieldset: CIR
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name: CIR
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- byte_offset: 12
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description: APB2 peripheral reset register (RCC_APB2RSTR)
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fieldset: APB2RSTR
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name: APB2RSTR
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- byte_offset: 16
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description: APB1 peripheral reset register (RCC_APB1RSTR)
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fieldset: APB1RSTR
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name: APB1RSTR
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- byte_offset: 20
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description: AHB Peripheral Clock enable register (RCC_AHBENR)
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fieldset: AHBENR
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name: AHBENR
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- byte_offset: 24
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description: APB2 peripheral clock enable register (RCC_APB2ENR)
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fieldset: APB2ENR
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name: APB2ENR
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- byte_offset: 28
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description: APB1 peripheral clock enable register (RCC_APB1ENR)
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fieldset: APB1ENR
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name: APB1ENR
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- byte_offset: 32
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description: Backup domain control register (RCC_BDCR)
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fieldset: BDCR
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name: BDCR
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- byte_offset: 36
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description: Control/status register (RCC_CSR)
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fieldset: CSR
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name: CSR
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- byte_offset: 40
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description: AHB peripheral clock reset register (RCC_AHBRSTR)
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fieldset: AHBRSTR
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name: AHBRSTR
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- byte_offset: 44
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description: Clock configuration register 2
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fieldset: CFGR2
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name: CFGR2
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enum/ADCPRE:
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bit_size: 2
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variants:
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- description: PCLK2 divided by 2
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name: Div2
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value: 0
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- description: PCLK2 divided by 4
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name: Div4
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value: 1
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- description: PCLK2 divided by 8
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name: Div6
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value: 2
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- description: PCLK2 divided by 16
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name: Div8
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value: 3
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enum/HPRE:
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bit_size: 4
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variants:
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- description: SYSCLK not divided
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name: Div1
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value: 0
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- description: SYSCLK divided by 2
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name: Div2
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value: 8
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- description: SYSCLK divided by 4
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name: Div4
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value: 9
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- description: SYSCLK divided by 8
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name: Div8
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value: 10
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- description: SYSCLK divided by 16
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name: Div16
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value: 11
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- description: SYSCLK divided by 64
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name: Div64
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value: 12
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- description: SYSCLK divided by 128
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name: Div128
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value: 13
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- description: SYSCLK divided by 256
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name: Div256
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value: 14
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- description: SYSCLK divided by 512
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name: Div512
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value: 15
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enum/I2S2SRC:
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bit_size: 1
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variants:
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- description: System clock (SYSCLK) selected as I2S clock entry
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name: SYSCLK
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value: 0
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- description: PLL3 VCO clock selected as I2S clock entry
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name: PLL3
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value: 1
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enum/MCO:
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bit_size: 4
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variants:
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- description: MCO output disabled, no clock on MCO
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name: NoMCO
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value: 0
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- description: System clock selected
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name: SYSCLK
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value: 4
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- description: HSI oscillator clock selected
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name: HSI
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value: 5
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- description: HSE oscillator clock selected
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name: HSE
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value: 6
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- description: PLL clock selected (divided by 1 or 2, depending en PLLNODIV)
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name: PLL
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value: 7
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enum/OTGFSPRE:
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bit_size: 1
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variants:
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- description: PLL clock is divided by 1.5
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name: DIV1_5
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value: 0
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- description: PLL clock is not divided
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name: DIV1
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value: 1
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enum/PLL2MUL:
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bit_size: 4
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variants:
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- description: PLL clock entry x8
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name: Mul8
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value: 6
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- description: PLL clock entry x9
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name: Mul9
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value: 7
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- description: PLL clock entry x10
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name: Mul10
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value: 8
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- description: PLL clock entry x11
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name: Mul11
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value: 9
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- description: PLL clock entry x12
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name: Mul12
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value: 10
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- description: PLL clock entry x13
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name: Mul13
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value: 11
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- description: PLL clock entry x14
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name: Mul14
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value: 12
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- description: PLL clock entry x16
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name: Mul16
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value: 14
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- description: PLL clock entry x20
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name: Mul20
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value: 15
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enum/PLLMUL:
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bit_size: 4
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variants:
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- description: PLL input clock x2
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name: Mul2
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value: 0
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- description: PLL input clock x3
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name: Mul3
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value: 1
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- description: PLL input clock x4
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name: Mul4
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value: 2
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- description: PLL input clock x5
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name: Mul5
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value: 3
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- description: PLL input clock x6
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name: Mul6
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value: 4
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- description: PLL input clock x7
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name: Mul7
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value: 5
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- description: PLL input clock x8
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name: Mul8
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value: 6
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- description: PLL input clock x9
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name: Mul9
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value: 7
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- description: PLL input clock x10
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name: Mul10
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value: 8
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- description: PLL input clock x11
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name: Mul11
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value: 9
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- description: PLL input clock x12
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name: Mul12
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value: 10
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- description: PLL input clock x13
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name: Mul13
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value: 11
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- description: PLL input clock x14
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name: Mul14
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value: 12
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- description: PLL input clock x15
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name: Mul15
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value: 13
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- description: PLL input clock x16
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name: Mul16
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value: 14
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- description: PLL input clock x16
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name: Mul16x
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value: 15
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enum/PLLSRC:
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bit_size: 1
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variants:
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- description: HSI divided by 2 selected as PLL input clock
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name: HSI_Div2
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value: 0
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- description: HSE divided by PREDIV selected as PLL input clock
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name: HSE_Div_PREDIV
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value: 1
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enum/PLLXTPRE:
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bit_size: 1
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variants:
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- description: HSE clock not divided
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name: Div1
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value: 0
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- description: HSE clock divided by 2
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name: Div2
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value: 1
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enum/PPRE1:
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bit_size: 3
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variants:
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- description: HCLK not divided
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name: Div1
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value: 0
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- description: HCLK divided by 2
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name: Div2
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value: 4
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- description: HCLK divided by 4
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name: Div4
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value: 5
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- description: HCLK divided by 8
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name: Div8
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value: 6
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- description: HCLK divided by 16
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name: Div16
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value: 7
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enum/PREDIV1:
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bit_size: 4
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variants:
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- description: PREDIV input clock not divided
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name: Div1
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value: 0
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- description: PREDIV input clock divided by 2
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name: Div2
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value: 1
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- description: PREDIV input clock divided by 3
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name: Div3
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value: 2
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- description: PREDIV input clock divided by 4
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name: Div4
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value: 3
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- description: PREDIV input clock divided by 5
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name: Div5
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value: 4
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- description: PREDIV input clock divided by 6
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name: Div6
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value: 5
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- description: PREDIV input clock divided by 7
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name: Div7
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value: 6
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- description: PREDIV input clock divided by 8
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name: Div8
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value: 7
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- description: PREDIV input clock divided by 9
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name: Div9
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value: 8
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- description: PREDIV input clock divided by 10
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name: Div10
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value: 9
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- description: PREDIV input clock divided by 11
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name: Div11
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value: 10
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- description: PREDIV input clock divided by 12
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name: Div12
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value: 11
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- description: PREDIV input clock divided by 13
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name: Div13
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value: 12
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- description: PREDIV input clock divided by 14
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name: Div14
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value: 13
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- description: PREDIV input clock divided by 15
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name: Div15
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value: 14
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- description: PREDIV input clock divided by 16
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name: Div16
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value: 15
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enum/PREDIV1SRC:
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bit_size: 1
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variants:
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- description: HSE oscillator clock selected as PREDIV1 clock entry
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name: HSE
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value: 0
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- description: PLL2 selected as PREDIV1 clock entry
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name: PLL2
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value: 1
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enum/RTCSEL:
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bit_size: 2
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variants:
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- description: No clock
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name: NoClock
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value: 0
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- description: LSE oscillator clock used as RTC clock
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name: LSE
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value: 1
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- description: LSI oscillator clock used as RTC clock
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name: LSI
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value: 2
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- description: HSE oscillator clock divided by a prescaler used as RTC clock
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name: HSE
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value: 3
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enum/SW:
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bit_size: 2
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variants:
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- description: HSI selected as system clock
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name: HSI
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value: 0
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- description: HSE selected as system clock
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name: HSE
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value: 1
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- description: PLL selected as system clock
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name: PLL
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value: 2
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enum/SWSR:
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bit_size: 2
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variants:
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- description: HSI oscillator used as system clock
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name: HSI
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value: 0
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- description: HSE oscillator used as system clock
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name: HSE
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value: 1
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- description: PLL used as system clock
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name: PLL
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value: 2
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enum/USBPRE:
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bit_size: 1
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variants:
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- description: PLL clock is divided by 1.5
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name: DIV1_5
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value: 0
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- description: PLL clock is not divided
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name: DIV1
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value: 1
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fieldset/AHBENR:
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description: AHB Peripheral Clock enable register (RCC_AHBENR)
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fields:
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- bit_offset: 0
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bit_size: 1
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description: DMA1 clock enable
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name: DMA1EN
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- bit_offset: 1
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bit_size: 1
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description: DMA2 clock enable
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name: DMA2EN
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- bit_offset: 2
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bit_size: 1
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description: SRAM interface clock enable
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name: SRAMEN
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- bit_offset: 4
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bit_size: 1
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description: FLITF clock enable
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name: FLITFEN
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- bit_offset: 6
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bit_size: 1
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description: CRC clock enable
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name: CRCEN
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- bit_offset: 8
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bit_size: 1
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description: FSMC clock enable
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name: FSMCEN
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- bit_offset: 10
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bit_size: 1
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description: SDIO clock enable
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name: SDIOEN
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- bit_offset: 12
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bit_size: 1
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description: USB OTG FS clock enable
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name: OTGFSEN
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- bit_offset: 14
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bit_size: 1
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description: Ethernet MAC clock enable
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name: ETHMACEN
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- bit_offset: 15
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bit_size: 1
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description: Ethernet MAC TX clock enable
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name: ETHMACTXEN
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- bit_offset: 16
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bit_size: 1
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description: Ethernet MAC RX clock enable
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name: ETHMACRXEN
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fieldset/AHBRSTR:
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description: AHB peripheral clock reset register (RCC_AHBRSTR)
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fields:
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- bit_offset: 12
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bit_size: 1
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description: USB OTG FS reset
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name: OTGFSRST
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- bit_offset: 14
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bit_size: 1
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description: Ethernet MAC reset
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name: ETHMACRST
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fieldset/APB1ENR:
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description: APB1 peripheral clock enable register (RCC_APB1ENR)
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fields:
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- bit_offset: 0
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bit_size: 1
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description: Timer 2 clock enable
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name: TIM2EN
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- bit_offset: 1
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bit_size: 1
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description: Timer 3 clock enable
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name: TIM3EN
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- bit_offset: 2
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bit_size: 1
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description: Timer 4 clock enable
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name: TIM4EN
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- bit_offset: 3
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bit_size: 1
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description: Timer 5 clock enable
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name: TIM5EN
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- bit_offset: 4
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bit_size: 1
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description: Timer 6 clock enable
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name: TIM6EN
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- bit_offset: 5
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bit_size: 1
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description: Timer 7 clock enable
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name: TIM7EN
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- bit_offset: 6
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bit_size: 1
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description: Timer 12 clock enable
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name: TIM12EN
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- bit_offset: 7
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bit_size: 1
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description: Timer 13 clock enable
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name: TIM13EN
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- bit_offset: 8
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bit_size: 1
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description: Timer 14 clock enable
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name: TIM14EN
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- bit_offset: 11
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bit_size: 1
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description: Window watchdog clock enable
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name: WWDGEN
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- bit_offset: 14
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bit_size: 1
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description: SPI 2 clock enable
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name: SPI2EN
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- bit_offset: 15
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bit_size: 1
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description: SPI 3 clock enable
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name: SPI3EN
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- bit_offset: 17
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bit_size: 1
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description: USART 2 clock enable
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name: USART2EN
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- bit_offset: 18
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bit_size: 1
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description: USART 3 clock enable
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|
name: USART3EN
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- bit_offset: 19
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bit_size: 1
|
|
description: UART 4 clock enable
|
|
name: UART4EN
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|
- bit_offset: 20
|
|
bit_size: 1
|
|
description: UART 5 clock enable
|
|
name: UART5EN
|
|
- bit_offset: 21
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|
bit_size: 1
|
|
description: I2C 1 clock enable
|
|
name: I2C1EN
|
|
- bit_offset: 22
|
|
bit_size: 1
|
|
description: I2C 2 clock enable
|
|
name: I2C2EN
|
|
- bit_offset: 23
|
|
bit_size: 1
|
|
description: USB clock enable
|
|
name: USBEN
|
|
- bit_offset: 25
|
|
bit_size: 1
|
|
description: CAN clock enable
|
|
name: CANEN
|
|
- bit_offset: 25
|
|
bit_size: 1
|
|
description: CAN1 clock enable
|
|
name: CAN1EN
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|
- bit_offset: 26
|
|
bit_size: 1
|
|
description: CAN2 clock enable
|
|
name: CAN2EN
|
|
- bit_offset: 27
|
|
bit_size: 1
|
|
description: Backup interface clock enable
|
|
name: BKPEN
|
|
- bit_offset: 28
|
|
bit_size: 1
|
|
description: Power interface clock enable
|
|
name: PWREN
|
|
- bit_offset: 29
|
|
bit_size: 1
|
|
description: DAC interface clock enable
|
|
name: DACEN
|
|
- bit_offset: 30
|
|
bit_size: 1
|
|
description: CEC clock enable
|
|
name: CECEN
|
|
fieldset/APB1RSTR:
|
|
description: APB1 peripheral reset register (RCC_APB1RSTR)
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: Timer 2 reset
|
|
name: TIM2RST
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: Timer 3 reset
|
|
name: TIM3RST
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: Timer 4 reset
|
|
name: TIM4RST
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: Timer 5 reset
|
|
name: TIM5RST
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: Timer 6 reset
|
|
name: TIM6RST
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: Timer 7 reset
|
|
name: TIM7RST
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: Timer 12 reset
|
|
name: TIM12RST
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: Timer 13 reset
|
|
name: TIM13RST
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: Timer 14 reset
|
|
name: TIM14RST
|
|
- bit_offset: 11
|
|
bit_size: 1
|
|
description: Window watchdog reset
|
|
name: WWDGRST
|
|
- bit_offset: 14
|
|
bit_size: 1
|
|
description: SPI2 reset
|
|
name: SPI2RST
|
|
- bit_offset: 15
|
|
bit_size: 1
|
|
description: SPI3 reset
|
|
name: SPI3RST
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: USART 2 reset
|
|
name: USART2RST
|
|
- bit_offset: 18
|
|
bit_size: 1
|
|
description: USART 3 reset
|
|
name: USART3RST
|
|
- bit_offset: 19
|
|
bit_size: 1
|
|
description: USART 4 reset
|
|
name: UART4RST
|
|
- bit_offset: 20
|
|
bit_size: 1
|
|
description: USART 5 reset
|
|
name: UART5RST
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: I2C1 reset
|
|
name: I2C1RST
|
|
- bit_offset: 22
|
|
bit_size: 1
|
|
description: I2C2 reset
|
|
name: I2C2RST
|
|
- bit_offset: 23
|
|
bit_size: 1
|
|
description: USB reset
|
|
name: USBRST
|
|
- bit_offset: 25
|
|
bit_size: 1
|
|
description: CAN reset
|
|
name: CANRST
|
|
- bit_offset: 25
|
|
bit_size: 1
|
|
description: CAN1 reset
|
|
name: CAN1RST
|
|
- bit_offset: 26
|
|
bit_size: 1
|
|
description: CAN2 reset
|
|
name: CAN2RST
|
|
- bit_offset: 27
|
|
bit_size: 1
|
|
description: Backup interface reset
|
|
name: BKPRST
|
|
- bit_offset: 28
|
|
bit_size: 1
|
|
description: Power interface reset
|
|
name: PWRRST
|
|
- bit_offset: 29
|
|
bit_size: 1
|
|
description: DAC interface reset
|
|
name: DACRST
|
|
- bit_offset: 30
|
|
bit_size: 1
|
|
description: CEC reset
|
|
name: CECRST
|
|
fieldset/APB2ENR:
|
|
description: APB2 peripheral clock enable register (RCC_APB2ENR)
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: Alternate function I/O clock enable
|
|
name: AFIOEN
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: I/O port A clock enable
|
|
name: GPIOAEN
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: I/O port B clock enable
|
|
name: GPIOBEN
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: I/O port C clock enable
|
|
name: GPIOCEN
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: I/O port D clock enable
|
|
name: GPIODEN
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: I/O port E clock enable
|
|
name: GPIOEEN
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: I/O port F clock enable
|
|
name: GPIOFEN
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: I/O port G clock enable
|
|
name: GPIOGEN
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: ADC 1 interface clock enable
|
|
name: ADC1EN
|
|
- bit_offset: 10
|
|
bit_size: 1
|
|
description: ADC 2 interface clock enable
|
|
name: ADC2EN
|
|
- bit_offset: 11
|
|
bit_size: 1
|
|
description: TIM1 Timer clock enable
|
|
name: TIM1EN
|
|
- bit_offset: 12
|
|
bit_size: 1
|
|
description: SPI 1 clock enable
|
|
name: SPI1EN
|
|
- bit_offset: 13
|
|
bit_size: 1
|
|
description: TIM8 Timer clock enable
|
|
name: TIM8EN
|
|
- bit_offset: 14
|
|
bit_size: 1
|
|
description: USART1 clock enable
|
|
name: USART1EN
|
|
- bit_offset: 15
|
|
bit_size: 1
|
|
description: ADC3 interface clock enable
|
|
name: ADC3EN
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: TIM15 Timer clock enable
|
|
name: TIM15EN
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: TIM16 Timer clock enable
|
|
name: TIM16EN
|
|
- bit_offset: 18
|
|
bit_size: 1
|
|
description: TIM17 Timer clock enable
|
|
name: TIM17EN
|
|
- bit_offset: 19
|
|
bit_size: 1
|
|
description: TIM9 Timer clock enable
|
|
name: TIM9EN
|
|
- bit_offset: 20
|
|
bit_size: 1
|
|
description: TIM10 Timer clock enable
|
|
name: TIM10EN
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: TIM11 Timer clock enable
|
|
name: TIM11EN
|
|
fieldset/APB2RSTR:
|
|
description: APB2 peripheral reset register (RCC_APB2RSTR)
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: Alternate function I/O reset
|
|
name: AFIORST
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: IO port A reset
|
|
name: GPIOARST
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: IO port B reset
|
|
name: GPIOBRST
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: IO port C reset
|
|
name: GPIOCRST
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: IO port D reset
|
|
name: GPIODRST
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: IO port E reset
|
|
name: GPIOERST
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: IO port F reset
|
|
name: GPIOFRST
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: IO port G reset
|
|
name: GPIOGRST
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: ADC 1 interface reset
|
|
name: ADC1RST
|
|
- bit_offset: 10
|
|
bit_size: 1
|
|
description: ADC 2 interface reset
|
|
name: ADC2RST
|
|
- bit_offset: 11
|
|
bit_size: 1
|
|
description: TIM1 timer reset
|
|
name: TIM1RST
|
|
- bit_offset: 12
|
|
bit_size: 1
|
|
description: SPI 1 reset
|
|
name: SPI1RST
|
|
- bit_offset: 13
|
|
bit_size: 1
|
|
description: TIM8 timer reset
|
|
name: TIM8RST
|
|
- bit_offset: 14
|
|
bit_size: 1
|
|
description: USART1 reset
|
|
name: USART1RST
|
|
- bit_offset: 15
|
|
bit_size: 1
|
|
description: ADC 3 interface reset
|
|
name: ADC3RST
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: TIM15 timer reset
|
|
name: TIM15RST
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: TIM16 timer reset
|
|
name: TIM16RST
|
|
- bit_offset: 18
|
|
bit_size: 1
|
|
description: TIM17 timer reset
|
|
name: TIM17RST
|
|
- bit_offset: 19
|
|
bit_size: 1
|
|
description: TIM9 timer reset
|
|
name: TIM9RST
|
|
- bit_offset: 20
|
|
bit_size: 1
|
|
description: TIM10 timer reset
|
|
name: TIM10RST
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: TIM11 timer reset
|
|
name: TIM11RST
|
|
fieldset/BDCR:
|
|
description: Backup domain control register (RCC_BDCR)
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: External Low Speed oscillator enable
|
|
name: LSEON
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: External Low Speed oscillator ready
|
|
name: LSERDY
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: External Low Speed oscillator bypass
|
|
name: LSEBYP
|
|
- bit_offset: 8
|
|
bit_size: 2
|
|
description: RTC clock source selection
|
|
enum: RTCSEL
|
|
name: RTCSEL
|
|
- bit_offset: 15
|
|
bit_size: 1
|
|
description: RTC clock enable
|
|
name: RTCEN
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: Backup domain software reset
|
|
name: BDRST
|
|
fieldset/CFGR:
|
|
description: Clock configuration register (RCC_CFGR)
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 2
|
|
description: System clock Switch
|
|
enum: SW
|
|
name: SW
|
|
- bit_offset: 2
|
|
bit_size: 2
|
|
description: System Clock Switch Status
|
|
enum_read: SWSR
|
|
name: SWS
|
|
- bit_offset: 4
|
|
bit_size: 4
|
|
description: AHB prescaler
|
|
enum: HPRE
|
|
name: HPRE
|
|
- bit_offset: 8
|
|
bit_size: 3
|
|
description: APB Low speed prescaler (APB1)
|
|
enum: PPRE1
|
|
name: PPRE1
|
|
- bit_offset: 11
|
|
bit_size: 3
|
|
description: APB High speed prescaler (APB2)
|
|
enum: PPRE1
|
|
name: PPRE2
|
|
- bit_offset: 14
|
|
bit_size: 2
|
|
description: ADC prescaler
|
|
enum: ADCPRE
|
|
name: ADCPRE
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: PLL entry clock source
|
|
enum: PLLSRC
|
|
name: PLLSRC
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: HSE divider for PLL entry
|
|
enum: PLLXTPRE
|
|
name: PLLXTPRE
|
|
- bit_offset: 18
|
|
bit_size: 4
|
|
description: PLL Multiplication Factor
|
|
enum: PLLMUL
|
|
name: PLLMUL
|
|
- bit_offset: 22
|
|
bit_size: 1
|
|
description: USB prescaler
|
|
enum: USBPRE
|
|
name: USBPRE
|
|
- bit_offset: 22
|
|
bit_size: 1
|
|
description: USB OTG FS prescaler
|
|
enum: OTGFSPRE
|
|
name: OTGFSPRE
|
|
- bit_offset: 24
|
|
bit_size: 3
|
|
description: Microcontroller clock output
|
|
enum: MCO
|
|
name: MCO
|
|
fieldset/CFGR2:
|
|
description: Clock configuration register2 (RCC_CFGR2)
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 4
|
|
description: PREDIV1 division factor
|
|
enum: PREDIV1
|
|
name: PREDIV1
|
|
- bit_offset: 4
|
|
bit_size: 4
|
|
description: PREDIV2 division factor
|
|
enum: PREDIV1
|
|
name: PREDIV2
|
|
- bit_offset: 8
|
|
bit_size: 4
|
|
description: PLL2 Multiplication Factor
|
|
enum: PLL2MUL
|
|
name: PLL2MUL
|
|
- bit_offset: 12
|
|
bit_size: 4
|
|
description: PLL3 Multiplication Factor
|
|
enum: PLL2MUL
|
|
name: PLL3MUL
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: PREDIV1 entry clock source
|
|
enum: PREDIV1SRC
|
|
name: PREDIV1SRC
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: I2S2 clock source
|
|
enum: I2S2SRC
|
|
name: I2S2SRC
|
|
- bit_offset: 18
|
|
bit_size: 1
|
|
description: I2S3 clock source
|
|
enum: I2S2SRC
|
|
name: I2S3SRC
|
|
fieldset/CIR:
|
|
description: Clock interrupt register (RCC_CIR)
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: LSI Ready Interrupt flag
|
|
name: LSIRDYF
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: LSE Ready Interrupt flag
|
|
name: LSERDYF
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: HSI Ready Interrupt flag
|
|
name: HSIRDYF
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: HSE Ready Interrupt flag
|
|
name: HSERDYF
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: PLL Ready Interrupt flag
|
|
name: PLLRDYF
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: PLL2 Ready Interrupt flag
|
|
name: PLL2RDYF
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: PLL3 Ready Interrupt flag
|
|
name: PLL3RDYF
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: Clock Security System Interrupt flag
|
|
name: CSSF
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: LSI Ready Interrupt Enable
|
|
name: LSIRDYIE
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: LSE Ready Interrupt Enable
|
|
name: LSERDYIE
|
|
- bit_offset: 10
|
|
bit_size: 1
|
|
description: HSI Ready Interrupt Enable
|
|
name: HSIRDYIE
|
|
- bit_offset: 11
|
|
bit_size: 1
|
|
description: HSE Ready Interrupt Enable
|
|
name: HSERDYIE
|
|
- bit_offset: 12
|
|
bit_size: 1
|
|
description: PLL Ready Interrupt Enable
|
|
name: PLLRDYIE
|
|
- bit_offset: 13
|
|
bit_size: 1
|
|
description: PLL2 Ready Interrupt Enable
|
|
name: PLL2RDYIE
|
|
- bit_offset: 14
|
|
bit_size: 1
|
|
description: PLL3 Ready Interrupt Enable
|
|
name: PLL3RDYIE
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: LSI Ready Interrupt Clear
|
|
name: LSIRDYC
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: LSE Ready Interrupt Clear
|
|
name: LSERDYC
|
|
- bit_offset: 18
|
|
bit_size: 1
|
|
description: HSI Ready Interrupt Clear
|
|
name: HSIRDYC
|
|
- bit_offset: 19
|
|
bit_size: 1
|
|
description: HSE Ready Interrupt Clear
|
|
name: HSERDYC
|
|
- bit_offset: 20
|
|
bit_size: 1
|
|
description: PLL Ready Interrupt Clear
|
|
name: PLLRDYC
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: PLL2 Ready Interrupt Clear
|
|
name: PLL2RDYC
|
|
- bit_offset: 22
|
|
bit_size: 1
|
|
description: PLL3 Ready Interrupt Clear
|
|
name: PLL3RDYC
|
|
- bit_offset: 23
|
|
bit_size: 1
|
|
description: Clock security system interrupt clear
|
|
name: CSSC
|
|
fieldset/CR:
|
|
description: Clock control register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: Internal High Speed clock enable
|
|
name: HSION
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: Internal High Speed clock ready flag
|
|
name: HSIRDY
|
|
- bit_offset: 3
|
|
bit_size: 5
|
|
description: Internal High Speed clock trimming
|
|
name: HSITRIM
|
|
- bit_offset: 8
|
|
bit_size: 8
|
|
description: Internal High Speed clock Calibration
|
|
name: HSICAL
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: External High Speed clock enable
|
|
name: HSEON
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: External High Speed clock ready flag
|
|
name: HSERDY
|
|
- bit_offset: 18
|
|
bit_size: 1
|
|
description: External High Speed clock Bypass
|
|
name: HSEBYP
|
|
- bit_offset: 19
|
|
bit_size: 1
|
|
description: Clock Security System enable
|
|
name: CSSON
|
|
- bit_offset: 24
|
|
bit_size: 1
|
|
description: PLL enable
|
|
name: PLLON
|
|
- bit_offset: 25
|
|
bit_size: 1
|
|
description: PLL clock ready flag
|
|
name: PLLRDY
|
|
- bit_offset: 26
|
|
bit_size: 1
|
|
description: PLL2 enable
|
|
name: PLL2ON
|
|
- bit_offset: 27
|
|
bit_size: 1
|
|
description: PLL2 clock ready flag
|
|
name: PLL2RDY
|
|
- bit_offset: 28
|
|
bit_size: 1
|
|
description: PLL3 enable
|
|
name: PLL3ON
|
|
- bit_offset: 29
|
|
bit_size: 1
|
|
description: PLL3 clock ready flag
|
|
name: PLL3RDY
|
|
fieldset/CSR:
|
|
description: Control/status register (RCC_CSR)
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: Internal low speed oscillator enable
|
|
name: LSION
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: Internal low speed oscillator ready
|
|
name: LSIRDY
|
|
- bit_offset: 24
|
|
bit_size: 1
|
|
description: Remove reset flag
|
|
name: RMVF
|
|
- bit_offset: 26
|
|
bit_size: 1
|
|
description: PIN reset flag
|
|
name: PINRSTF
|
|
- bit_offset: 27
|
|
bit_size: 1
|
|
description: POR/PDR reset flag
|
|
name: PORRSTF
|
|
- bit_offset: 28
|
|
bit_size: 1
|
|
description: Software reset flag
|
|
name: SFTRSTF
|
|
- bit_offset: 29
|
|
bit_size: 1
|
|
description: Independent watchdog reset flag
|
|
name: IWDGRSTF
|
|
- bit_offset: 30
|
|
bit_size: 1
|
|
description: Window watchdog reset flag
|
|
name: WWDGRSTF
|
|
- bit_offset: 31
|
|
bit_size: 1
|
|
description: Low-power reset flag
|
|
name: LPWRRSTF
|