block/RCC:
  description: Reset and clock control
  items:
  - byte_offset: 0
    description: Clock control register
    fieldset: CR
    name: CR
  - byte_offset: 4
    description: Clock configuration register (RCC_CFGR)
    fieldset: CFGR
    name: CFGR
  - byte_offset: 8
    description: Clock interrupt register (RCC_CIR)
    fieldset: CIR
    name: CIR
  - byte_offset: 12
    description: APB2 peripheral reset register (RCC_APB2RSTR)
    fieldset: APB2RSTR
    name: APB2RSTR
  - byte_offset: 16
    description: APB1 peripheral reset register (RCC_APB1RSTR)
    fieldset: APB1RSTR
    name: APB1RSTR
  - byte_offset: 20
    description: AHB Peripheral Clock enable register (RCC_AHBENR)
    fieldset: AHBENR
    name: AHBENR
  - byte_offset: 24
    description: APB2 peripheral clock enable register (RCC_APB2ENR)
    fieldset: APB2ENR
    name: APB2ENR
  - byte_offset: 28
    description: APB1 peripheral clock enable register (RCC_APB1ENR)
    fieldset: APB1ENR
    name: APB1ENR
  - byte_offset: 32
    description: Backup domain control register (RCC_BDCR)
    fieldset: BDCR
    name: BDCR
  - byte_offset: 36
    description: Control/status register (RCC_CSR)
    fieldset: CSR
    name: CSR
  - byte_offset: 40
    description: AHB peripheral clock reset register (RCC_AHBRSTR)
    fieldset: AHBRSTR
    name: AHBRSTR
  - byte_offset: 44
    description: Clock configuration register 2
    fieldset: CFGR2
    name: CFGR2
enum/ADCPRE:
  bit_size: 2
  variants:
  - description: PCLK2 divided by 2
    name: Div2
    value: 0
  - description: PCLK2 divided by 4
    name: Div4
    value: 1
  - description: PCLK2 divided by 8
    name: Div6
    value: 2
  - description: PCLK2 divided by 16
    name: Div8
    value: 3
enum/HPRE:
  bit_size: 4
  variants:
  - description: SYSCLK not divided
    name: Div1
    value: 0
  - description: SYSCLK divided by 2
    name: Div2
    value: 8
  - description: SYSCLK divided by 4
    name: Div4
    value: 9
  - description: SYSCLK divided by 8
    name: Div8
    value: 10
  - description: SYSCLK divided by 16
    name: Div16
    value: 11
  - description: SYSCLK divided by 64
    name: Div64
    value: 12
  - description: SYSCLK divided by 128
    name: Div128
    value: 13
  - description: SYSCLK divided by 256
    name: Div256
    value: 14
  - description: SYSCLK divided by 512
    name: Div512
    value: 15
enum/I2S2SRC:
  bit_size: 1
  variants:
  - description: System clock (SYSCLK) selected as I2S clock entry
    name: SYSCLK
    value: 0
  - description: PLL3 VCO clock selected as I2S clock entry
    name: PLL3
    value: 1
enum/MCO:
  bit_size: 4
  variants:
  - description: MCO output disabled, no clock on MCO
    name: NoMCO
    value: 0
  - description: System clock selected
    name: SYSCLK
    value: 4
  - description: HSI oscillator clock selected
    name: HSI
    value: 5
  - description: HSE oscillator clock selected
    name: HSE
    value: 6
  - description: PLL clock selected (divided by 1 or 2, depending en PLLNODIV)
    name: PLL
    value: 7
enum/OTGFSPRE:
  bit_size: 1
  variants:
  - description: PLL clock is divided by 1.5
    name: DIV1_5
    value: 0
  - description: PLL clock is not divided
    name: DIV1
    value: 1
enum/PLL2MUL:
  bit_size: 4
  variants:
  - description: PLL clock entry x8
    name: Mul8
    value: 6
  - description: PLL clock entry x9
    name: Mul9
    value: 7
  - description: PLL clock entry x10
    name: Mul10
    value: 8
  - description: PLL clock entry x11
    name: Mul11
    value: 9
  - description: PLL clock entry x12
    name: Mul12
    value: 10
  - description: PLL clock entry x13
    name: Mul13
    value: 11
  - description: PLL clock entry x14
    name: Mul14
    value: 12
  - description: PLL clock entry x16
    name: Mul16
    value: 14
  - description: PLL clock entry x20
    name: Mul20
    value: 15
enum/PLLMUL:
  bit_size: 4
  variants:
  - description: PLL input clock x2
    name: Mul2
    value: 0
  - description: PLL input clock x3
    name: Mul3
    value: 1
  - description: PLL input clock x4
    name: Mul4
    value: 2
  - description: PLL input clock x5
    name: Mul5
    value: 3
  - description: PLL input clock x6
    name: Mul6
    value: 4
  - description: PLL input clock x7
    name: Mul7
    value: 5
  - description: PLL input clock x8
    name: Mul8
    value: 6
  - description: PLL input clock x9
    name: Mul9
    value: 7
  - description: PLL input clock x10
    name: Mul10
    value: 8
  - description: PLL input clock x11
    name: Mul11
    value: 9
  - description: PLL input clock x12
    name: Mul12
    value: 10
  - description: PLL input clock x13
    name: Mul13
    value: 11
  - description: PLL input clock x14
    name: Mul14
    value: 12
  - description: PLL input clock x15
    name: Mul15
    value: 13
  - description: PLL input clock x16
    name: Mul16
    value: 14
  - description: PLL input clock x16
    name: Mul16x
    value: 15
enum/PLLSRC:
  bit_size: 1
  variants:
  - description: HSI divided by 2 selected as PLL input clock
    name: HSI_Div2
    value: 0
  - description: HSE divided by PREDIV selected as PLL input clock
    name: HSE_Div_PREDIV
    value: 1
enum/PLLXTPRE:
  bit_size: 1
  variants:
  - description: HSE clock not divided
    name: Div1
    value: 0
  - description: HSE clock divided by 2
    name: Div2
    value: 1
enum/PPRE1:
  bit_size: 3
  variants:
  - description: HCLK not divided
    name: Div1
    value: 0
  - description: HCLK divided by 2
    name: Div2
    value: 4
  - description: HCLK divided by 4
    name: Div4
    value: 5
  - description: HCLK divided by 8
    name: Div8
    value: 6
  - description: HCLK divided by 16
    name: Div16
    value: 7
enum/PREDIV1:
  bit_size: 4
  variants:
  - description: PREDIV input clock not divided
    name: Div1
    value: 0
  - description: PREDIV input clock divided by 2
    name: Div2
    value: 1
  - description: PREDIV input clock divided by 3
    name: Div3
    value: 2
  - description: PREDIV input clock divided by 4
    name: Div4
    value: 3
  - description: PREDIV input clock divided by 5
    name: Div5
    value: 4
  - description: PREDIV input clock divided by 6
    name: Div6
    value: 5
  - description: PREDIV input clock divided by 7
    name: Div7
    value: 6
  - description: PREDIV input clock divided by 8
    name: Div8
    value: 7
  - description: PREDIV input clock divided by 9
    name: Div9
    value: 8
  - description: PREDIV input clock divided by 10
    name: Div10
    value: 9
  - description: PREDIV input clock divided by 11
    name: Div11
    value: 10
  - description: PREDIV input clock divided by 12
    name: Div12
    value: 11
  - description: PREDIV input clock divided by 13
    name: Div13
    value: 12
  - description: PREDIV input clock divided by 14
    name: Div14
    value: 13
  - description: PREDIV input clock divided by 15
    name: Div15
    value: 14
  - description: PREDIV input clock divided by 16
    name: Div16
    value: 15
enum/PREDIV1SRC:
  bit_size: 1
  variants:
  - description: HSE oscillator clock selected as PREDIV1 clock entry
    name: HSE
    value: 0
  - description: PLL2 selected as PREDIV1 clock entry
    name: PLL2
    value: 1
enum/RTCSEL:
  bit_size: 2
  variants:
  - description: No clock
    name: NoClock
    value: 0
  - description: LSE oscillator clock used as RTC clock
    name: LSE
    value: 1
  - description: LSI oscillator clock used as RTC clock
    name: LSI
    value: 2
  - description: HSE oscillator clock divided by a prescaler used as RTC clock
    name: HSE
    value: 3
enum/SW:
  bit_size: 2
  variants:
  - description: HSI selected as system clock
    name: HSI
    value: 0
  - description: HSE selected as system clock
    name: HSE
    value: 1
  - description: PLL selected as system clock
    name: PLL
    value: 2
enum/SWSR:
  bit_size: 2
  variants:
  - description: HSI oscillator used as system clock
    name: HSI
    value: 0
  - description: HSE oscillator used as system clock
    name: HSE
    value: 1
  - description: PLL used as system clock
    name: PLL
    value: 2
enum/USBPRE:
  bit_size: 1
  variants:
  - description: PLL clock is divided by 1.5
    name: DIV1_5
    value: 0
  - description: PLL clock is not divided
    name: DIV1
    value: 1
fieldset/AHBENR:
  description: AHB Peripheral Clock enable register (RCC_AHBENR)
  fields:
  - bit_offset: 0
    bit_size: 1
    description: DMA1 clock enable
    name: DMA1EN
  - bit_offset: 1
    bit_size: 1
    description: DMA2 clock enable
    name: DMA2EN
  - bit_offset: 2
    bit_size: 1
    description: SRAM interface clock enable
    name: SRAMEN
  - bit_offset: 4
    bit_size: 1
    description: FLITF clock enable
    name: FLITFEN
  - bit_offset: 6
    bit_size: 1
    description: CRC clock enable
    name: CRCEN
  - bit_offset: 8
    bit_size: 1
    description: FSMC clock enable
    name: FSMCEN
  - bit_offset: 10
    bit_size: 1
    description: SDIO clock enable
    name: SDIOEN
  - bit_offset: 12
    bit_size: 1
    description: USB OTG FS clock enable
    name: OTGFSEN
  - bit_offset: 14
    bit_size: 1
    description: Ethernet MAC clock enable
    name: ETHMACEN
  - bit_offset: 15
    bit_size: 1
    description: Ethernet MAC TX clock enable
    name: ETHMACTXEN
  - bit_offset: 16
    bit_size: 1
    description: Ethernet MAC RX clock enable
    name: ETHMACRXEN
fieldset/AHBRSTR:
  description: AHB peripheral clock reset register (RCC_AHBRSTR)
  fields:
  - bit_offset: 12
    bit_size: 1
    description: USB OTG FS reset
    name: OTGFSRST
  - bit_offset: 14
    bit_size: 1
    description: Ethernet MAC reset
    name: ETHMACRST
fieldset/APB1ENR:
  description: APB1 peripheral clock enable register (RCC_APB1ENR)
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Timer 2 clock enable
    name: TIM2EN
  - bit_offset: 1
    bit_size: 1
    description: Timer 3 clock enable
    name: TIM3EN
  - bit_offset: 2
    bit_size: 1
    description: Timer 4 clock enable
    name: TIM4EN
  - bit_offset: 3
    bit_size: 1
    description: Timer 5 clock enable
    name: TIM5EN
  - bit_offset: 4
    bit_size: 1
    description: Timer 6 clock enable
    name: TIM6EN
  - bit_offset: 5
    bit_size: 1
    description: Timer 7 clock enable
    name: TIM7EN
  - bit_offset: 6
    bit_size: 1
    description: Timer 12 clock enable
    name: TIM12EN
  - bit_offset: 7
    bit_size: 1
    description: Timer 13 clock enable
    name: TIM13EN
  - bit_offset: 8
    bit_size: 1
    description: Timer 14 clock enable
    name: TIM14EN
  - bit_offset: 11
    bit_size: 1
    description: Window watchdog clock enable
    name: WWDGEN
  - bit_offset: 14
    bit_size: 1
    description: SPI 2 clock enable
    name: SPI2EN
  - bit_offset: 15
    bit_size: 1
    description: SPI 3 clock enable
    name: SPI3EN
  - bit_offset: 17
    bit_size: 1
    description: USART 2 clock enable
    name: USART2EN
  - bit_offset: 18
    bit_size: 1
    description: USART 3 clock enable
    name: USART3EN
  - bit_offset: 19
    bit_size: 1
    description: UART 4 clock enable
    name: UART4EN
  - bit_offset: 20
    bit_size: 1
    description: UART 5 clock enable
    name: UART5EN
  - bit_offset: 21
    bit_size: 1
    description: I2C 1 clock enable
    name: I2C1EN
  - bit_offset: 22
    bit_size: 1
    description: I2C 2 clock enable
    name: I2C2EN
  - bit_offset: 23
    bit_size: 1
    description: USB clock enable
    name: USBEN
  - bit_offset: 25
    bit_size: 1
    description: CAN clock enable
    name: CANEN
  - bit_offset: 25
    bit_size: 1
    description: CAN1 clock enable
    name: CAN1EN
  - bit_offset: 26
    bit_size: 1
    description: CAN2 clock enable
    name: CAN2EN
  - bit_offset: 27
    bit_size: 1
    description: Backup interface clock enable
    name: BKPEN
  - bit_offset: 28
    bit_size: 1
    description: Power interface clock enable
    name: PWREN
  - bit_offset: 29
    bit_size: 1
    description: DAC interface clock enable
    name: DACEN
  - bit_offset: 30
    bit_size: 1
    description: CEC clock enable
    name: CECEN
fieldset/APB1RSTR:
  description: APB1 peripheral reset register (RCC_APB1RSTR)
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Timer 2 reset
    name: TIM2RST
  - bit_offset: 1
    bit_size: 1
    description: Timer 3 reset
    name: TIM3RST
  - bit_offset: 2
    bit_size: 1
    description: Timer 4 reset
    name: TIM4RST
  - bit_offset: 3
    bit_size: 1
    description: Timer 5 reset
    name: TIM5RST
  - bit_offset: 4
    bit_size: 1
    description: Timer 6 reset
    name: TIM6RST
  - bit_offset: 5
    bit_size: 1
    description: Timer 7 reset
    name: TIM7RST
  - bit_offset: 6
    bit_size: 1
    description: Timer 12 reset
    name: TIM12RST
  - bit_offset: 7
    bit_size: 1
    description: Timer 13 reset
    name: TIM13RST
  - bit_offset: 8
    bit_size: 1
    description: Timer 14 reset
    name: TIM14RST
  - bit_offset: 11
    bit_size: 1
    description: Window watchdog reset
    name: WWDGRST
  - bit_offset: 14
    bit_size: 1
    description: SPI2 reset
    name: SPI2RST
  - bit_offset: 15
    bit_size: 1
    description: SPI3 reset
    name: SPI3RST
  - bit_offset: 17
    bit_size: 1
    description: USART 2 reset
    name: USART2RST
  - bit_offset: 18
    bit_size: 1
    description: USART 3 reset
    name: USART3RST
  - bit_offset: 19
    bit_size: 1
    description: USART 4 reset
    name: UART4RST
  - bit_offset: 20
    bit_size: 1
    description: USART 5 reset
    name: UART5RST
  - bit_offset: 21
    bit_size: 1
    description: I2C1 reset
    name: I2C1RST
  - bit_offset: 22
    bit_size: 1
    description: I2C2 reset
    name: I2C2RST
  - bit_offset: 23
    bit_size: 1
    description: USB reset
    name: USBRST
  - bit_offset: 25
    bit_size: 1
    description: CAN reset
    name: CANRST
  - bit_offset: 25
    bit_size: 1
    description: CAN1 reset
    name: CAN1RST
  - bit_offset: 26
    bit_size: 1
    description: CAN2 reset
    name: CAN2RST
  - bit_offset: 27
    bit_size: 1
    description: Backup interface reset
    name: BKPRST
  - bit_offset: 28
    bit_size: 1
    description: Power interface reset
    name: PWRRST
  - bit_offset: 29
    bit_size: 1
    description: DAC interface reset
    name: DACRST
  - bit_offset: 30
    bit_size: 1
    description: CEC reset
    name: CECRST
fieldset/APB2ENR:
  description: APB2 peripheral clock enable register (RCC_APB2ENR)
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Alternate function I/O clock enable
    name: AFIOEN
  - bit_offset: 2
    bit_size: 1
    description: I/O port A clock enable
    name: GPIOAEN
  - bit_offset: 3
    bit_size: 1
    description: I/O port B clock enable
    name: GPIOBEN
  - bit_offset: 4
    bit_size: 1
    description: I/O port C clock enable
    name: GPIOCEN
  - bit_offset: 5
    bit_size: 1
    description: I/O port D clock enable
    name: GPIODEN
  - bit_offset: 6
    bit_size: 1
    description: I/O port E clock enable
    name: GPIOEEN
  - bit_offset: 7
    bit_size: 1
    description: I/O port F clock enable
    name: GPIOFEN
  - bit_offset: 8
    bit_size: 1
    description: I/O port G clock enable
    name: GPIOGEN
  - bit_offset: 9
    bit_size: 1
    description: ADC 1 interface clock enable
    name: ADC1EN
  - bit_offset: 10
    bit_size: 1
    description: ADC 2 interface clock enable
    name: ADC2EN
  - bit_offset: 11
    bit_size: 1
    description: TIM1 Timer clock enable
    name: TIM1EN
  - bit_offset: 12
    bit_size: 1
    description: SPI 1 clock enable
    name: SPI1EN
  - bit_offset: 13
    bit_size: 1
    description: TIM8 Timer clock enable
    name: TIM8EN
  - bit_offset: 14
    bit_size: 1
    description: USART1 clock enable
    name: USART1EN
  - bit_offset: 15
    bit_size: 1
    description: ADC3 interface clock enable
    name: ADC3EN
  - bit_offset: 16
    bit_size: 1
    description: TIM15 Timer clock enable
    name: TIM15EN
  - bit_offset: 17
    bit_size: 1
    description: TIM16 Timer clock enable
    name: TIM16EN
  - bit_offset: 18
    bit_size: 1
    description: TIM17 Timer clock enable
    name: TIM17EN
  - bit_offset: 19
    bit_size: 1
    description: TIM9 Timer clock enable
    name: TIM9EN
  - bit_offset: 20
    bit_size: 1
    description: TIM10 Timer clock enable
    name: TIM10EN
  - bit_offset: 21
    bit_size: 1
    description: TIM11 Timer clock enable
    name: TIM11EN
fieldset/APB2RSTR:
  description: APB2 peripheral reset register (RCC_APB2RSTR)
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Alternate function I/O reset
    name: AFIORST
  - bit_offset: 2
    bit_size: 1
    description: IO port A reset
    name: GPIOARST
  - bit_offset: 3
    bit_size: 1
    description: IO port B reset
    name: GPIOBRST
  - bit_offset: 4
    bit_size: 1
    description: IO port C reset
    name: GPIOCRST
  - bit_offset: 5
    bit_size: 1
    description: IO port D reset
    name: GPIODRST
  - bit_offset: 6
    bit_size: 1
    description: IO port E reset
    name: GPIOERST
  - bit_offset: 7
    bit_size: 1
    description: IO port F reset
    name: GPIOFRST
  - bit_offset: 8
    bit_size: 1
    description: IO port G reset
    name: GPIOGRST
  - bit_offset: 9
    bit_size: 1
    description: ADC 1 interface reset
    name: ADC1RST
  - bit_offset: 10
    bit_size: 1
    description: ADC 2 interface reset
    name: ADC2RST
  - bit_offset: 11
    bit_size: 1
    description: TIM1 timer reset
    name: TIM1RST
  - bit_offset: 12
    bit_size: 1
    description: SPI 1 reset
    name: SPI1RST
  - bit_offset: 13
    bit_size: 1
    description: TIM8 timer reset
    name: TIM8RST
  - bit_offset: 14
    bit_size: 1
    description: USART1 reset
    name: USART1RST
  - bit_offset: 15
    bit_size: 1
    description: ADC 3 interface reset
    name: ADC3RST
  - bit_offset: 16
    bit_size: 1
    description: TIM15 timer reset
    name: TIM15RST
  - bit_offset: 17
    bit_size: 1
    description: TIM16 timer reset
    name: TIM16RST
  - bit_offset: 18
    bit_size: 1
    description: TIM17 timer reset
    name: TIM17RST
  - bit_offset: 19
    bit_size: 1
    description: TIM9 timer reset
    name: TIM9RST
  - bit_offset: 20
    bit_size: 1
    description: TIM10 timer reset
    name: TIM10RST
  - bit_offset: 21
    bit_size: 1
    description: TIM11 timer reset
    name: TIM11RST
fieldset/BDCR:
  description: Backup domain control register (RCC_BDCR)
  fields:
  - bit_offset: 0
    bit_size: 1
    description: External Low Speed oscillator enable
    name: LSEON
  - bit_offset: 1
    bit_size: 1
    description: External Low Speed oscillator ready
    name: LSERDY
  - bit_offset: 2
    bit_size: 1
    description: External Low Speed oscillator bypass
    name: LSEBYP
  - bit_offset: 8
    bit_size: 2
    description: RTC clock source selection
    enum: RTCSEL
    name: RTCSEL
  - bit_offset: 15
    bit_size: 1
    description: RTC clock enable
    name: RTCEN
  - bit_offset: 16
    bit_size: 1
    description: Backup domain software reset
    name: BDRST
fieldset/CFGR:
  description: Clock configuration register (RCC_CFGR)
  fields:
  - bit_offset: 0
    bit_size: 2
    description: System clock Switch
    enum: SW
    name: SW
  - bit_offset: 2
    bit_size: 2
    description: System Clock Switch Status
    enum_read: SWSR
    name: SWS
  - bit_offset: 4
    bit_size: 4
    description: AHB prescaler
    enum: HPRE
    name: HPRE
  - bit_offset: 8
    bit_size: 3
    description: APB Low speed prescaler (APB1)
    enum: PPRE1
    name: PPRE1
  - bit_offset: 11
    bit_size: 3
    description: APB High speed prescaler (APB2)
    enum: PPRE1
    name: PPRE2
  - bit_offset: 14
    bit_size: 2
    description: ADC prescaler
    enum: ADCPRE
    name: ADCPRE
  - bit_offset: 16
    bit_size: 1
    description: PLL entry clock source
    enum: PLLSRC
    name: PLLSRC
  - bit_offset: 17
    bit_size: 1
    description: HSE divider for PLL entry
    enum: PLLXTPRE
    name: PLLXTPRE
  - bit_offset: 18
    bit_size: 4
    description: PLL Multiplication Factor
    enum: PLLMUL
    name: PLLMUL
  - bit_offset: 22
    bit_size: 1
    description: USB prescaler
    enum: USBPRE
    name: USBPRE
  - bit_offset: 22
    bit_size: 1
    description: USB OTG FS prescaler
    enum: OTGFSPRE
    name: OTGFSPRE
  - bit_offset: 24
    bit_size: 3
    description: Microcontroller clock output
    enum: MCO
    name: MCO
fieldset/CFGR2:
  description: Clock configuration register2 (RCC_CFGR2)
  fields:
  - bit_offset: 0
    bit_size: 4
    description: PREDIV1 division factor
    enum: PREDIV1
    name: PREDIV1
  - bit_offset: 4
    bit_size: 4
    description: PREDIV2 division factor
    enum: PREDIV1
    name: PREDIV2
  - bit_offset: 8
    bit_size: 4
    description: PLL2 Multiplication Factor
    enum: PLL2MUL
    name: PLL2MUL
  - bit_offset: 12
    bit_size: 4
    description: PLL3 Multiplication Factor
    enum: PLL2MUL
    name: PLL3MUL
  - bit_offset: 16
    bit_size: 1
    description: PREDIV1 entry clock source
    enum: PREDIV1SRC
    name: PREDIV1SRC
  - bit_offset: 17
    bit_size: 1
    description: I2S2 clock source
    enum: I2S2SRC
    name: I2S2SRC
  - bit_offset: 18
    bit_size: 1
    description: I2S3 clock source
    enum: I2S2SRC
    name: I2S3SRC
fieldset/CIR:
  description: Clock interrupt register (RCC_CIR)
  fields:
  - bit_offset: 0
    bit_size: 1
    description: LSI Ready Interrupt flag
    name: LSIRDYF
  - bit_offset: 1
    bit_size: 1
    description: LSE Ready Interrupt flag
    name: LSERDYF
  - bit_offset: 2
    bit_size: 1
    description: HSI Ready Interrupt flag
    name: HSIRDYF
  - bit_offset: 3
    bit_size: 1
    description: HSE Ready Interrupt flag
    name: HSERDYF
  - bit_offset: 4
    bit_size: 1
    description: PLL Ready Interrupt flag
    name: PLLRDYF
  - bit_offset: 5
    bit_size: 1
    description: PLL2 Ready Interrupt flag
    name: PLL2RDYF
  - bit_offset: 6
    bit_size: 1
    description: PLL3 Ready Interrupt flag
    name: PLL3RDYF
  - bit_offset: 7
    bit_size: 1
    description: Clock Security System Interrupt flag
    name: CSSF
  - bit_offset: 8
    bit_size: 1
    description: LSI Ready Interrupt Enable
    name: LSIRDYIE
  - bit_offset: 9
    bit_size: 1
    description: LSE Ready Interrupt Enable
    name: LSERDYIE
  - bit_offset: 10
    bit_size: 1
    description: HSI Ready Interrupt Enable
    name: HSIRDYIE
  - bit_offset: 11
    bit_size: 1
    description: HSE Ready Interrupt Enable
    name: HSERDYIE
  - bit_offset: 12
    bit_size: 1
    description: PLL Ready Interrupt Enable
    name: PLLRDYIE
  - bit_offset: 13
    bit_size: 1
    description: PLL2 Ready Interrupt Enable
    name: PLL2RDYIE
  - bit_offset: 14
    bit_size: 1
    description: PLL3 Ready Interrupt Enable
    name: PLL3RDYIE
  - bit_offset: 16
    bit_size: 1
    description: LSI Ready Interrupt Clear
    name: LSIRDYC
  - bit_offset: 17
    bit_size: 1
    description: LSE Ready Interrupt Clear
    name: LSERDYC
  - bit_offset: 18
    bit_size: 1
    description: HSI Ready Interrupt Clear
    name: HSIRDYC
  - bit_offset: 19
    bit_size: 1
    description: HSE Ready Interrupt Clear
    name: HSERDYC
  - bit_offset: 20
    bit_size: 1
    description: PLL Ready Interrupt Clear
    name: PLLRDYC
  - bit_offset: 21
    bit_size: 1
    description: PLL2 Ready Interrupt Clear
    name: PLL2RDYC
  - bit_offset: 22
    bit_size: 1
    description: PLL3 Ready Interrupt Clear
    name: PLL3RDYC
  - bit_offset: 23
    bit_size: 1
    description: Clock security system interrupt clear
    name: CSSC
fieldset/CR:
  description: Clock control register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Internal High Speed clock enable
    name: HSION
  - bit_offset: 1
    bit_size: 1
    description: Internal High Speed clock ready flag
    name: HSIRDY
  - bit_offset: 3
    bit_size: 5
    description: Internal High Speed clock trimming
    name: HSITRIM
  - bit_offset: 8
    bit_size: 8
    description: Internal High Speed clock Calibration
    name: HSICAL
  - bit_offset: 16
    bit_size: 1
    description: External High Speed clock enable
    name: HSEON
  - bit_offset: 17
    bit_size: 1
    description: External High Speed clock ready flag
    name: HSERDY
  - bit_offset: 18
    bit_size: 1
    description: External High Speed clock Bypass
    name: HSEBYP
  - bit_offset: 19
    bit_size: 1
    description: Clock Security System enable
    name: CSSON
  - bit_offset: 24
    bit_size: 1
    description: PLL enable
    name: PLLON
  - bit_offset: 25
    bit_size: 1
    description: PLL clock ready flag
    name: PLLRDY
  - bit_offset: 26
    bit_size: 1
    description: PLL2 enable
    name: PLL2ON
  - bit_offset: 27
    bit_size: 1
    description: PLL2 clock ready flag
    name: PLL2RDY
  - bit_offset: 28
    bit_size: 1
    description: PLL3 enable
    name: PLL3ON
  - bit_offset: 29
    bit_size: 1
    description: PLL3 clock ready flag
    name: PLL3RDY
fieldset/CSR:
  description: Control/status register (RCC_CSR)
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Internal low speed oscillator enable
    name: LSION
  - bit_offset: 1
    bit_size: 1
    description: Internal low speed oscillator ready
    name: LSIRDY
  - bit_offset: 24
    bit_size: 1
    description: Remove reset flag
    name: RMVF
  - bit_offset: 26
    bit_size: 1
    description: PIN reset flag
    name: PINRSTF
  - bit_offset: 27
    bit_size: 1
    description: POR/PDR reset flag
    name: PORRSTF
  - bit_offset: 28
    bit_size: 1
    description: Software reset flag
    name: SFTRSTF
  - bit_offset: 29
    bit_size: 1
    description: Independent watchdog reset flag
    name: IWDGRSTF
  - bit_offset: 30
    bit_size: 1
    description: Window watchdog reset flag
    name: WWDGRSTF
  - bit_offset: 31
    bit_size: 1
    description: Low-power reset flag
    name: LPWRRSTF