920 lines
29 KiB
YAML
920 lines
29 KiB
YAML
block/DMA2D:
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description: DMA2D
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items:
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- byte_offset: 0
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description: DMA2D control register
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fieldset: CR
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name: CR
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- access: Read
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byte_offset: 4
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description: DMA2D Interrupt Status Register
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fieldset: ISR
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name: ISR
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- byte_offset: 8
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description: DMA2D interrupt flag clear register
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fieldset: IFCR
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name: IFCR
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- byte_offset: 12
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description: DMA2D foreground memory address register
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fieldset: FGMAR
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name: FGMAR
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- byte_offset: 16
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description: DMA2D foreground offset register
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fieldset: FGOR
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name: FGOR
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- byte_offset: 20
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description: DMA2D background memory address register
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fieldset: BGMAR
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name: BGMAR
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- byte_offset: 24
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description: DMA2D background offset register
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fieldset: BGOR
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name: BGOR
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- byte_offset: 28
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description: DMA2D foreground PFC control register
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fieldset: FGPFCCR
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name: FGPFCCR
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- byte_offset: 32
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description: DMA2D foreground color register
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fieldset: FGCOLR
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name: FGCOLR
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- byte_offset: 36
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description: DMA2D background PFC control register
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fieldset: BGPFCCR
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name: BGPFCCR
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- byte_offset: 40
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description: DMA2D background color register
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fieldset: BGCOLR
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name: BGCOLR
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- byte_offset: 44
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description: DMA2D foreground CLUT memory address register
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fieldset: FGCMAR
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name: FGCMAR
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- byte_offset: 48
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description: DMA2D background CLUT memory address register
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fieldset: BGCMAR
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name: BGCMAR
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- byte_offset: 52
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description: DMA2D output PFC control register
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fieldset: OPFCCR
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name: OPFCCR
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- byte_offset: 56
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description: DMA2D output color register
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fieldset: OCOLR
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name: OCOLR
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- byte_offset: 60
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description: DMA2D output memory address register
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fieldset: OMAR
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name: OMAR
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- byte_offset: 64
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description: DMA2D output offset register
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fieldset: OOR
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name: OOR
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- byte_offset: 68
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description: DMA2D number of line register
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fieldset: NLR
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name: NLR
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- byte_offset: 72
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description: DMA2D line watermark register
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fieldset: LWR
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name: LWR
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- byte_offset: 76
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description: DMA2D AXI master timer configuration register
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fieldset: AMTCR
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name: AMTCR
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enum/ABORT:
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bit_size: 1
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variants:
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- description: Transfer abort requested
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name: AbortRequest
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value: 1
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enum/BGPFCCR_AI:
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bit_size: 1
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variants:
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- description: Regular alpha
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name: RegularAlpha
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value: 0
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- description: Inverted alpha
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name: InvertedAlpha
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value: 1
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enum/BGPFCCR_AM:
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bit_size: 2
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variants:
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- description: No modification of alpha channel
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name: NoModify
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value: 0
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- description: Replace with value in ALPHA[7:0]
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name: Replace
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value: 1
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- description: Multiply with value in ALPHA[7:0]
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name: Multiply
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value: 2
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enum/BGPFCCR_CCM:
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bit_size: 1
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variants:
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- description: CLUT color format ARGB8888
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name: ARGB8888
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value: 0
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- description: CLUT color format RGB888
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name: RGB888
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value: 1
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enum/BGPFCCR_CM:
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bit_size: 4
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variants:
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- description: Color mode ARGB8888
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name: ARGB8888
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value: 0
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- description: Color mode RGB888
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name: RGB888
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value: 1
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- description: Color mode RGB565
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name: RGB565
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value: 2
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- description: Color mode ARGB1555
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name: ARGB1555
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value: 3
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- description: Color mode ARGB4444
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name: ARGB4444
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value: 4
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- description: Color mode L8
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name: L8
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value: 5
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- description: Color mode AL44
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name: AL44
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value: 6
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- description: Color mode AL88
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name: AL88
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value: 7
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- description: Color mode L4
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name: L4
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value: 8
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- description: Color mode A8
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name: A8
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value: 9
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- description: Color mode A4
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name: A4
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value: 10
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enum/BGPFCCR_RBS:
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bit_size: 1
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variants:
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- description: No Red Blue Swap (RGB or ARGB)
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name: Regular
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value: 0
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- description: Red Blue Swap (BGR or ABGR)
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name: Swap
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value: 1
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enum/BGPFCCR_START:
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bit_size: 1
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variants:
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- description: Start the automatic loading of the CLUT
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name: Start
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value: 1
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enum/CAECIF:
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bit_size: 1
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variants:
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- description: Clear the CAEIF flag in the ISR register
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name: Clear
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value: 1
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enum/CAEIE:
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bit_size: 1
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variants:
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- description: CAE interrupt disabled
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name: Disabled
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value: 0
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- description: CAE interrupt enabled
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name: Enabled
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value: 1
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enum/CCEIF:
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bit_size: 1
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variants:
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- description: Clear the CEIF flag in the ISR register
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name: Clear
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value: 1
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enum/CCTCIF:
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bit_size: 1
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variants:
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- description: Clear the CTCIF flag in the ISR register
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name: Clear
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value: 1
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enum/CEIE:
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bit_size: 1
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variants:
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- description: CE interrupt disabled
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name: Disabled
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value: 0
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- description: CE interrupt enabled
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name: Enabled
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value: 1
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enum/CR_START:
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bit_size: 1
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variants:
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- description: Launch the DMA2D
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name: Start
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value: 1
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enum/CTCIE:
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bit_size: 1
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variants:
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- description: CTC interrupt disabled
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name: Disabled
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value: 0
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- description: CTC interrupt enabled
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name: Enabled
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value: 1
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enum/CTCIF:
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bit_size: 1
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variants:
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- description: Clear the TCIF flag in the ISR register
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name: Clear
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value: 1
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enum/CTEIF:
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bit_size: 1
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variants:
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- description: Clear the TEIF flag in the ISR register
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name: Clear
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value: 1
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enum/CTWIF:
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bit_size: 1
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variants:
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- description: Clear the TWIF flag in the ISR register
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name: Clear
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value: 1
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enum/EN:
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bit_size: 1
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variants:
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- description: Disabled AHB/AXI dead-time functionality
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name: Disabled
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value: 0
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- description: Enabled AHB/AXI dead-time functionality
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name: Enabled
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value: 1
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enum/FGPFCCR_AI:
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bit_size: 1
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variants:
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- description: Regular alpha
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name: RegularAlpha
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value: 0
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- description: Inverted alpha
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name: InvertedAlpha
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value: 1
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enum/FGPFCCR_AM:
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bit_size: 2
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variants:
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- description: No modification of alpha channel
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name: NoModify
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value: 0
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- description: Replace with value in ALPHA[7:0]
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name: Replace
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value: 1
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- description: Multiply with value in ALPHA[7:0]
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name: Multiply
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value: 2
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enum/FGPFCCR_CCM:
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bit_size: 1
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variants:
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- description: CLUT color format ARGB8888
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name: ARGB8888
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value: 0
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- description: CLUT color format RGB888
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name: RGB888
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value: 1
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enum/FGPFCCR_CM:
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bit_size: 4
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variants:
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- description: Color mode ARGB8888
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name: ARGB8888
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value: 0
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- description: Color mode RGB888
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name: RGB888
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value: 1
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- description: Color mode RGB565
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name: RGB565
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value: 2
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- description: Color mode ARGB1555
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name: ARGB1555
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value: 3
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- description: Color mode ARGB4444
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name: ARGB4444
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value: 4
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- description: Color mode L8
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name: L8
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value: 5
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- description: Color mode AL44
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name: AL44
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value: 6
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- description: Color mode AL88
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name: AL88
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value: 7
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- description: Color mode L4
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name: L4
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value: 8
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- description: Color mode A8
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name: A8
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value: 9
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- description: Color mode A4
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name: A4
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value: 10
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- description: Color mode YCbCr
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name: YCbCr
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value: 11
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enum/FGPFCCR_RBS:
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bit_size: 1
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variants:
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- description: No Red Blue Swap (RGB or ARGB)
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name: Regular
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value: 0
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- description: Red Blue Swap (BGR or ABGR)
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name: Swap
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value: 1
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enum/FGPFCCR_START:
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bit_size: 1
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variants:
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- description: Start the automatic loading of the CLUT
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name: Start
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value: 1
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enum/MODE:
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bit_size: 2
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variants:
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- description: Memory-to-memory (FG fetch only)
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name: MemoryToMemory
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value: 0
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- description: Memory-to-memory with PFC (FG fetch only with FG PFC active)
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name: MemoryToMemoryPFC
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value: 1
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- description: Memory-to-memory with blending (FG and BG fetch with PFC and blending)
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name: MemoryToMemoryPFCBlending
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value: 2
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- description: Register-to-memory
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name: RegisterToMemory
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value: 3
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enum/OPFCCR_AI:
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bit_size: 1
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variants:
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- description: Regular alpha
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name: RegularAlpha
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value: 0
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- description: Inverted alpha
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name: InvertedAlpha
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value: 1
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enum/OPFCCR_CM:
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bit_size: 3
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variants:
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- description: ARGB8888
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name: ARGB8888
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value: 0
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- description: RGB888
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name: RGB888
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value: 1
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- description: RGB565
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name: RGB565
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value: 2
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- description: ARGB1555
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name: ARGB1555
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value: 3
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- description: ARGB4444
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name: ARGB4444
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value: 4
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enum/OPFCCR_RBS:
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bit_size: 1
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variants:
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- description: No Red Blue Swap (RGB or ARGB)
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name: Regular
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value: 0
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- description: Red Blue Swap (BGR or ABGR)
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name: Swap
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value: 1
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enum/SB:
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bit_size: 1
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variants:
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- description: Regular byte order
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name: Regular
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value: 0
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- description: Bytes are swapped two by two
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name: SwapBytes
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value: 1
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enum/SUSP:
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bit_size: 1
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variants:
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- description: Transfer not suspended
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name: NotSuspended
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value: 0
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- description: Transfer suspended
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name: Suspended
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value: 1
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enum/TCIE:
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bit_size: 1
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variants:
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- description: TC interrupt disabled
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name: Disabled
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value: 0
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- description: TC interrupt enabled
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name: Enabled
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value: 1
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enum/TEIE:
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bit_size: 1
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variants:
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- description: TE interrupt disabled
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name: Disabled
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value: 0
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- description: TE interrupt enabled
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name: Enabled
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value: 1
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enum/TWIE:
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bit_size: 1
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variants:
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- description: TW interrupt disabled
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name: Disabled
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value: 0
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- description: TW interrupt enabled
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name: Enabled
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value: 1
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fieldset/AMTCR:
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description: DMA2D AXI master timer configuration register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: Enable Enables the dead time functionality.
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enum: EN
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name: EN
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- bit_offset: 8
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bit_size: 8
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description: Dead Time Dead time value in the AXI clock cycle inserted between
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two consecutive accesses on the AXI master port. These bits represent the minimum
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guaranteed number of cycles between two consecutive AXI accesses.
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name: DT
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fieldset/BGCMAR:
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description: DMA2D background CLUT memory address register
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fields:
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- bit_offset: 0
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bit_size: 32
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description: Memory address Address of the data used for the CLUT address dedicated
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to the background image. This register can only be written when no transfer
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is on going. Once the CLUT transfer has started, this register is read-only.
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If the background CLUT format is 32-bit, the address must be 32-bit aligned.
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name: MA
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fieldset/BGCOLR:
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description: DMA2D background color register
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fields:
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- bit_offset: 0
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bit_size: 8
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description: Blue Value These bits define the blue value for the A4 or A8 mode
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of the background. These bits can only be written when data transfers are disabled.
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Once the transfer has started, they are read-only.
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name: BLUE
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- bit_offset: 8
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bit_size: 8
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description: Green Value These bits define the green value for the A4 or A8 mode
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of the background. These bits can only be written when data transfers are disabled.
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Once the transfer has started, they are read-only.
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name: GREEN
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- bit_offset: 16
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bit_size: 8
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description: Red Value These bits define the red value for the A4 or A8 mode of
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the background. These bits can only be written when data transfers are disabled.
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Once the transfer has started, they are read-only.
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name: RED
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fieldset/BGMAR:
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description: DMA2D background memory address register
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fields:
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- bit_offset: 0
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bit_size: 32
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description: Memory address Address of the data used for the background image.
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This register can only be written when data transfers are disabled. Once a data
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transfer has started, this register is read-only. The address alignment must
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match the image format selected e.g. a 32-bit per pixel format must be 32-bit
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aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel
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format must be 8-bit aligned.
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name: MA
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fieldset/BGOR:
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description: DMA2D background offset register
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fields:
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- bit_offset: 0
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bit_size: 16
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description: Line offset Line offset used for the background image (expressed
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in pixel). This value is used for the address generation. It is added at the
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end of each line to determine the starting address of the next line. These bits
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can only be written when data transfers are disabled. Once data transfer has
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started, they become read-only. If the image format is 4-bit per pixel, the
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line offset must be even.
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name: LO
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fieldset/BGPFCCR:
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description: DMA2D background PFC control register
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fields:
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- bit_offset: 0
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bit_size: 4
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description: 'Color mode These bits define the color format of the foreground
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image. These bits can only be written when data transfers are disabled. Once
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the transfer has started, they are read-only. others: meaningless'
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enum: BGPFCCR_CM
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name: CM
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- bit_offset: 4
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bit_size: 1
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description: CLUT Color mode These bits define the color format of the CLUT. This
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register can only be written when the transfer is disabled. Once the CLUT transfer
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has started, this bit is read-only.
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enum: BGPFCCR_CCM
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name: CCM
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- bit_offset: 5
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bit_size: 1
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description: 'Start This bit is set to start the automatic loading of the CLUT.
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This bit is automatically reset: ** at the end of the transfer ** when the transfer
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is aborted by the user application by setting the ABORT bit in the DMA2D_CR
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** when a transfer error occurs ** when the transfer has not started due to
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a configuration error or another transfer operation already on going (data transfer
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or automatic BackGround CLUT transfer).'
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enum: BGPFCCR_START
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name: START
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- bit_offset: 8
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bit_size: 8
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description: CLUT size These bits define the size of the CLUT used for the BG.
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Once the CLUT transfer has started, this field is read-only. The number of CLUT
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entries is equal to CS[7:0] + 1.
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name: CS
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- bit_offset: 16
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bit_size: 2
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description: 'Alpha mode These bits define which alpha channel value to be used
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for the background image. These bits can only be written when data transfers
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are disabled. Once the transfer has started, they are read-only. others: meaningless'
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enum: BGPFCCR_AM
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name: AM
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- bit_offset: 20
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bit_size: 1
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description: Alpha Inverted This bit inverts the alpha value. Once the transfer
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has started, this bit is read-only.
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enum: BGPFCCR_AI
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name: AI
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- bit_offset: 21
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bit_size: 1
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description: Red Blue Swap This bit allows to swap the R & B to support BGR
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or ABGR color formats. Once the transfer has started, this bit is read-only.
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enum: BGPFCCR_RBS
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name: RBS
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- bit_offset: 24
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bit_size: 8
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description: 'Alpha value These bits define a fixed alpha channel value which
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can replace the original alpha value or be multiplied with the original alpha
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value according to the alpha mode selected with bits AM[1: 0]. These bits can
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only be written when data transfers are disabled. Once the transfer has started,
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they are read-only.'
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name: ALPHA
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fieldset/CR:
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description: DMA2D control register
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fields:
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- bit_offset: 0
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bit_size: 1
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|
description: Start This bit can be used to launch the DMA2D according to the parameters
|
|
loaded in the various configuration registers
|
|
enum: CR_START
|
|
name: START
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: Suspend This bit can be used to suspend the current transfer. This
|
|
bit is set and reset by software. It is automatically reset by hardware when
|
|
the START bit is reset.
|
|
enum: SUSP
|
|
name: SUSP
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: Abort This bit can be used to abort the current transfer. This bit
|
|
is set by software and is automatically reset by hardware when the START bit
|
|
is reset.
|
|
enum: ABORT
|
|
name: ABORT
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: Transfer error interrupt enable This bit is set and cleared by software.
|
|
enum: TEIE
|
|
name: TEIE
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: Transfer complete interrupt enable This bit is set and cleared by
|
|
software.
|
|
enum: TCIE
|
|
name: TCIE
|
|
- bit_offset: 10
|
|
bit_size: 1
|
|
description: Transfer watermark interrupt enable This bit is set and cleared by
|
|
software.
|
|
enum: TWIE
|
|
name: TWIE
|
|
- bit_offset: 11
|
|
bit_size: 1
|
|
description: CLUT access error interrupt enable This bit is set and cleared by
|
|
software.
|
|
enum: CAEIE
|
|
name: CAEIE
|
|
- bit_offset: 12
|
|
bit_size: 1
|
|
description: CLUT transfer complete interrupt enable This bit is set and cleared
|
|
by software.
|
|
enum: CTCIE
|
|
name: CTCIE
|
|
- bit_offset: 13
|
|
bit_size: 1
|
|
description: Configuration Error Interrupt Enable This bit is set and cleared
|
|
by software.
|
|
enum: CEIE
|
|
name: CEIE
|
|
- bit_offset: 16
|
|
bit_size: 2
|
|
description: DMA2D mode This bit is set and cleared by software. It cannot be
|
|
modified while a transfer is ongoing.
|
|
enum: MODE
|
|
name: MODE
|
|
fieldset/FGCMAR:
|
|
description: DMA2D foreground CLUT memory address register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 32
|
|
description: Memory Address Address of the data used for the CLUT address dedicated
|
|
to the foreground image. This register can only be written when no transfer
|
|
is ongoing. Once the CLUT transfer has started, this register is read-only.
|
|
If the foreground CLUT format is 32-bit, the address must be 32-bit aligned.
|
|
name: MA
|
|
fieldset/FGCOLR:
|
|
description: DMA2D foreground color register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 8
|
|
description: Blue Value These bits defines the blue value for the A4 or A8 mode
|
|
of the foreground image. They can only be written when data transfers are disabled.
|
|
Once the transfer has started, They are read-only.
|
|
name: BLUE
|
|
- bit_offset: 8
|
|
bit_size: 8
|
|
description: Green Value These bits defines the green value for the A4 or A8 mode
|
|
of the foreground image. They can only be written when data transfers are disabled.
|
|
Once the transfer has started, They are read-only.
|
|
name: GREEN
|
|
- bit_offset: 16
|
|
bit_size: 8
|
|
description: Red Value These bits defines the red value for the A4 or A8 mode
|
|
of the foreground image. They can only be written when data transfers are disabled.
|
|
Once the transfer has started, they are read-only.
|
|
name: RED
|
|
fieldset/FGMAR:
|
|
description: DMA2D foreground memory address register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 32
|
|
description: Memory address Address of the data used for the foreground image.
|
|
This register can only be written when data transfers are disabled. Once the
|
|
data transfer has started, this register is read-only. The address alignment
|
|
must match the image format selected e.g. a 32-bit per pixel format must be
|
|
32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit
|
|
per pixel format must be 8-bit aligned.
|
|
name: MA
|
|
fieldset/FGOR:
|
|
description: DMA2D foreground offset register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 16
|
|
description: Line offset Line offset used for the foreground expressed in pixel.
|
|
This value is used to generate the address. It is added at the end of each line
|
|
to determine the starting address of the next line. These bits can only be written
|
|
when data transfers are disabled. Once a data transfer has started, they become
|
|
read-only. If the image format is 4-bit per pixel, the line offset must be even.
|
|
name: LO
|
|
fieldset/FGPFCCR:
|
|
description: DMA2D foreground PFC control register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 4
|
|
description: 'Color mode These bits defines the color format of the foreground
|
|
image. They can only be written when data transfers are disabled. Once the transfer
|
|
has started, they are read-only. others: meaningless'
|
|
enum: FGPFCCR_CM
|
|
name: CM
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: CLUT color mode This bit defines the color format of the CLUT. It
|
|
can only be written when the transfer is disabled. Once the CLUT transfer has
|
|
started, this bit is read-only.
|
|
enum: FGPFCCR_CCM
|
|
name: CCM
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: 'Start This bit can be set to start the automatic loading of the
|
|
CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer
|
|
is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when
|
|
a transfer error occurs ** when the transfer has not started due to a configuration
|
|
error or another transfer operation already ongoing (data transfer or automatic
|
|
background CLUT transfer).'
|
|
enum: FGPFCCR_START
|
|
name: START
|
|
- bit_offset: 8
|
|
bit_size: 8
|
|
description: CLUT size These bits define the size of the CLUT used for the foreground
|
|
image. Once the CLUT transfer has started, this field is read-only. The number
|
|
of CLUT entries is equal to CS[7:0] + 1.
|
|
name: CS
|
|
- bit_offset: 16
|
|
bit_size: 2
|
|
description: Alpha mode These bits select the alpha channel value to be used for
|
|
the foreground image. They can only be written data the transfer are disabled.
|
|
Once the transfer has started, they become read-only. other configurations are
|
|
meaningless
|
|
enum: FGPFCCR_AM
|
|
name: AM
|
|
- bit_offset: 18
|
|
bit_size: 2
|
|
description: 'Chroma Sub-Sampling These bits define the chroma sub-sampling mode
|
|
for YCbCr color mode. Once the transfer has started, these bits are read-only.
|
|
others: meaningless'
|
|
name: CSS
|
|
- bit_offset: 20
|
|
bit_size: 1
|
|
description: Alpha Inverted This bit inverts the alpha value. Once the transfer
|
|
has started, this bit is read-only.
|
|
enum: FGPFCCR_AI
|
|
name: AI
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: Red Blue Swap This bit allows to swap the R & B to support BGR
|
|
or ABGR color formats. Once the transfer has started, this bit is read-only.
|
|
enum: FGPFCCR_RBS
|
|
name: RBS
|
|
- bit_offset: 24
|
|
bit_size: 8
|
|
description: Alpha value These bits define a fixed alpha channel value which can
|
|
replace the original alpha value or be multiplied by the original alpha value
|
|
according to the alpha mode selected through the AM[1:0] bits. These bits can
|
|
only be written when data transfers are disabled. Once a transfer has started,
|
|
they become read-only.
|
|
name: ALPHA
|
|
fieldset/IFCR:
|
|
description: DMA2D interrupt flag clear register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: Clear Transfer error interrupt flag Programming this bit to 1 clears
|
|
the TEIF flag in the DMA2D_ISR register
|
|
enum: CTEIF
|
|
name: CTEIF
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: Clear transfer complete interrupt flag Programming this bit to 1
|
|
clears the TCIF flag in the DMA2D_ISR register
|
|
enum: CTCIF
|
|
name: CTCIF
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: Clear transfer watermark interrupt flag Programming this bit to 1
|
|
clears the TWIF flag in the DMA2D_ISR register
|
|
enum: CTWIF
|
|
name: CTWIF
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: Clear CLUT access error interrupt flag Programming this bit to 1
|
|
clears the CAEIF flag in the DMA2D_ISR register
|
|
enum: CAECIF
|
|
name: CAECIF
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: Clear CLUT transfer complete interrupt flag Programming this bit
|
|
to 1 clears the CTCIF flag in the DMA2D_ISR register
|
|
enum: CCTCIF
|
|
name: CCTCIF
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: Clear configuration error interrupt flag Programming this bit to
|
|
1 clears the CEIF flag in the DMA2D_ISR register
|
|
enum: CCEIF
|
|
name: CCEIF
|
|
fieldset/ISR:
|
|
description: DMA2D Interrupt Status Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: Transfer error interrupt flag This bit is set when an error occurs
|
|
during a DMA transfer (data transfer or automatic CLUT loading).
|
|
name: TEIF
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: Transfer complete interrupt flag This bit is set when a DMA2D transfer
|
|
operation is complete (data transfer only).
|
|
name: TCIF
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: Transfer watermark interrupt flag This bit is set when the last pixel
|
|
of the watermarked line has been transferred.
|
|
name: TWIF
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: CLUT access error interrupt flag This bit is set when the CPU accesses
|
|
the CLUT while the CLUT is being automatically copied from a system memory to
|
|
the internal DMA2D.
|
|
name: CAEIF
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: CLUT transfer complete interrupt flag This bit is set when the CLUT
|
|
copy from a system memory area to the internal DMA2D memory is complete.
|
|
name: CTCIF
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: Configuration error interrupt flag This bit is set when the START
|
|
bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration
|
|
has been programmed.
|
|
name: CEIF
|
|
fieldset/LWR:
|
|
description: DMA2D line watermark register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 16
|
|
description: Line watermark These bits allow to configure the line watermark for
|
|
interrupt generation. An interrupt is raised when the last pixel of the watermarked
|
|
line has been transferred. These bits can only be written when data transfers
|
|
are disabled. Once the transfer has started, they are read-only.
|
|
name: LW
|
|
fieldset/NLR:
|
|
description: DMA2D number of line register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 16
|
|
description: Number of lines Number of lines of the area to be transferred. These
|
|
bits can only be written when data transfers are disabled. Once the transfer
|
|
has started, they are read-only.
|
|
name: NL
|
|
- bit_offset: 16
|
|
bit_size: 14
|
|
description: Pixel per lines Number of pixels per lines of the area to be transferred.
|
|
These bits can only be written when data transfers are disabled. Once the transfer
|
|
has started, they are read-only. If any of the input image format is 4-bit per
|
|
pixel, pixel per lines must be even.
|
|
name: PL
|
|
fieldset/OCOLR:
|
|
description: DMA2D output color register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 8
|
|
description: Blue Value These bits define the blue value of the output image.
|
|
These bits can only be written when data transfers are disabled. Once the transfer
|
|
has started, they are read-only.
|
|
name: BLUE
|
|
- bit_offset: 8
|
|
bit_size: 8
|
|
description: Green Value These bits define the green value of the output image.
|
|
These bits can only be written when data transfers are disabled. Once the transfer
|
|
has started, they are read-only.
|
|
name: GREEN
|
|
- bit_offset: 16
|
|
bit_size: 8
|
|
description: Red Value These bits define the red value of the output image. These
|
|
bits can only be written when data transfers are disabled. Once the transfer
|
|
has started, they are read-only.
|
|
name: RED
|
|
- bit_offset: 24
|
|
bit_size: 8
|
|
description: Alpha Channel Value These bits define the alpha channel of the output
|
|
color. These bits can only be written when data transfers are disabled. Once
|
|
the transfer has started, they are read-only.
|
|
name: ALPHA
|
|
fieldset/OMAR:
|
|
description: DMA2D output memory address register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 32
|
|
description: Memory Address Address of the data used for the output FIFO. These
|
|
bits can only be written when data transfers are disabled. Once the transfer
|
|
has started, they are read-only. The address alignment must match the image
|
|
format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a
|
|
16-bit per pixel format must be 16-bit aligned.
|
|
name: MA
|
|
fieldset/OOR:
|
|
description: DMA2D output offset register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 16
|
|
description: Line Offset Line offset used for the output (expressed in pixels).
|
|
This value is used for the address generation. It is added at the end of each
|
|
line to determine the starting address of the next line. These bits can only
|
|
be written when data transfers are disabled. Once the transfer has started,
|
|
they are read-only.
|
|
name: LO
|
|
fieldset/OPFCCR:
|
|
description: DMA2D output PFC control register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 3
|
|
description: 'Color mode These bits define the color format of the output image.
|
|
These bits can only be written when data transfers are disabled. Once the transfer
|
|
has started, they are read-only. others: meaningless'
|
|
enum: OPFCCR_CM
|
|
name: CM
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: Swap Bytes
|
|
enum: SB
|
|
name: SB
|
|
- bit_offset: 20
|
|
bit_size: 1
|
|
description: Alpha Inverted This bit inverts the alpha value. Once the transfer
|
|
has started, this bit is read-only.
|
|
enum: OPFCCR_AI
|
|
name: AI
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: Red Blue Swap This bit allows to swap the R & B to support BGR
|
|
or ABGR color formats. Once the transfer has started, this bit is read-only.
|
|
enum: OPFCCR_RBS
|
|
name: RBS
|