block/DMA2D: description: DMA2D items: - byte_offset: 0 description: DMA2D control register fieldset: CR name: CR - access: Read byte_offset: 4 description: DMA2D Interrupt Status Register fieldset: ISR name: ISR - byte_offset: 8 description: DMA2D interrupt flag clear register fieldset: IFCR name: IFCR - byte_offset: 12 description: DMA2D foreground memory address register fieldset: FGMAR name: FGMAR - byte_offset: 16 description: DMA2D foreground offset register fieldset: FGOR name: FGOR - byte_offset: 20 description: DMA2D background memory address register fieldset: BGMAR name: BGMAR - byte_offset: 24 description: DMA2D background offset register fieldset: BGOR name: BGOR - byte_offset: 28 description: DMA2D foreground PFC control register fieldset: FGPFCCR name: FGPFCCR - byte_offset: 32 description: DMA2D foreground color register fieldset: FGCOLR name: FGCOLR - byte_offset: 36 description: DMA2D background PFC control register fieldset: BGPFCCR name: BGPFCCR - byte_offset: 40 description: DMA2D background color register fieldset: BGCOLR name: BGCOLR - byte_offset: 44 description: DMA2D foreground CLUT memory address register fieldset: FGCMAR name: FGCMAR - byte_offset: 48 description: DMA2D background CLUT memory address register fieldset: BGCMAR name: BGCMAR - byte_offset: 52 description: DMA2D output PFC control register fieldset: OPFCCR name: OPFCCR - byte_offset: 56 description: DMA2D output color register fieldset: OCOLR name: OCOLR - byte_offset: 60 description: DMA2D output memory address register fieldset: OMAR name: OMAR - byte_offset: 64 description: DMA2D output offset register fieldset: OOR name: OOR - byte_offset: 68 description: DMA2D number of line register fieldset: NLR name: NLR - byte_offset: 72 description: DMA2D line watermark register fieldset: LWR name: LWR - byte_offset: 76 description: DMA2D AXI master timer configuration register fieldset: AMTCR name: AMTCR enum/ABORT: bit_size: 1 variants: - description: Transfer abort requested name: AbortRequest value: 1 enum/BGPFCCR_AI: bit_size: 1 variants: - description: Regular alpha name: RegularAlpha value: 0 - description: Inverted alpha name: InvertedAlpha value: 1 enum/BGPFCCR_AM: bit_size: 2 variants: - description: No modification of alpha channel name: NoModify value: 0 - description: Replace with value in ALPHA[7:0] name: Replace value: 1 - description: Multiply with value in ALPHA[7:0] name: Multiply value: 2 enum/BGPFCCR_CCM: bit_size: 1 variants: - description: CLUT color format ARGB8888 name: ARGB8888 value: 0 - description: CLUT color format RGB888 name: RGB888 value: 1 enum/BGPFCCR_CM: bit_size: 4 variants: - description: Color mode ARGB8888 name: ARGB8888 value: 0 - description: Color mode RGB888 name: RGB888 value: 1 - description: Color mode RGB565 name: RGB565 value: 2 - description: Color mode ARGB1555 name: ARGB1555 value: 3 - description: Color mode ARGB4444 name: ARGB4444 value: 4 - description: Color mode L8 name: L8 value: 5 - description: Color mode AL44 name: AL44 value: 6 - description: Color mode AL88 name: AL88 value: 7 - description: Color mode L4 name: L4 value: 8 - description: Color mode A8 name: A8 value: 9 - description: Color mode A4 name: A4 value: 10 enum/BGPFCCR_RBS: bit_size: 1 variants: - description: No Red Blue Swap (RGB or ARGB) name: Regular value: 0 - description: Red Blue Swap (BGR or ABGR) name: Swap value: 1 enum/BGPFCCR_START: bit_size: 1 variants: - description: Start the automatic loading of the CLUT name: Start value: 1 enum/CAECIF: bit_size: 1 variants: - description: Clear the CAEIF flag in the ISR register name: Clear value: 1 enum/CAEIE: bit_size: 1 variants: - description: CAE interrupt disabled name: Disabled value: 0 - description: CAE interrupt enabled name: Enabled value: 1 enum/CCEIF: bit_size: 1 variants: - description: Clear the CEIF flag in the ISR register name: Clear value: 1 enum/CCTCIF: bit_size: 1 variants: - description: Clear the CTCIF flag in the ISR register name: Clear value: 1 enum/CEIE: bit_size: 1 variants: - description: CE interrupt disabled name: Disabled value: 0 - description: CE interrupt enabled name: Enabled value: 1 enum/CR_START: bit_size: 1 variants: - description: Launch the DMA2D name: Start value: 1 enum/CTCIE: bit_size: 1 variants: - description: CTC interrupt disabled name: Disabled value: 0 - description: CTC interrupt enabled name: Enabled value: 1 enum/CTCIF: bit_size: 1 variants: - description: Clear the TCIF flag in the ISR register name: Clear value: 1 enum/CTEIF: bit_size: 1 variants: - description: Clear the TEIF flag in the ISR register name: Clear value: 1 enum/CTWIF: bit_size: 1 variants: - description: Clear the TWIF flag in the ISR register name: Clear value: 1 enum/EN: bit_size: 1 variants: - description: Disabled AHB/AXI dead-time functionality name: Disabled value: 0 - description: Enabled AHB/AXI dead-time functionality name: Enabled value: 1 enum/FGPFCCR_AI: bit_size: 1 variants: - description: Regular alpha name: RegularAlpha value: 0 - description: Inverted alpha name: InvertedAlpha value: 1 enum/FGPFCCR_AM: bit_size: 2 variants: - description: No modification of alpha channel name: NoModify value: 0 - description: Replace with value in ALPHA[7:0] name: Replace value: 1 - description: Multiply with value in ALPHA[7:0] name: Multiply value: 2 enum/FGPFCCR_CCM: bit_size: 1 variants: - description: CLUT color format ARGB8888 name: ARGB8888 value: 0 - description: CLUT color format RGB888 name: RGB888 value: 1 enum/FGPFCCR_CM: bit_size: 4 variants: - description: Color mode ARGB8888 name: ARGB8888 value: 0 - description: Color mode RGB888 name: RGB888 value: 1 - description: Color mode RGB565 name: RGB565 value: 2 - description: Color mode ARGB1555 name: ARGB1555 value: 3 - description: Color mode ARGB4444 name: ARGB4444 value: 4 - description: Color mode L8 name: L8 value: 5 - description: Color mode AL44 name: AL44 value: 6 - description: Color mode AL88 name: AL88 value: 7 - description: Color mode L4 name: L4 value: 8 - description: Color mode A8 name: A8 value: 9 - description: Color mode A4 name: A4 value: 10 - description: Color mode YCbCr name: YCbCr value: 11 enum/FGPFCCR_RBS: bit_size: 1 variants: - description: No Red Blue Swap (RGB or ARGB) name: Regular value: 0 - description: Red Blue Swap (BGR or ABGR) name: Swap value: 1 enum/FGPFCCR_START: bit_size: 1 variants: - description: Start the automatic loading of the CLUT name: Start value: 1 enum/MODE: bit_size: 2 variants: - description: Memory-to-memory (FG fetch only) name: MemoryToMemory value: 0 - description: Memory-to-memory with PFC (FG fetch only with FG PFC active) name: MemoryToMemoryPFC value: 1 - description: Memory-to-memory with blending (FG and BG fetch with PFC and blending) name: MemoryToMemoryPFCBlending value: 2 - description: Register-to-memory name: RegisterToMemory value: 3 enum/OPFCCR_AI: bit_size: 1 variants: - description: Regular alpha name: RegularAlpha value: 0 - description: Inverted alpha name: InvertedAlpha value: 1 enum/OPFCCR_CM: bit_size: 3 variants: - description: ARGB8888 name: ARGB8888 value: 0 - description: RGB888 name: RGB888 value: 1 - description: RGB565 name: RGB565 value: 2 - description: ARGB1555 name: ARGB1555 value: 3 - description: ARGB4444 name: ARGB4444 value: 4 enum/OPFCCR_RBS: bit_size: 1 variants: - description: No Red Blue Swap (RGB or ARGB) name: Regular value: 0 - description: Red Blue Swap (BGR or ABGR) name: Swap value: 1 enum/SB: bit_size: 1 variants: - description: Regular byte order name: Regular value: 0 - description: Bytes are swapped two by two name: SwapBytes value: 1 enum/SUSP: bit_size: 1 variants: - description: Transfer not suspended name: NotSuspended value: 0 - description: Transfer suspended name: Suspended value: 1 enum/TCIE: bit_size: 1 variants: - description: TC interrupt disabled name: Disabled value: 0 - description: TC interrupt enabled name: Enabled value: 1 enum/TEIE: bit_size: 1 variants: - description: TE interrupt disabled name: Disabled value: 0 - description: TE interrupt enabled name: Enabled value: 1 enum/TWIE: bit_size: 1 variants: - description: TW interrupt disabled name: Disabled value: 0 - description: TW interrupt enabled name: Enabled value: 1 fieldset/AMTCR: description: DMA2D AXI master timer configuration register fields: - bit_offset: 0 bit_size: 1 description: Enable Enables the dead time functionality. enum: EN name: EN - bit_offset: 8 bit_size: 8 description: Dead Time Dead time value in the AXI clock cycle inserted between two consecutive accesses on the AXI master port. These bits represent the minimum guaranteed number of cycles between two consecutive AXI accesses. name: DT fieldset/BGCMAR: description: DMA2D background CLUT memory address register fields: - bit_offset: 0 bit_size: 32 description: Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. If the background CLUT format is 32-bit, the address must be 32-bit aligned. name: MA fieldset/BGCOLR: description: DMA2D background color register fields: - bit_offset: 0 bit_size: 8 description: Blue Value These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. name: BLUE - bit_offset: 8 bit_size: 8 description: Green Value These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. name: GREEN - bit_offset: 16 bit_size: 8 description: Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. name: RED fieldset/BGMAR: description: DMA2D background memory address register fields: - bit_offset: 0 bit_size: 32 description: Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned. name: MA fieldset/BGOR: description: DMA2D background offset register fields: - bit_offset: 0 bit_size: 16 description: Line offset Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even. name: LO fieldset/BGPFCCR: description: DMA2D background PFC control register fields: - bit_offset: 0 bit_size: 4 description: 'Color mode These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless' enum: BGPFCCR_CM name: CM - bit_offset: 4 bit_size: 1 description: CLUT Color mode These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only. enum: BGPFCCR_CCM name: CCM - bit_offset: 5 bit_size: 1 description: 'Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic BackGround CLUT transfer).' enum: BGPFCCR_START name: START - bit_offset: 8 bit_size: 8 description: CLUT size These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1. name: CS - bit_offset: 16 bit_size: 2 description: 'Alpha mode These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless' enum: BGPFCCR_AM name: AM - bit_offset: 20 bit_size: 1 description: Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only. enum: BGPFCCR_AI name: AI - bit_offset: 21 bit_size: 1 description: Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. enum: BGPFCCR_RBS name: RBS - bit_offset: 24 bit_size: 8 description: 'Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.' name: ALPHA fieldset/CR: description: DMA2D control register fields: - bit_offset: 0 bit_size: 1 description: Start This bit can be used to launch the DMA2D according to the parameters loaded in the various configuration registers enum: CR_START name: START - bit_offset: 1 bit_size: 1 description: Suspend This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when the START bit is reset. enum: SUSP name: SUSP - bit_offset: 2 bit_size: 1 description: Abort This bit can be used to abort the current transfer. This bit is set by software and is automatically reset by hardware when the START bit is reset. enum: ABORT name: ABORT - bit_offset: 8 bit_size: 1 description: Transfer error interrupt enable This bit is set and cleared by software. enum: TEIE name: TEIE - bit_offset: 9 bit_size: 1 description: Transfer complete interrupt enable This bit is set and cleared by software. enum: TCIE name: TCIE - bit_offset: 10 bit_size: 1 description: Transfer watermark interrupt enable This bit is set and cleared by software. enum: TWIE name: TWIE - bit_offset: 11 bit_size: 1 description: CLUT access error interrupt enable This bit is set and cleared by software. enum: CAEIE name: CAEIE - bit_offset: 12 bit_size: 1 description: CLUT transfer complete interrupt enable This bit is set and cleared by software. enum: CTCIE name: CTCIE - bit_offset: 13 bit_size: 1 description: Configuration Error Interrupt Enable This bit is set and cleared by software. enum: CEIE name: CEIE - bit_offset: 16 bit_size: 2 description: DMA2D mode This bit is set and cleared by software. It cannot be modified while a transfer is ongoing. enum: MODE name: MODE fieldset/FGCMAR: description: DMA2D foreground CLUT memory address register fields: - bit_offset: 0 bit_size: 32 description: Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned. name: MA fieldset/FGCOLR: description: DMA2D foreground color register fields: - bit_offset: 0 bit_size: 8 description: Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only. name: BLUE - bit_offset: 8 bit_size: 8 description: Green Value These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only. name: GREEN - bit_offset: 16 bit_size: 8 description: Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. name: RED fieldset/FGMAR: description: DMA2D foreground memory address register fields: - bit_offset: 0 bit_size: 32 description: Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned. name: MA fieldset/FGOR: description: DMA2D foreground offset register fields: - bit_offset: 0 bit_size: 16 description: Line offset Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once a data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even. name: LO fieldset/FGPFCCR: description: DMA2D foreground PFC control register fields: - bit_offset: 0 bit_size: 4 description: 'Color mode These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless' enum: FGPFCCR_CM name: CM - bit_offset: 4 bit_size: 1 description: CLUT color mode This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only. enum: FGPFCCR_CCM name: CCM - bit_offset: 5 bit_size: 1 description: 'Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer).' enum: FGPFCCR_START name: START - bit_offset: 8 bit_size: 8 description: CLUT size These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1. name: CS - bit_offset: 16 bit_size: 2 description: Alpha mode These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. other configurations are meaningless enum: FGPFCCR_AM name: AM - bit_offset: 18 bit_size: 2 description: 'Chroma Sub-Sampling These bits define the chroma sub-sampling mode for YCbCr color mode. Once the transfer has started, these bits are read-only. others: meaningless' name: CSS - bit_offset: 20 bit_size: 1 description: Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only. enum: FGPFCCR_AI name: AI - bit_offset: 21 bit_size: 1 description: Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. enum: FGPFCCR_RBS name: RBS - bit_offset: 24 bit_size: 8 description: Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only. name: ALPHA fieldset/IFCR: description: DMA2D interrupt flag clear register fields: - bit_offset: 0 bit_size: 1 description: Clear Transfer error interrupt flag Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register enum: CTEIF name: CTEIF - bit_offset: 1 bit_size: 1 description: Clear transfer complete interrupt flag Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register enum: CTCIF name: CTCIF - bit_offset: 2 bit_size: 1 description: Clear transfer watermark interrupt flag Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register enum: CTWIF name: CTWIF - bit_offset: 3 bit_size: 1 description: Clear CLUT access error interrupt flag Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register enum: CAECIF name: CAECIF - bit_offset: 4 bit_size: 1 description: Clear CLUT transfer complete interrupt flag Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register enum: CCTCIF name: CCTCIF - bit_offset: 5 bit_size: 1 description: Clear configuration error interrupt flag Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register enum: CCEIF name: CCEIF fieldset/ISR: description: DMA2D Interrupt Status Register fields: - bit_offset: 0 bit_size: 1 description: Transfer error interrupt flag This bit is set when an error occurs during a DMA transfer (data transfer or automatic CLUT loading). name: TEIF - bit_offset: 1 bit_size: 1 description: Transfer complete interrupt flag This bit is set when a DMA2D transfer operation is complete (data transfer only). name: TCIF - bit_offset: 2 bit_size: 1 description: Transfer watermark interrupt flag This bit is set when the last pixel of the watermarked line has been transferred. name: TWIF - bit_offset: 3 bit_size: 1 description: CLUT access error interrupt flag This bit is set when the CPU accesses the CLUT while the CLUT is being automatically copied from a system memory to the internal DMA2D. name: CAEIF - bit_offset: 4 bit_size: 1 description: CLUT transfer complete interrupt flag This bit is set when the CLUT copy from a system memory area to the internal DMA2D memory is complete. name: CTCIF - bit_offset: 5 bit_size: 1 description: Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed. name: CEIF fieldset/LWR: description: DMA2D line watermark register fields: - bit_offset: 0 bit_size: 16 description: Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. name: LW fieldset/NLR: description: DMA2D number of line register fields: - bit_offset: 0 bit_size: 16 description: Number of lines Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. name: NL - bit_offset: 16 bit_size: 14 description: Pixel per lines Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. If any of the input image format is 4-bit per pixel, pixel per lines must be even. name: PL fieldset/OCOLR: description: DMA2D output color register fields: - bit_offset: 0 bit_size: 8 description: Blue Value These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. name: BLUE - bit_offset: 8 bit_size: 8 description: Green Value These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. name: GREEN - bit_offset: 16 bit_size: 8 description: Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. name: RED - bit_offset: 24 bit_size: 8 description: Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. name: ALPHA fieldset/OMAR: description: DMA2D output memory address register fields: - bit_offset: 0 bit_size: 32 description: Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned. name: MA fieldset/OOR: description: DMA2D output offset register fields: - bit_offset: 0 bit_size: 16 description: Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. name: LO fieldset/OPFCCR: description: DMA2D output PFC control register fields: - bit_offset: 0 bit_size: 3 description: 'Color mode These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless' enum: OPFCCR_CM name: CM - bit_offset: 8 bit_size: 1 description: Swap Bytes enum: SB name: SB - bit_offset: 20 bit_size: 1 description: Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only. enum: OPFCCR_AI name: AI - bit_offset: 21 bit_size: 1 description: Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. enum: OPFCCR_RBS name: RBS