stm32-data/data/registers/syscfg_u0.yaml

block/SYSCFG:
  description: SYSCFG register block
  items:
  - name: CFGR1
    description: SYSCFG configuration register 1
    byte_offset: 0
    fieldset: CFGR1
  - name: CFGR2
    description: SYSCFG configuration register 2
    byte_offset: 24
    fieldset: CFGR2
  - name: SCSR
    description: SYSCFG SRAM2 control and status register
    byte_offset: 28
    fieldset: SCSR
  - name: SKR
    description: SYSCFG SRAM2 key register
    byte_offset: 32
    fieldset: SKR
  - name: TSCCR
    description: SYSCFG TSC comparator register
    byte_offset: 36
    fieldset: TSCCR
  - name: ITLINE0
    description: SYSCFG interrupt line 0 status register
    byte_offset: 128
    fieldset: ITLINE0
  - name: ITLINE1
    description: SYSCFG interrupt line 1 status register
    byte_offset: 132
    fieldset: ITLINE1
  - name: ITLINE2
    description: SYSCFG interrupt line 2 status register
    byte_offset: 136
    fieldset: ITLINE2
  - name: ITLINE3
    description: SYSCFG interrupt line 3 status register
    byte_offset: 140
    fieldset: ITLINE3
  - name: ITLINE4
    description: SYSCFG interrupt line 4 status register
    byte_offset: 144
    fieldset: ITLINE4
  - name: ITLINE5
    description: SYSCFG interrupt line 5 status register
    byte_offset: 148
    fieldset: ITLINE5
  - name: ITLINE6
    description: SYSCFG interrupt line 6 status register
    byte_offset: 152
    fieldset: ITLINE6
  - name: ITLINE7
    description: SYSCFG interrupt line 7 status register
    byte_offset: 156
    fieldset: ITLINE7
  - name: ITLINE8
    description: SYSCFG interrupt line 8 status register
    byte_offset: 160
    fieldset: ITLINE8
  - name: ITLINE9
    description: SYSCFG interrupt line 9 status register
    byte_offset: 164
    fieldset: ITLINE9
  - name: ITLINE10
    description: SYSCFG interrupt line 10 status register
    byte_offset: 168
    fieldset: ITLINE10
  - name: ITLINE11
    description: SYSCFG interrupt line 11 status register
    byte_offset: 172
    fieldset: ITLINE11
  - name: ITLINE12
    description: SYSCFG interrupt line 12 status register
    byte_offset: 176
    fieldset: ITLINE12
  - name: ITLINE13
    description: SYSCFG interrupt line 13 status register
    byte_offset: 180
    fieldset: ITLINE13
  - name: ITLINE14
    description: SYSCFG interrupt line 14 status register
    byte_offset: 184
    fieldset: ITLINE14
  - name: ITLINE15
    description: SYSCFG interrupt line 15 status register
    byte_offset: 188
    fieldset: ITLINE15
  - name: ITLINE16
    description: SYSCFG interrupt line 16 status register
    byte_offset: 192
    fieldset: ITLINE16
  - name: ITLINE17
    description: SYSCFG interrupt line 17 status register
    byte_offset: 196
    fieldset: ITLINE17
  - name: ITLINE18
    description: SYSCFG interrupt line 18 status register
    byte_offset: 200
    fieldset: ITLINE18
  - name: ITLINE19
    description: SYSCFG interrupt line 19 status register
    byte_offset: 204
    fieldset: ITLINE19
  - name: ITLINE20
    description: SYSCFG interrupt line 20 status register
    byte_offset: 208
    fieldset: ITLINE20
  - name: ITLINE21
    description: SYSCFG interrupt line 21 status register
    byte_offset: 212
    fieldset: ITLINE21
  - name: ITLINE22
    description: SYSCFG interrupt line 22 status register
    byte_offset: 216
    fieldset: ITLINE22
  - name: ITLINE23
    description: SYSCFG interrupt line 23 status register
    byte_offset: 220
    fieldset: ITLINE23
  - name: ITLINE24
    description: SYSCFG interrupt line 24 status register
    byte_offset: 224
    fieldset: ITLINE24
  - name: ITLINE25
    description: SYSCFG interrupt line 25 status register
    byte_offset: 228
    fieldset: ITLINE25
  - name: ITLINE26
    description: SYSCFG interrupt line 26 status register
    byte_offset: 232
    fieldset: ITLINE26
  - name: ITLINE27
    description: SYSCFG interrupt line 27 status register
    byte_offset: 236
    fieldset: ITLINE27
  - name: ITLINE28
    description: SYSCFG interrupt line 28 status register
    byte_offset: 240
    fieldset: ITLINE28
  - name: ITLINE29
    description: SYSCFG interrupt line 29 status register
    byte_offset: 244
    fieldset: ITLINE29
  - name: ITLINE30
    description: SYSCFG interrupt line 30 status register
    byte_offset: 248
    fieldset: ITLINE30
  - name: ITLINE31
    description: SYSCFG interrupt line 31 status register
    byte_offset: 252
    fieldset: ITLINE31
fieldset/CFGR1:
  description: SYSCFG configuration register 1
  fields:
  - name: MEM_MODE
    description: 'Memory mapping selection bits These bits are set and cleared by software. They control the memory internal mapping at address 0x000010000. After reset these bits take on the value selected by the actual boot mode configuration. Refer to Section12.5: Boot configuration for more details. X0: Main flash memory mapped at 0x000010000'
    bit_offset: 0
    bit_size: 2
    enum: MEM_MODE
  - name: PA11_RMP
    description: |-
      PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port.
      0: No remap (PA11)
      1: Remap (PA9)
    bit_offset: 3
    bit_size: 1
  - name: PA12_RMP
    description: |-
      PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port.
      0: No remap (PA12)
      1: Remap (PA10)
    bit_offset: 4
    bit_size: 1
  - name: IR_POL
    description: IR output polarity selection
    bit_offset: 5
    bit_size: 1
  - name: IR_MOD
    description: 'IR Modulation Envelope signal selection This bitfield selects the signal for IR modulation envelope:'
    bit_offset: 6
    bit_size: 2
    enum: IR_MOD
  - name: BOOSTEN
    description: 'I/O analog switch voltage booster enable This bit selects the way of supplying I/O analog switches: When using the analog inputs , setting to 0 is recommended for high V<sub>DD</sub>, setting to 1 for low V<sub>DD</sub> (less than 2.4 V).'
    bit_offset: 8
    bit_size: 1
  - name: I2C_PB6_FMP
    description: |-
      Fast Mode Plus (FM+) enable for PB6 This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB6 I/O port. With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
      0: Disable
      1: Enable
    bit_offset: 16
    bit_size: 1
  - name: I2C_PB7_FMP
    description: |-
      Fast Mode Plus (FM+) enable for PB7 This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB7 I/O port. With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
      0: Disable
      1: Enable
    bit_offset: 17
    bit_size: 1
  - name: I2C_PB8_FMP
    description: |-
      Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB8 I/O port. With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
      0: Disable
      1: Enable
    bit_offset: 18
    bit_size: 1
  - name: I2C_PB9_FMP
    description: |-
      Fast Mode Plus (FM+) enable for PB9 This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PB9 I/O port. With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
      0: Disable
      1: Enable
    bit_offset: 19
    bit_size: 1
  - name: I2C_PA9_FMP
    description: |-
      Fast Mode Plus (FM+) enable for PA9 This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PA9 I/O port. With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
      0: Disable
      1: Enable
    bit_offset: 22
    bit_size: 1
  - name: I2C_PA10_FMP
    description: |-
      Fast Mode Plus (FM+) enable for PA10 This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on PA10 I/O port. With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
      0: Disable
      1: Enable
    bit_offset: 23
    bit_size: 1
  - name: I2C3_FMP
    description: |-
      Fast Mode Plus (FM+) enable for I2C3 This bit is set and cleared by software. It enables I<sup>2</sup>C FM+ driving capability on I/O ports configured as I2C3 through GPIOx_AFR registers. With this bit in disable state, the I<sup>2</sup>C FM+ driving capability on I/O ports configured as I2C3 can be enabled through their corresponding I2Cx_FMP bit. When I<sup>2</sup>C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.
      0: Disable
      1: Enable
    bit_offset: 24
    bit_size: 1
fieldset/CFGR2:
  description: SYSCFG configuration register 2
  fields:
  - name: CCL
    description: Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP bit enable bit This bit is set by software and cleared by a system reset. It can be use to enable and lock the connection of Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP (Hardfault) output to TIM1/15/16 Break input.
    bit_offset: 0
    bit_size: 1
  - name: SPL
    description: SRAM1 parity lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM1 parity error signal connection to TIM1/15/16 Break input.
    bit_offset: 1
    bit_size: 1
  - name: PVDL
    description: PVD lock enable bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register.
    bit_offset: 2
    bit_size: 1
  - name: ECCL
    description: ECC error lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the flash ECC 2-bit error detection signal connection to TIM1/15/16 Break input.
    bit_offset: 3
    bit_size: 1
  - name: BKPL
    description: Backup SRAM2 parity lock This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/15/16 Break input.
    bit_offset: 4
    bit_size: 1
  - name: BKPF
    description: Backup SRAM2 parity error flag This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing 1.
    bit_offset: 7
    bit_size: 1
  - name: SPF
    description: SRAM1 parity error flag This bit is set by hardware when an SRAM1 parity error is detected. It is cleared by software by writing 1.
    bit_offset: 8
    bit_size: 1
fieldset/ITLINE0:
  description: SYSCFG interrupt line 0 status register
  fields:
  - name: WWDG
    description: Window watchdog interrupt pending flag
    bit_offset: 0
    bit_size: 1
fieldset/ITLINE1:
  description: SYSCFG interrupt line 1 status register
  fields:
  - name: PVDOUT
    description: PVD supply monitoring interrupt request pending (EXTI line 16).
    bit_offset: 0
    bit_size: 1
  - name: PVMOUT1
    description: V<sub>DDUSB</sub> supply monitoring interrupt request pending (EXTI line 19)
    bit_offset: 1
    bit_size: 1
  - name: PVMOUT3
    description: ADC supply monitoring interrupt request pending (EXTI line 20)
    bit_offset: 2
    bit_size: 1
  - name: PVMOUT4
    description: DAC supply monitoring interrupt request pending (EXTI line 21)
    bit_offset: 3
    bit_size: 1
fieldset/ITLINE10:
  description: SYSCFG interrupt line 10 status register
  fields:
  - name: DMA1_CH2
    description: DMA1 channel 2 interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: DMA1_CH3
    description: DMA1 channel 3 interrupt request pending
    bit_offset: 1
    bit_size: 1
fieldset/ITLINE11:
  description: SYSCFG interrupt line 11 status register
  fields:
  - name: DMAMUX
    description: DMAMUX interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: DMA1_CH4
    description: DMA1 channel 4 interrupt request pending
    bit_offset: 1
    bit_size: 1
  - name: DMA1_CH5
    description: DMA1 channel 5 interrupt request pending
    bit_offset: 2
    bit_size: 1
  - name: DMA1_CH6
    description: DMA1 channel 6 interrupt request pending
    bit_offset: 3
    bit_size: 1
  - name: DMA1_CH7
    description: DMA1 channel 7 interrupt request pending
    bit_offset: 4
    bit_size: 1
  - name: DMA2_CH1
    description: DMA2 channel 1 interrupt request pending
    bit_offset: 5
    bit_size: 1
  - name: DMA2_CH2
    description: DMA2 channel 2 interrupt request pending
    bit_offset: 6
    bit_size: 1
  - name: DMA2_CH3
    description: DMA2 channel 3 interrupt request pending
    bit_offset: 7
    bit_size: 1
  - name: DMA2_CH4
    description: DMA2 channel 4 interrupt request pending
    bit_offset: 8
    bit_size: 1
  - name: DMA2_CH5
    description: DMA2 channel 5 interrupt request pending
    bit_offset: 9
    bit_size: 1
fieldset/ITLINE12:
  description: SYSCFG interrupt line 12 status register
  fields:
  - name: ADC
    description: ADC interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: COMP1
    description: Comparator 1 interrupt request pending (EXTI line 17)
    bit_offset: 1
    bit_size: 1
  - name: COMP2
    description: Comparator 2 interrupt request pending (EXTI line 18)
    bit_offset: 2
    bit_size: 1
fieldset/ITLINE13:
  description: SYSCFG interrupt line 13 status register
  fields:
  - name: TIM1_CCU
    description: Timer 1 commutation interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: TIM1_TRG
    description: Timer 1 trigger interrupt request pending
    bit_offset: 1
    bit_size: 1
  - name: TIM1_UPD
    description: Timer 1 update interrupt request pending
    bit_offset: 2
    bit_size: 1
  - name: TIM1_BRK
    description: Timer 1 break interrupt request pending
    bit_offset: 3
    bit_size: 1
fieldset/ITLINE14:
  description: SYSCFG interrupt line 14 status register
  fields:
  - name: TIM1_CC1
    description: Timer 1 capture compare 1 interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: TIM1_CC2
    description: Timer 1 capture compare 2 interrupt request pending
    bit_offset: 1
    bit_size: 1
  - name: TIM1_CC3
    description: Timer 1 capture compare 3 interrupt request pending
    bit_offset: 2
    bit_size: 1
  - name: TIM1_CC4
    description: Timer 1 capture compare 4 interrupt request pending
    bit_offset: 3
    bit_size: 1
fieldset/ITLINE15:
  description: SYSCFG interrupt line 15 status register
  fields:
  - name: TIM2
    description: Timer 2 interrupt request pending
    bit_offset: 0
    bit_size: 1
fieldset/ITLINE16:
  description: SYSCFG interrupt line 16 status register
  fields:
  - name: TIM3
    description: Timer 3 interrupt request pending
    bit_offset: 0
    bit_size: 1
fieldset/ITLINE17:
  description: SYSCFG interrupt line 17 status register
  fields:
  - name: TIM6
    description: Timer 6 interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: DAC
    description: DAC underrun interrupt request pending
    bit_offset: 1
    bit_size: 1
  - name: LPTIM1
    description: Low-power timer 1 interrupt request pending (EXTI line 29)
    bit_offset: 2
    bit_size: 1
fieldset/ITLINE18:
  description: SYSCFG interrupt line 18 status register
  fields:
  - name: TIM7
    description: Timer 7 interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: LPTIM2
    description: Low-power timer 2 interrupt request pending (EXTI line 30)
    bit_offset: 1
    bit_size: 1
fieldset/ITLINE19:
  description: SYSCFG interrupt line 19 status register
  fields:
  - name: TIM15
    description: Timer 15 interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: LPTIM3
    description: Low-power timer 3 interrupt request pending
    bit_offset: 1
    bit_size: 1
fieldset/ITLINE2:
  description: SYSCFG interrupt line 2 status register
  fields:
  - name: TAMP
    description: Tamper interrupt request pending (EXTI line 21)
    bit_offset: 0
    bit_size: 1
  - name: RTC
    description: RTC interrupt request pending (EXTI line 19)
    bit_offset: 1
    bit_size: 1
fieldset/ITLINE20:
  description: SYSCFG interrupt line 20 status register
  fields:
  - name: TIM16
    description: Timer 16 interrupt request pending
    bit_offset: 0
    bit_size: 1
fieldset/ITLINE21:
  description: SYSCFG interrupt line 21 status register
  fields:
  - name: TSC_MCE
    description: TSC max count error interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: TSC_EOA
    description: TSC end of acquisition interrupt request pending
    bit_offset: 1
    bit_size: 1
fieldset/ITLINE22:
  description: SYSCFG interrupt line 22 status register
  fields:
  - name: LCD
    description: LCD interrupt request pending
    bit_offset: 0
    bit_size: 1
fieldset/ITLINE23:
  description: SYSCFG interrupt line 23 status register
  fields:
  - name: I2C1
    description: I2C1 interrupt request pending (EXTI line 33)
    bit_offset: 0
    bit_size: 1
fieldset/ITLINE24:
  description: SYSCFG interrupt line 24 status register
  fields:
  - name: I2C2
    description: I2C2 interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: I2C4
    description: I2C4 interrupt request pending
    bit_offset: 1
    bit_size: 1
  - name: I2C3
    description: I2C3 interrupt request pending (EXTI line 23)
    bit_offset: 2
    bit_size: 1
fieldset/ITLINE25:
  description: SYSCFG interrupt line 25 status register
  fields:
  - name: SPI1
    description: SPI1 interrupt request pending
    bit_offset: 0
    bit_size: 1
fieldset/ITLINE26:
  description: SYSCFG interrupt line 26 status register
  fields:
  - name: SPI2
    description: SPI2 interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: SPI3
    description: SPI3 interrupt request pending
    bit_offset: 1
    bit_size: 1
fieldset/ITLINE27:
  description: SYSCFG interrupt line 27 status register
  fields:
  - name: USART1
    description: USART1 interrupt request pending, combined with EXTI line 25
    bit_offset: 0
    bit_size: 1
fieldset/ITLINE28:
  description: SYSCFG interrupt line 28 status register
  fields:
  - name: USART2
    description: USART2 interrupt request pending (EXTI line 35)
    bit_offset: 0
    bit_size: 1
  - name: LPUART2
    description: LPUART2 interrupt request pending (EXTI line 31)
    bit_offset: 1
    bit_size: 1
fieldset/ITLINE29:
  description: SYSCFG interrupt line 29 status register
  fields:
  - name: USART3
    description: USART3 interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: LPUART1
    description: LPUART1 interrupt request pending (EXTI line 30)
    bit_offset: 1
    bit_size: 1
fieldset/ITLINE3:
  description: SYSCFG interrupt line 3 status register
  fields:
  - name: FLASH_ITF
    description: Flash interface interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: FLASH_ECC
    description: Flash interface ECC interrupt request pending
    bit_offset: 1
    bit_size: 1
fieldset/ITLINE30:
  description: SYSCFG interrupt line 30 status register
  fields:
  - name: USART4
    description: USART4 interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: LPUART3
    description: LPUART3 interrupt request pending (EXTI line 32)
    bit_offset: 1
    bit_size: 1
fieldset/ITLINE31:
  description: SYSCFG interrupt line 31 status register
  fields:
  - name: RNG
    description: RNG interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: AES
    description: AES interrupt request pending
    bit_offset: 1
    bit_size: 1
fieldset/ITLINE4:
  description: SYSCFG interrupt line 4 status register
  fields:
  - name: RCC
    description: Reset and clock control interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: CRS
    description: CRS interrupt request pending
    bit_offset: 1
    bit_size: 1
fieldset/ITLINE5:
  description: SYSCFG interrupt line 5 status register
  fields:
  - name: EXTI0
    description: EXTI line 0 interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: EXTI1
    description: EXTI line 1 interrupt request pending
    bit_offset: 1
    bit_size: 1
fieldset/ITLINE6:
  description: SYSCFG interrupt line 6 status register
  fields:
  - name: EXTI2
    description: EXTI line 2 interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: EXTI3
    description: EXTI line 3 interrupt request pending
    bit_offset: 1
    bit_size: 1
fieldset/ITLINE7:
  description: SYSCFG interrupt line 7 status register
  fields:
  - name: EXTI4
    description: EXTI line 4 interrupt request pending
    bit_offset: 0
    bit_size: 1
  - name: EXTI5
    description: EXTI line 5 interrupt request pending
    bit_offset: 1
    bit_size: 1
  - name: EXTI6
    description: EXTI line 6 interrupt request pending
    bit_offset: 2
    bit_size: 1
  - name: EXTI7
    description: EXTI line 7 interrupt request pending
    bit_offset: 3
    bit_size: 1
  - name: EXTI8
    description: EXTI line 8 interrupt request pending
    bit_offset: 4
    bit_size: 1
  - name: EXTI9
    description: EXTI line 9 interrupt request pending
    bit_offset: 5
    bit_size: 1
  - name: EXTI10
    description: EXTI line 10 interrupt request pending
    bit_offset: 6
    bit_size: 1
  - name: EXTI11
    description: EXTI line 11 interrupt request pending
    bit_offset: 7
    bit_size: 1
  - name: EXTI12
    description: EXTI line 12 interrupt request pending
    bit_offset: 8
    bit_size: 1
  - name: EXTI13
    description: EXTI line 13 interrupt request pending
    bit_offset: 9
    bit_size: 1
  - name: EXTI14
    description: EXTI line 14 interrupt request pending
    bit_offset: 10
    bit_size: 1
  - name: EXTI15
    description: EXTI line 15 interrupt request pending
    bit_offset: 11
    bit_size: 1
fieldset/ITLINE8:
  description: SYSCFG interrupt line 8 status register
  fields:
  - name: USB
    description: USB interrupt request pending
    bit_offset: 0
    bit_size: 1
fieldset/ITLINE9:
  description: SYSCFG interrupt line 9 status register
  fields:
  - name: DMA1_CH1
    description: DMA1 channel 1 interrupt request pending
    bit_offset: 0
    bit_size: 1
fieldset/SCSR:
  description: SYSCFG SRAM2 control and status register
  fields:
  - name: SRAM2ER
    description: 'SRAM2 erase Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at the end of the SRAM2 erase operation. Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register.'
    bit_offset: 0
    bit_size: 1
  - name: SRAM2BSY
    description: SRAM2 busy by erase operation
    bit_offset: 1
    bit_size: 1
fieldset/SKR:
  description: SYSCFG SRAM2 key register
  fields:
  - name: KEY
    description: 'SRAM2 write protection key for software erase The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register: Write 0xCA into KEY[7:0] Write 0x53 into KEY[7:0] Writing a wrong key reactivates the write protection.'
    bit_offset: 0
    bit_size: 8
fieldset/TSCCR:
  description: SYSCFG TSC comparator register
  fields:
  - name: G2_IO1
    description: Comparator mode for group 2 on I/O 1
    bit_offset: 0
    bit_size: 1
  - name: G2_IO3
    description: Comparator mode for group 2 on I/O 3
    bit_offset: 1
    bit_size: 1
  - name: G4_IO3
    description: Comparator mode for group 4 on I/O 3
    bit_offset: 2
    bit_size: 1
  - name: G6_IO1
    description: Comparator mode for group 6 on I/O 1
    bit_offset: 3
    bit_size: 1
  - name: G7_IO1
    description: Comparator mode for group 7 on I/O 1
    bit_offset: 4
    bit_size: 1
  - name: TSC_IOCTRL
    description: I/O control in comparator mode The I/O control in comparator mode can be overwritten by hardware.
    bit_offset: 5
    bit_size: 1
enum/IR_MOD:
  bit_size: 2
  variants:
  - name: TIM16
    description: TIM16
    value: 0
  - name: USART1
    description: USART1
    value: 1
  - name: USART2
    description: USART2
    value: 2
enum/MEM_MODE:
  bit_size: 2
  variants:
  - name: System_Flash
    description: System flash memory mapped at 0x000010000
    value: 1
  - name: SRAM
    description: Embedded SRAM mapped at 0x000010000
    value: 3