eZio Pan
d20904a208
refactor with clippy
2023-12-24 19:07:32 +08:00
Dario Nieuwenhuis
61e278be14
Merge pull request #317 from eZioPan/tim-cleanup
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remove `OCPE`, `OPM`, `ECE` enum of `TIM`
2023-12-23 14:39:26 +00:00
eZio Pan
837685460b
remove OCPE, OPM, ECE enum of TIM
2023-12-23 18:54:07 +08:00
Dario Nieuwenhuis
2234f380f5
Merge pull request #316 from eZioPan/dma-cleanup
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DMA cleanup
2023-12-19 10:59:54 +00:00
eZio Pan
9a5ac3abce
DMA cleanup
2023-12-19 13:47:15 +08:00
Dario Nieuwenhuis
91cee0d1fd
Merge pull request #315 from eZioPan/rm-enum-tim-cr1-arpe
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remove TIM CR1 ARPE enums, it just a enable/disable field
2023-12-14 13:17:34 +00:00
eZio Pan
9e680c8d69
no need TIM CR1 ARPE enum, just a enable/disable field
2023-12-14 21:09:00 +08:00
Dario Nieuwenhuis
8f5fcae8c2
Fix QUADSPI RCC bit names.
2023-12-08 23:43:52 +01:00
Dario Nieuwenhuis
589e8e35d7
Merge pull request #314 from embassy-rs/update-headers
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Update headers.
2023-12-08 22:25:08 +00:00
Dario Nieuwenhuis
6fe2c922b8
Update headers.
2023-12-08 23:19:12 +01:00
Dario Nieuwenhuis
13461b78b5
Merge pull request #313 from embassy-rs/qspi-fix
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Fix qspi for all chips.
2023-12-08 20:57:54 +00:00
Dario Nieuwenhuis
3634020845
Fix qspi for all chips.
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Co-Authored-By: Tupelov <64274155+Tupelov@users.noreply.github.com>
2023-12-08 21:54:03 +01:00
Dario Nieuwenhuis
019a5da1c4
Merge pull request #309 from CaptainMaso/adc-f3_v1_1
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STM32L151C(6,8,B)T ADC
2023-12-08 17:58:09 +00:00
Sam
830341361e
STM32L1 to use ADC1 address instead of incorrect ADC address
2023-12-08 18:55:54 +01:00
Sam
1cc9a2fcca
limit ADC1 clocks fallback for stm32l series
2023-12-08 18:55:54 +01:00
Sam
08c1f451b6
ADC stm32l151c8 specifics
2023-12-08 18:55:53 +01:00
Sam
b53fd35116
ADC afit_v1_1 implementation
2023-12-08 18:55:38 +01:00
Dario Nieuwenhuis
b6181ce3f3
Merge pull request #308 from tcbennun/fdcan-fix
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fdcan: add H7 support; fix regs for others; add message RAM blocks
2023-12-08 17:21:24 +00:00
Dario Nieuwenhuis
ea6b2aa1bb
Merge pull request #312 from aurelj/adc_remove_extsel
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ADC: remove EXTSEL and JEXTSEL enum as they can be inconsistent between chips
2023-12-06 20:40:12 +00:00
Aurélien Jacobs
2e467a5373
ADC: remove EXTSEL and JEXTSEL enum as they can be inconsistent between chips
2023-12-06 18:27:20 +01:00
Dario Nieuwenhuis
7117ad49c0
Merge pull request #306 from adamgreig/g4-dac
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Rework DAC support for all STM32s
2023-11-24 22:57:00 +00:00
Torin Cooper-Bennun
d5d131a702
rcc: g4,l5: add missing enums for FDCANSEL; fix a few incorrect descs
2023-11-21 14:57:43 +00:00
Torin Cooper-Bennun
389f547c13
fdcan: array-ify fields with 1 bit per FIFO element
2023-11-21 12:42:29 +00:00
Torin Cooper-Bennun
27c71ac451
fdcan: generate register blocks for message RAM
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this is a special case, as most data sources don't mention this as a
separate peripheral at all, and those that do don't handle the offsets
in the case of multiple FDCANS
H7 chips have a single 10KB block shared between all FDCANs
2023-11-21 10:45:51 +00:00
Torin Cooper-Bennun
90ff5316eb
rcc: fix FDCAN: multiple FDCANs share the same RCC fields
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the RCC fields are named either FDCAN or FDCAN12
2023-11-21 10:45:51 +00:00
Torin Cooper-Bennun
f65fd694e1
fdcan: fix register block definitions; separate version for H7
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the Cube XMLs refer to "fdcan_v1_0" and "fdcan_v1_1" but these seem to
have no bearing on the actual registers used. Thus chips.rs should make
no distinction between v1_0 and v1_1.
the previous YAML seems to have been generated from a G4 SVD, but this
series' SVDs consistently have several errata.
I have therefore replaced can_fdcan.yaml with can_fdcan_v1.yaml, built
from an H5 SVD which appears to match the RMs of G0, G4, H5 and L5
chips.
the H7 series has a totally different FDCAN, so I've added a separate
YAML for it.
2023-11-21 10:45:51 +00:00
Adam Greig
be9d7fd584
H5: rename DAC12EN to DAC1EN to match peripheral name
2023-11-19 13:47:13 +00:00
Adam Greig
a0f7bc881a
WL5/WLE: rename DAC1EN to DACEN in RCC, per reference manual and peripheral name
2023-11-19 13:29:43 +00:00
Adam Greig
78232c013e
Rework DACs for all STM32
2023-11-19 04:51:20 +00:00
Adam Greig
82101c985c
DAC v1-4: Remove TSEL enum from TSEL fields, arrayify TSEL fields
2023-11-19 04:51:20 +00:00
Adam Greig
7ce7dc901f
Add DACv4 support for STM32G4
2023-11-19 04:51:19 +00:00
Dario Nieuwenhuis
f6d1ffc1a2
Fix G0 USB interrupts.
2023-11-18 01:39:07 +01:00
Dario Nieuwenhuis
4852f5040a
Ensure no duplicate irqs with the same signal.
2023-11-18 00:39:24 +01:00
Dario Nieuwenhuis
f5a4c58efa
Remove USB_DRD_FS rename hack.
2023-11-18 00:00:14 +01:00
Dario Nieuwenhuis
f0866ffbc4
Check for non-existing interrupts earlier.
2023-11-17 23:55:55 +01:00
Dario Nieuwenhuis
221d24f6f8
Parse interrupts on demand for each chip instead of upfront.
2023-11-17 23:42:07 +01:00
Dario Nieuwenhuis
fbb8f77326
rcc: consistency fixes on f2
2023-11-13 01:47:21 +01:00
Dario Nieuwenhuis
c551c07bf1
rcc: consistency fixes.
2023-11-13 01:00:53 +01:00
xoviat
8e0b734459
Merge pull request #307 from xoviat/macros
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macros: handle one enum field
2023-11-07 00:07:08 +00:00
xoviat
69706e61e4
macros: handle one enum field
2023-11-06 18:01:39 -06:00
xoviat
1374ed6227
Merge pull request #304 from xoviat/cache
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ci: cache sources
2023-11-05 23:07:44 +00:00
xoviat
8ae9a1f2a9
quiet clones
2023-11-05 17:05:25 -06:00
xoviat
2e3736a558
ci: cache sources
2023-11-05 16:52:45 -06:00
Dario Nieuwenhuis
8381654ade
crs: add for l5.
2023-11-05 23:37:05 +01:00
xoviat
04d773b7b3
Merge pull request #303 from xoviat/low-power
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add stop mode rcc data
2023-11-05 22:29:38 +00:00
Dario Nieuwenhuis
e78c8c9d94
crs: add for all chips.
2023-11-05 23:12:27 +01:00
xoviat
54fedeeefa
don't serialize default stop mode
2023-11-05 16:11:58 -06:00
xoviat
62567511fb
Merge branch 'main' of https://github.com/embassy-rs/stm32-data into low-power
2023-11-05 15:59:50 -06:00
Dario Nieuwenhuis
3f7663279f
generated: add --allow-empty
2023-11-05 22:56:05 +01:00
xoviat
b9efaf36d8
add stop mode rcc data
2023-11-05 15:52:50 -06:00
