chemicstry
706d803b17
Cleanup RTCv1 register names
2022-06-05 22:52:52 +02:00
chemicstry
419e4aa9fe
Fixup names
2022-06-05 22:52:52 +02:00
chemicstry
660faf14dd
Add missing enums
2022-06-05 22:52:52 +02:00
chemicstry
6811a09679
Fix names
2022-06-05 22:52:52 +02:00
chemicstry
85162f723f
Manually cleanup all RTC registers
2022-06-05 22:52:52 +02:00
chemicstry
42cd969fcd
WIP: merging RTCv2 registers
2022-06-05 22:52:52 +02:00
chemicstry
82110c6686
Fix control characters
2022-06-05 22:52:52 +02:00
chemicstry
82c3d2a485
Group rtc regs by version
2022-06-05 22:52:51 +02:00
chemicstry
5ec0ad4387
Add RTC registers for all chips
2022-06-05 22:52:14 +02:00
Dario Nieuwenhuis
1910d1886a
Merge pull request #148 from chemicstry/f1_bkp
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Add F1 BKP peripheral
2022-06-05 22:43:25 +02:00
chemicstry
22386bae0c
Use offsets for non-contiguous array
2022-06-04 21:18:48 +03:00
Dario Nieuwenhuis
8cd6b1e17b
Merge pull request #145 from jensenn/lcd-peripheral
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Add LCD peripheral
2022-06-03 18:37:37 +02:00
chemicstry
f0e27880b9
Cleanup
2022-06-03 10:26:58 +03:00
chemicstry
137611f0f6
Merge branch 'main' into f1_bkp
2022-06-03 10:20:14 +03:00
chemicstry
582969eb56
Add F1 BKP peripheral
2022-06-03 10:18:22 +03:00
Dario Nieuwenhuis
ed612cb8a2
usb: unify StatRx, StatTx.
2022-05-30 00:58:52 +02:00
Dario Nieuwenhuis
805f86c8cb
pwr_l5: add missing State0 VOS
2022-05-30 00:58:52 +02:00
Jensenn
846847b9d5
Split LCD peripheral into v1, v2
2022-05-10 13:53:11 -06:00
Dario Nieuwenhuis
987fd8a158
Merge pull request #143 from GrantM11235/f1-rcc-fixup
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Clean up rcc for f1/f1cl and separate f100 rcc
2022-05-07 02:10:37 +02:00
Dario Nieuwenhuis
29af680860
Merge pull request #144 from embassy-rs/flash-cleanup
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Clean-up F3 and F7 flash registers
2022-05-07 02:09:49 +02:00
Jensenn
8b59cb1d85
Fix LCD display memory array
2022-05-06 14:59:23 -06:00
Jensenn
521417bbb0
make LCD display memory an array
2022-05-06 14:26:20 -06:00
Matous Hybl
f2498652f1
Clean-up F3 and F7 flash registers
2022-05-06 21:52:51 +02:00
Grant Miller
423a80a8f8
Fix ADCPRE descriptions
2022-05-01 19:31:43 -05:00
Grant Miller
ad6f5a5434
Clean up rcc_f1cl.yaml
2022-05-01 19:29:40 -05:00
Grant Miller
e905859bdf
Clean up rcc_f1.yaml
2022-05-01 19:28:29 -05:00
Grant Miller
d7674ab524
Create rcc_f100.yaml
2022-05-01 19:27:28 -05:00
Grant Miller
9ea9bd5215
Prevent crash if xENR exists but xRSTR doesn't
2022-05-01 19:20:48 -05:00
Dario Nieuwenhuis
c36a510e47
unify ETH vs ETHMAC in RCC regs.
2022-04-28 01:54:55 +02:00
Dario Nieuwenhuis
b8325a23ac
Merge pull request #142 from embassy-rs/generate-flash-settings
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Generate flash settings
2022-04-27 14:34:55 +02:00
Ulf Lilleengen
4535a98b19
Use the largest sector size
2022-04-27 14:20:29 +02:00
Ulf Lilleengen
bd97be07b3
Generate more flash settings
2022-04-27 13:25:48 +02:00
Matous Hybl
0c9329fe94
Add ADC3 common for H7s
2022-04-27 00:51:20 +02:00
Matous Hybl
a87cf34197
Add ADC registers for F1 and H7
2022-04-27 00:50:46 +02:00
Dario Nieuwenhuis
eff26e3e77
Add stm32u5 GPDMA, SPI
2022-04-26 23:53:28 +02:00
Dario Nieuwenhuis
bb6053d4ee
chiptool fmt
2022-04-26 21:16:00 +02:00
Dario Nieuwenhuis
6e8a2d8868
Merge pull request #141 from Gekkio/f2-spi
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Add SPI for F2 devices (spi2s1_v2_1)
2022-04-26 19:32:52 +02:00
Joonas Javanainen
ad291b5af3
Map spi2s1_v2_1 used on F2 devices
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This seems identical to v2_2 (as used by F429) with one naming exception
in status register SR bit 8 (TI frame format error):
v2_1 data names the bit "TIFRFE" and the enum TIFRERR
v2_2 data names the bit "FRE" and the enum FRER
The register bit layout is identical.
2022-04-26 20:24:36 +03:00
Dario Nieuwenhuis
2db5d47cc6
Merge pull request #140 from davidlenfesty/eth-v1a
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Generate support for ethernet v1a and v1b
2022-04-26 18:28:41 +02:00
Dario Nieuwenhuis
7e9d04b342
Merge pull request #139 from embassy-rs/stm32wl-flash
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Stm32wl flash
2022-04-26 18:18:13 +02:00
Ulf Lilleengen
afcd7a7d69
Rename flash_w[bl]55 flash_w[bl]
2022-04-26 18:17:09 +02:00
David Lenfesty
121e5bc92b
Generate ethernet peripherals for f2 and f4
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These are eth v1b, according to stm32-rs it should have the same register
changes as v1c, so I just copied it over.
2022-04-26 10:09:28 -06:00
David Lenfesty
05bf8c23c1
fix RCC MCO register for f1 CL variants
2022-04-26 10:04:50 -06:00
Ulf Lilleengen
83544cfdfc
Remove enums from l0 regs
2022-04-26 14:53:40 +02:00
Ulf Lilleengen
004542bf86
Add l0 flash support
2022-04-26 14:51:37 +02:00
Ulf Lilleengen
3dd39de946
Add flash for stm32wl
2022-04-26 14:51:37 +02:00
Jensenn
b7d299d2a8
Update perimap for LCD peripheral
2022-04-25 13:20:57 -06:00
Jensenn
9728ff7a95
Remove useless fieldsets in LCD display memory
2022-04-25 12:08:32 -06:00
Jensenn
974de5f19b
Add BUFEN field from l4xx devices
2022-04-25 12:05:36 -06:00
Jensenn
338c78b771
Add LCD register set from l100 device
2022-04-25 12:04:23 -06:00
