Dario Nieuwenhuis
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c8698f3cd8
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chiptool fmt.
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2024-02-15 23:25:16 +01:00 |
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eZio Pan
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f2c85fb49c
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update timer_v1
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2024-02-15 20:42:08 +01:00 |
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eZio Pan
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e857389850
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Add OR register.
OR1 is the same as OR. The content is different across chip serials. Leave entire register to HAL to parse.
OR2 and OR3 are just AF1 and AF2.
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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9fa345af29
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add TIM_BASIC_NO_CR2, common part of TIM_BASIC and TIM_1CH_CMP
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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10a1a61bae
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let TIM_ADV based on TIM_2CH_CMP
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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cd490fd7f3
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let TIM_GP16 based on TIM_2CH
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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6b5e0c6b4e
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add TIM_CORE, common part of TIM_BASIC and TIM_1CH
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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db6e501fd3
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make 2CH_CMP based on 1CH_CMP
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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771c51b438
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bug fix
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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abb0f63c4a
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tailoring timer_v1 from timer_v2
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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81d09e5782
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branch timer_v1 from timer_v2
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2024-02-05 16:27:10 +08:00 |
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eZio Pan
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837685460b
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remove OCPE, OPM, ECE enum of TIM
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2023-12-23 18:54:07 +08:00 |
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eZio Pan
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9e680c8d69
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no need TIM CR1 ARPE enum, just a enable/disable field
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2023-12-14 21:09:00 +08:00 |
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Dario Nieuwenhuis
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86fb0cfc2f
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chiptool fmt.
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2023-09-16 02:34:03 +02:00 |
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chemicstry
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1d9e453670
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Add missing timer ITR3 field
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2022-03-30 01:59:08 +03:00 |
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Dario Nieuwenhuis
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2c5e858584
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chiptool fmt
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2022-02-14 00:45:36 +01:00 |
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Dario Nieuwenhuis
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c6c5c099bb
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fmt all register yamls
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2021-11-17 21:23:26 +01:00 |
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Dario Nieuwenhuis
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69b1c6a96c
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Add the thing
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2021-04-15 04:42:04 +02:00 |
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