Dario Nieuwenhuis
8534ae884d
rcc: make GPIO EN/RST regs naming consistent.
2021-08-19 23:50:42 +02:00
Timo Kröger
babbe782f3
rcc_l0: Remove non existing RCC bits
...
## firewall
l0x0, l0x1: FWEN - Firewall clock enable bit
l0x2, l0x3: MIFIEN - MiFaRe Firewall clock enable bit
action: none
## watchdog
peripheral: WWDG
WWDGRST vs WWDRST
action: remove
## CRS vs CRC
l0x2, l0x3: CRC reset is wrong
action: remove duplicate CRC bit
## LPUART12RST vs USART2RST
action: rename, it sholud be USART2
2021-08-03 14:31:36 +02:00
Timo Kröger
d1597c646d
rcc_l0: Remove duplicate I2C3 reset bit
2021-08-03 10:55:51 +02:00
Bob McWhirter
9040fafc33
Ensure the RCC reg is named DMA1EN and not just DMAEN
2021-07-12 15:55:13 -04:00
Ulf Lilleengen
c1aae8d3d8
Run through transform again
2021-06-07 12:22:09 +02:00
Ulf Lilleengen
fea5e31f8b
Regen and remove *ON enums
2021-06-03 15:13:46 +02:00
Ulf Lilleengen
529b991404
Do merge
2021-06-03 14:31:27 +02:00
Ulf Lilleengen
18a99a3a3b
Add RCC register for STM32F4 and STM32L4
...
Register block based in STM32F427ZI and STM32L4R9.
Use bool for reset registers.
Define clock mapping for RNG peripherals. There are no 1 <-> 1 mapping
of RNG peripheral to clock in the Cubedb sources. The mapping will
pre-select the clock source for RNG for now.
2021-06-03 11:33:24 +02:00
Ulf Lilleengen
9ad584c149
Remove enums from enable registers
...
Add transform for RCC
2021-06-02 16:32:43 +02:00
Ulf Lilleengen
2ff87b75ce
Add RCC register block for STM32L0
2021-05-20 13:26:25 +02:00
