eZio Pan
6b3a0ec599
pwr-cleanup
2024-01-03 21:35:19 +08:00
eZio Pan
63fffc8917
opamp-cleanup
2024-01-03 21:34:54 +08:00
eZio Pan
8c3f2428b4
ltdc-cleanup
2024-01-03 21:34:29 +08:00
eZio Pan
b6fd3b1bc9
hrtim-cleanup
2024-01-03 21:34:09 +08:00
eZio Pan
2dbc72e316
gpio-cleanup
2024-01-03 21:33:46 +08:00
eZio Pan
a4b31425b9
exti-cleanup
2024-01-03 21:33:26 +08:00
eZio Pan
9e58b83115
eth-cleanup
2024-01-03 21:33:00 +08:00
Dario Nieuwenhuis
760125dee1
Merge pull request #331 from eZioPan/rtc-cleanup2
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Rtc cleanup2
2024-01-02 14:11:27 +00:00
Dario Nieuwenhuis
4d06d09121
Merge pull request #333 from eZioPan/ltdc-cleanup
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ltdc-cleanup
2024-01-02 14:10:21 +00:00
eZio Pan
fcc8ff8c78
fix description
2024-01-02 19:08:51 +08:00
eZio Pan
8e2437a6c3
rtc-cleanup
2024-01-02 19:01:53 +08:00
eZio Pan
fc4bca09cc
ltdc-cleanup
2024-01-02 18:58:56 +08:00
eZio Pan
5e6056d36e
flash-cleanup
2024-01-02 18:54:50 +08:00
eZio Pan
aa06d3ab90
chiptool fmt
2024-01-02 18:24:46 +08:00
Dario Nieuwenhuis
a535002553
Merge pull request #325 from chrenderle/main
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Add rtc registers for stm32l5
2024-01-01 21:11:26 +00:00
Dario Nieuwenhuis
ad5c88c0b5
Merge pull request #329 from eZioPan/syscfg-cleanup
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syscfg-cleanup
2024-01-01 20:56:56 +00:00
eZio Pan
a3244693bd
manually fix description
2024-01-01 21:27:34 +08:00
eZio Pan
a21b679c2d
eth_v1: apply chiptool transform
2024-01-01 20:54:54 +08:00
eZio Pan
45efe8a301
merge field PAGE_WP and FPU_IE
2024-01-01 14:49:00 +08:00
eZio Pan
751158dace
syscfg-cleanup
2024-01-01 10:54:33 +08:00
Christian Enderle
0ddf28abe3
dbgmcu: add support for stm32l5
2023-12-28 11:11:40 +01:00
Christian Enderle
031827e535
Minor changes to rtc_v3u5
2023-12-26 11:32:28 +01:00
Christian Enderle
28306c1d75
Added rtc registers for stm32l5
2023-12-26 11:32:15 +01:00
Dario Nieuwenhuis
8caf2f0bda
Merge pull request #323 from eZioPan/bxcan-cleanup
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bxcan-cleanup
2023-12-25 12:55:27 +00:00
eZio Pan
3d9cdb5b43
rename enum of BIDIOE, make meaning clearer
2023-12-25 15:30:17 +08:00
eZio Pan
3efb14e312
bxcan-cleanup
2023-12-25 14:15:36 +08:00
Dario Nieuwenhuis
94c4bbe9d8
Merge pull request #320 from eZioPan/spi-cleanup
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spi-cleanup
2023-12-24 18:59:35 +00:00
eZio Pan
168b85e650
spi-cleanup
2023-12-24 22:40:13 +08:00
Dario Nieuwenhuis
25c76eb0c8
Merge pull request #319 from eZioPan/rtc-cleanup
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rtc-cleanup
2023-12-24 12:09:26 +00:00
eZio Pan
124616527c
rtc-cleanup
2023-12-24 16:47:50 +08:00
eZio Pan
3a54f8d5f5
wwdg-cleanup
2023-12-24 16:46:54 +08:00
eZio Pan
837685460b
remove OCPE, OPM, ECE enum of TIM
2023-12-23 18:54:07 +08:00
eZio Pan
9a5ac3abce
DMA cleanup
2023-12-19 13:47:15 +08:00
eZio Pan
9e680c8d69
no need TIM CR1 ARPE enum, just a enable/disable field
2023-12-14 21:09:00 +08:00
Dario Nieuwenhuis
8f5fcae8c2
Fix QUADSPI RCC bit names.
2023-12-08 23:43:52 +01:00
Dario Nieuwenhuis
6fe2c922b8
Update headers.
2023-12-08 23:19:12 +01:00
Dario Nieuwenhuis
3634020845
Fix qspi for all chips.
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Co-Authored-By: Tupelov <64274155+Tupelov@users.noreply.github.com>
2023-12-08 21:54:03 +01:00
Sam
b53fd35116
ADC afit_v1_1 implementation
2023-12-08 18:55:38 +01:00
Dario Nieuwenhuis
b6181ce3f3
Merge pull request #308 from tcbennun/fdcan-fix
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fdcan: add H7 support; fix regs for others; add message RAM blocks
2023-12-08 17:21:24 +00:00
Aurélien Jacobs
2e467a5373
ADC: remove EXTSEL and JEXTSEL enum as they can be inconsistent between chips
2023-12-06 18:27:20 +01:00
Torin Cooper-Bennun
d5d131a702
rcc: g4,l5: add missing enums for FDCANSEL; fix a few incorrect descs
2023-11-21 14:57:43 +00:00
Torin Cooper-Bennun
389f547c13
fdcan: array-ify fields with 1 bit per FIFO element
2023-11-21 12:42:29 +00:00
Torin Cooper-Bennun
27c71ac451
fdcan: generate register blocks for message RAM
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this is a special case, as most data sources don't mention this as a
separate peripheral at all, and those that do don't handle the offsets
in the case of multiple FDCANS
H7 chips have a single 10KB block shared between all FDCANs
2023-11-21 10:45:51 +00:00
Torin Cooper-Bennun
f65fd694e1
fdcan: fix register block definitions; separate version for H7
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the Cube XMLs refer to "fdcan_v1_0" and "fdcan_v1_1" but these seem to
have no bearing on the actual registers used. Thus chips.rs should make
no distinction between v1_0 and v1_1.
the previous YAML seems to have been generated from a G4 SVD, but this
series' SVDs consistently have several errata.
I have therefore replaced can_fdcan.yaml with can_fdcan_v1.yaml, built
from an H5 SVD which appears to match the RMs of G0, G4, H5 and L5
chips.
the H7 series has a totally different FDCAN, so I've added a separate
YAML for it.
2023-11-21 10:45:51 +00:00
Adam Greig
be9d7fd584
H5: rename DAC12EN to DAC1EN to match peripheral name
2023-11-19 13:47:13 +00:00
Adam Greig
a0f7bc881a
WL5/WLE: rename DAC1EN to DACEN in RCC, per reference manual and peripheral name
2023-11-19 13:29:43 +00:00
Adam Greig
78232c013e
Rework DACs for all STM32
2023-11-19 04:51:20 +00:00
Adam Greig
82101c985c
DAC v1-4: Remove TSEL enum from TSEL fields, arrayify TSEL fields
2023-11-19 04:51:20 +00:00
Adam Greig
7ce7dc901f
Add DACv4 support for STM32G4
2023-11-19 04:51:19 +00:00
Dario Nieuwenhuis
fbb8f77326
rcc: consistency fixes on f2
2023-11-13 01:47:21 +01:00
