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677 Commits

Author SHA1 Message Date
ExplodingWaffle
30dcf3cabe remove UCPD_ prefixes, remove unneeded enums 2023-09-01 16:24:11 +01:00
ExplodingWaffle
82f8d72be7 add ucpd 2023-09-01 15:59:29 +01:00
xoviat
6146d25433 pwr/wl5: remove some enums 2023-08-27 10:06:24 -05:00
Dario Nieuwenhuis
114bd7fb46 h7/flash: add missing CRCRDERR 2023-08-18 22:43:11 +02:00
Dominik Sliwa
6b2f2c3ac3 split H7 flash for stm32h7a3/b3/b0 chips 2023-08-18 22:13:58 +02:00
Don Reilly
dff9c321f3 readd DBGMCU back into F3 and F3v2 2023-08-07 15:04:18 -05:00
Don Reilly
42273a7f02 rework f3 series rcc take 2 2023-08-07 14:38:22 -05:00
xoviat
f427d49566 adc/f3: cleanup enums 2023-08-06 15:28:34 -05:00
Don Reilly
51371cb835 add vrefintcal for f3 2023-08-05 22:23:05 -05:00
Don Reilly
5953194935 cleaning up mess after fixing headers.rs 2023-08-05 22:14:32 -05:00
Don Reilly
39d4db37fe get common registers for adc12(34) 2023-08-05 18:27:00 -05:00
xoviat
0ac0a44bb0 lptim: consolidate and add for stm32wb 2023-08-03 20:28:33 -05:00
Don Reilly
759fa53724 fix adc_f3 resolution namings to match existing convention across 2023-08-03 11:15:36 -05:00
xoviat
5dbdc9b0ca adc/f3: fix sample time enum 2023-08-02 20:48:32 -05:00
Dario Nieuwenhuis
9d536f55a8
Merge pull request #221 from xoviat/adc 
adc: add f3
 2023-07-22 15:42:34 +00:00
JuliDi
a910aa76fc
fix wrong indentation 2023-07-22 16:50:44 +02:00
JuliDi
2abb498685
adapt DAC trigger enum for v3 2023-07-22 16:48:08 +02:00
JuliDi
57ccc6a59b
add DAC v3 2023-07-22 16:25:15 +02:00
xoviat
4b06fdbf76 adc/f3: naming 2023-07-12 19:43:25 -05:00
xoviat
5ae0934c28 adc/f3: more cleanup 2023-07-12 19:42:31 -05:00
xoviat
c943b0472d adc/f3: more cleanup 2023-07-12 18:00:55 -05:00
xoviat
cada030e1a adc/f3: more cleanup 2023-07-12 17:45:39 -05:00
xoviat
48041c787e adc/f3: some cleanup 2023-07-12 17:33:23 -05:00
xoviat
feb4f685ed adc: add f3 2023-07-11 21:10:08 -05:00
Dario Nieuwenhuis
0ad838d889
Merge pull request #213 from xoviat/hrtim 
hrtim: add common registers and v2
 2023-07-08 08:40:13 +00:00
Dario Nieuwenhuis
793aeb9289
Merge pull request #209 from JcBernack/rng-update 
update RNG registers and mapping
 2023-07-07 15:24:57 +00:00
Dario Nieuwenhuis
d54274df23
Merge pull request #216 from xoviat/fdcan 
add fdcan
 2023-07-07 14:53:43 +00:00
xoviat
4bbc7a3d12 rcc/f3: add hrtim clock 2023-07-06 20:12:22 -05:00
xoviat
b91dd597d3 fdcan: arraify 2023-07-04 13:20:24 -05:00
xoviat
1e9103cd22 fdcan: add registers 2023-07-04 13:04:54 -05:00
xoviat
b7f7cb95f9 hrtim: fix registers, adc offsets 2023-07-02 15:22:21 -05:00
xoviat
c496da8628 hrtim/v2: add registers 2023-07-02 14:13:46 -05:00
xoviat
d8779b6992 hrtim/v1: remove extra enums 2023-07-02 13:58:08 -05:00
xoviat
5531ec8273 hrtim/v1: add remanining registers 2023-07-02 11:45:28 -05:00
xoviat
51c7a56fba hrtim/v1: fix some registers 2023-07-01 17:18:28 -05:00
xoviat
a0e307ab25 hrtim/v1: add some missing registers 2023-07-01 16:40:12 -05:00
Jan Christoph Bernack
f1b05d243d
update RNG registers and mapping 2023-06-30 17:44:07 +02:00
Dario Nieuwenhuis
91ec06089b spi: remove useless enums. 2023-06-29 01:48:37 +02:00
Dario Nieuwenhuis
1678c9f1e1 rtc: remove useless enums. 2023-06-29 00:59:16 +02:00
Dario Nieuwenhuis
1cfb795d6b Fix accidental arrayifications. 2023-06-29 00:57:25 +02:00
Dario Nieuwenhuis
3f01ff4545 Remove enum_read, enum_write. 2023-06-28 22:36:19 +02:00
Dario Nieuwenhuis
0d958def0e chiptool fmt. 2023-06-28 22:22:17 +02:00
Cliff L. Biffle
3c49b933fc gpio_v2: remove another case where indexing was potentially misleading 
The field docs suggested that the index was in the range 0..15, which is
not true in this case.
 2023-06-28 11:18:58 -07:00
Dario Nieuwenhuis
a80ddd6acd
Merge pull request #207 from cbiffle/gpio-v2-afr-array-docs 
gpio_v2: expand docs on AFRx register pair to describe indexing.
 2023-06-28 18:11:29 +00:00
Cliff L. Biffle
d8592bdd8c gpio_v2: expand docs on AFRx register pair to describe indexing. 2023-06-28 11:06:26 -07:00
Cliff L. Biffle
b93e9286d3 G0/C0: fix SYSCFG.CFGR1.MEM_MODE definition 
- Added docs from reference manual / fixed existing partial copy of
  reference manual docs
- Renamed System Flash case to SYSTEM_FLASH because FLASH was ambiguous
  (you really don't want to activate the System Flash when you wanted
  Main Flash, where your program lives!)
- Added Main Flash case.
 2023-06-28 10:06:46 -07:00
Cliff L. Biffle
3d86ef6d30 G0 SYSCFG: fix PA11/PA12 RMP definitions 
It looks like the G0 file here picked up the F0-style "one remapping bit
for both pins" field definition. The G0 series actually has C0-style
dual remapping bits.
 2023-06-28 08:50:53 -07:00
Dario Nieuwenhuis
30747405c8 otg: Increase max amount of EPs. 
H7 has 9 EPs, registers seem laid out for up to 16 EPs so use that.
 2023-06-27 04:07:18 +02:00
Kevin Lannen
efc220eb38 CRS: Use L0 CRS definitions for G0 and G4 
Comparing the register definitions these peripherals are identical.
 2023-06-20 09:48:09 -06:00
Kevin Lannen
a1189407f7 STM32G4: Add enum for CLK48SEL 2023-06-19 16:26:48 -06:00