hrtim/v1: fix some registers
This commit is contained in:
parent
a0e307ab25
commit
51c7a56fba
@ -115,428 +115,6 @@ block/HRTIM:
|
||||
description: "High Resolution Timer: DLL Control Register"
|
||||
byte_offset: 0x3cc
|
||||
fieldset: HRTIM_DLLCR
|
||||
fieldset/HRTIM_CR1:
|
||||
description: "High Resolution Timer: Control Register 1"
|
||||
items:
|
||||
- name: MUDIS
|
||||
description: Master Update Disable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TUDIS
|
||||
description: Timer X Update Disable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
- name: ADUSRC
|
||||
description: ADC Trigger X Update Source
|
||||
bit_offset: 16
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 4
|
||||
stride: 2
|
||||
enum: UPDATESOURCE
|
||||
fieldset/HRTIM_CR2:
|
||||
description: "High Resolution Timer: Control Register 2"
|
||||
items:
|
||||
- name: MSWU
|
||||
description: Master Timer Software Update
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TSWU
|
||||
description: Timer X Software Update
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
- name: MRST
|
||||
description: Master Counter Software Reset
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: TRST
|
||||
description: Timer X Counter Software Reset
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
fieldset/HRTIM_ISR:
|
||||
description: "High Resolution Timer: Interrupt Status Register"
|
||||
items:
|
||||
- name: FLT
|
||||
description: Fault X Interrupt Flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
- name: SYSFLT
|
||||
description: System Fault Interrupt Flag
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DLLRDY
|
||||
description: DLL Ready Interrupt Flag
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: BMPER
|
||||
description: Burst Mode Period Interrupt Flag
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
fieldset/HRTIM_ICR:
|
||||
description: "High Resolution Timer: Interrupt Clear Register"
|
||||
items:
|
||||
- name: FLT
|
||||
description: Fault X Interrupt Flag Clear
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
- name: SYSFLT
|
||||
description: System Fault Interrupt Flag Clear
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DLLRDY
|
||||
description: DLL Ready Interrupt Flag Clear
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: BMPER
|
||||
description: Burst Mode Period Interrupt Flag Clear
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
fieldset/HRTIM_IER:
|
||||
description: "High Resolution Timer: Interrupt Enable Register"
|
||||
items:
|
||||
- name: FLT
|
||||
description: Fault X Interrupt Flag Enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
- name: SYSFLT
|
||||
description: System Fault Interrupt Flag Enable
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DLLRDY
|
||||
description: DLL Ready Interrupt Flag Enable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: BMPER
|
||||
description: Burst Mode Period Interrupt Flag Enable
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
fieldset/HRTIM_OENR:
|
||||
description: "High Resolution Timer: Output Enable Register"
|
||||
items:
|
||||
- name: T1OEN
|
||||
description: "Timer X Output Enable"
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 2
|
||||
- 4
|
||||
- 6
|
||||
- 8
|
||||
- name: T2OEN
|
||||
description: "Timer X Complementary Output Enable"
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 2
|
||||
- 4
|
||||
- 6
|
||||
- 8
|
||||
fieldset/HRTIM_ODISR:
|
||||
description: "High Resolution Timer: Output Disable Register"
|
||||
items:
|
||||
- name: T1ODIS
|
||||
description: "Timer X Output Disable"
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 2
|
||||
- 4
|
||||
- 6
|
||||
- 8
|
||||
- name: T2ODIS
|
||||
description: "Timer X Complementary Output Disable"
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 2
|
||||
- 4
|
||||
- 6
|
||||
- 8
|
||||
fieldset/HRTIM_ODSR:
|
||||
description: "High Resolution Timer: Output Disable Status Register"
|
||||
items:
|
||||
- name: T1ODIS
|
||||
description: "Timer X Output Disable Status"
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 2
|
||||
- 4
|
||||
- 6
|
||||
- 8
|
||||
- name: T2ODIS
|
||||
description: "Timer X Complementary Output Disable Status"
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 2
|
||||
- 4
|
||||
- 6
|
||||
- 8
|
||||
fieldset/HRTIM_BMCR:
|
||||
description: "High Resolution Timer: Burst Mode Control Register"
|
||||
items:
|
||||
- name: BME
|
||||
description: Burst Mode Enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: BMOM
|
||||
description: Burst Mode Operating Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: BMCLK
|
||||
description: Burst Mode Clock source
|
||||
bit_offset: 2
|
||||
bit_size: 3
|
||||
- name: BMPRSC
|
||||
description: Burst Mode Prescaler
|
||||
bit_offset: 6
|
||||
bit_size: 3
|
||||
- name: BMPREN
|
||||
description: Burst Mode Preload Enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: MTBM
|
||||
description: Master Timer Burst Mode
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TBM
|
||||
description: Timer X Burst Mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
- name: BMSTAT
|
||||
decription: Burst Mode Status
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/HRTIM_BMTRGR:
|
||||
description: "High Resolution Timer: Burst Mode Trigger Register"
|
||||
items:
|
||||
- name: SW
|
||||
description: Software start
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: MSTRST
|
||||
description: Master reset or roll-over
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MSTREP
|
||||
description: Master repetition
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: MSTCMP
|
||||
description: Master Compare X
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 1
|
||||
- name: TRST
|
||||
description: Timer X reset or roll-over
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 16
|
||||
- name: TREP
|
||||
description: Timer X repetition
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 16
|
||||
- name: TCMP1
|
||||
description: Timer X compare 1 event
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 16
|
||||
- name: TCMP2
|
||||
description: Timer X compare 2 event
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 16
|
||||
fieldset/HRTIM_BMCMPR:
|
||||
description: "High Resolution Timer: Burst Mode Compare Register"
|
||||
items:
|
||||
- name: BMCMP
|
||||
description: Burst mode compare value
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/HRTIM_BMPERs:
|
||||
description: "High Resolution Timer: Burst Mode Period Register"
|
||||
items:
|
||||
- name: BMPER
|
||||
description: Burst mode period value
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/HRTIM_EECR1:
|
||||
description: "High Resolution Timer: External Events Control Register 1"
|
||||
items:
|
||||
- name: EESRC
|
||||
description: External Event X Source
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
- name: EEPOL
|
||||
description: External Event X Polarity
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
- name: EESNS
|
||||
description: External Event X Sensitivity
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
- name: EEFAST
|
||||
description: External Event X Fast Mode
|
||||
bit_offset: 5
|
||||
bit_size: 2
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
fieldset/HRTIM_EECR2:
|
||||
description: "High Resolution Timer: External Events Control Register 2"
|
||||
items:
|
||||
- name: EESRC
|
||||
description: External Event X Source
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
- name: EEPOL
|
||||
description: External Event X Polarity
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
- name: EESNS
|
||||
description: External Event X Sensitivity
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
fieldset/HRTIM_EECR3:
|
||||
description: "High Resolution Timer: External Events Control Register 2"
|
||||
items:
|
||||
- name: EEF
|
||||
description: External Event X filter
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
- name: EEVSD
|
||||
description: External Event Sampling Clock Division
|
||||
bit_offset: 30
|
||||
bit_size: 2
|
||||
fieldset/HRTIM_DLLCR:
|
||||
description: "High Resolution Timer: DLL Control Register"
|
||||
items:
|
||||
- name: CAL
|
||||
description: DLL Calibration Start
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CALEN
|
||||
description: DLL Calibration Enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: CALRTE
|
||||
description: DLL Calibration Rate
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
block/HRTIM_TIMX:
|
||||
description: "High Resolution Timer: Timing Unit"
|
||||
items:
|
||||
@ -647,6 +225,428 @@ block/HRTIM_TIMX:
|
||||
description: Timer X Fault Register
|
||||
byte_offset: 104
|
||||
fieldset: TIMXFLT
|
||||
fieldset/HRTIM_CR1:
|
||||
description: "High Resolution Timer: Control Register 1"
|
||||
fields:
|
||||
- name: MUDIS
|
||||
description: Master Update Disable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TUDIS
|
||||
description: Timer X Update Disable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
- name: ADUSRC
|
||||
description: ADC Trigger X Update Source
|
||||
bit_offset: 16
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 4
|
||||
stride: 2
|
||||
enum: UPDATESOURCE
|
||||
fieldset/HRTIM_CR2:
|
||||
description: "High Resolution Timer: Control Register 2"
|
||||
fields:
|
||||
- name: MSWU
|
||||
description: Master Timer Software Update
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TSWU
|
||||
description: Timer X Software Update
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
- name: MRST
|
||||
description: Master Counter Software Reset
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: TRST
|
||||
description: Timer X Counter Software Reset
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
fieldset/HRTIM_ISR:
|
||||
description: "High Resolution Timer: Interrupt Status Register"
|
||||
fields:
|
||||
- name: FLT
|
||||
description: Fault X Interrupt Flag
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
- name: SYSFLT
|
||||
description: System Fault Interrupt Flag
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DLLRDY
|
||||
description: DLL Ready Interrupt Flag
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: BMPER
|
||||
description: Burst Mode Period Interrupt Flag
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
fieldset/HRTIM_ICR:
|
||||
description: "High Resolution Timer: Interrupt Clear Register"
|
||||
fields:
|
||||
- name: FLT
|
||||
description: Fault X Interrupt Flag Clear
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
- name: SYSFLT
|
||||
description: System Fault Interrupt Flag Clear
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DLLRDY
|
||||
description: DLL Ready Interrupt Flag Clear
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: BMPER
|
||||
description: Burst Mode Period Interrupt Flag Clear
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
fieldset/HRTIM_IER:
|
||||
description: "High Resolution Timer: Interrupt Enable Register"
|
||||
fields:
|
||||
- name: FLT
|
||||
description: Fault X Interrupt Flag Enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
- name: SYSFLT
|
||||
description: System Fault Interrupt Flag Enable
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DLLRDY
|
||||
description: DLL Ready Interrupt Flag Enable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: BMPER
|
||||
description: Burst Mode Period Interrupt Flag Enable
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
fieldset/HRTIM_OENR:
|
||||
description: "High Resolution Timer: Output Enable Register"
|
||||
fields:
|
||||
- name: T1OEN
|
||||
description: "Timer X Output Enable"
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 2
|
||||
- 4
|
||||
- 6
|
||||
- 8
|
||||
- name: T2OEN
|
||||
description: "Timer X Complementary Output Enable"
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 2
|
||||
- 4
|
||||
- 6
|
||||
- 8
|
||||
fieldset/HRTIM_ODISR:
|
||||
description: "High Resolution Timer: Output Disable Register"
|
||||
fields:
|
||||
- name: T1ODIS
|
||||
description: "Timer X Output Disable"
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 2
|
||||
- 4
|
||||
- 6
|
||||
- 8
|
||||
- name: T2ODIS
|
||||
description: "Timer X Complementary Output Disable"
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 2
|
||||
- 4
|
||||
- 6
|
||||
- 8
|
||||
fieldset/HRTIM_ODSR:
|
||||
description: "High Resolution Timer: Output Disable Status Register"
|
||||
fields:
|
||||
- name: T1ODIS
|
||||
description: "Timer X Output Disable Status"
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 2
|
||||
- 4
|
||||
- 6
|
||||
- 8
|
||||
- name: T2ODIS
|
||||
description: "Timer X Complementary Output Disable Status"
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 2
|
||||
- 4
|
||||
- 6
|
||||
- 8
|
||||
fieldset/HRTIM_BMCR:
|
||||
description: "High Resolution Timer: Burst Mode Control Register"
|
||||
fields:
|
||||
- name: BME
|
||||
description: Burst Mode Enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: BMOM
|
||||
description: Burst Mode Operating Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: BMCLK
|
||||
description: Burst Mode Clock source
|
||||
bit_offset: 2
|
||||
bit_size: 3
|
||||
- name: BMPRSC
|
||||
description: Burst Mode Prescaler
|
||||
bit_offset: 6
|
||||
bit_size: 3
|
||||
- name: BMPREN
|
||||
description: Burst Mode Preload Enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: MTBM
|
||||
description: Master Timer Burst Mode
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TBM
|
||||
description: Timer X Burst Mode
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 5
|
||||
stride: 1
|
||||
- name: BMSTAT
|
||||
decription: Burst Mode Status
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/HRTIM_BMTRGR:
|
||||
description: "High Resolution Timer: Burst Mode Trigger Register"
|
||||
fields:
|
||||
- name: SW
|
||||
description: Software start
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: MSTRST
|
||||
description: Master reset or roll-over
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: MSTREP
|
||||
description: Master repetition
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: MSTCMP
|
||||
description: Master Compare X
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 1
|
||||
- name: TRST
|
||||
description: Timer X reset or roll-over
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 16
|
||||
- name: TREP
|
||||
description: Timer X repetition
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 16
|
||||
- name: TCMP1
|
||||
description: Timer X compare 1 event
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 16
|
||||
- name: TCMP2
|
||||
description: Timer X compare 2 event
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 4
|
||||
- 8
|
||||
- 12
|
||||
- 16
|
||||
fieldset/HRTIM_BMCMPR:
|
||||
description: "High Resolution Timer: Burst Mode Compare Register"
|
||||
fields:
|
||||
- name: BMCMP
|
||||
description: Burst mode compare value
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/HRTIM_BMPER:
|
||||
description: "High Resolution Timer: Burst Mode Period Register"
|
||||
fields:
|
||||
- name: BMPER
|
||||
description: Burst mode period value
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/HRTIM_EECR1:
|
||||
description: "High Resolution Timer: External Events Control Register 1"
|
||||
fields:
|
||||
- name: EESRC
|
||||
description: External Event X Source
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
- name: EEPOL
|
||||
description: External Event X Polarity
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
- name: EESNS
|
||||
description: External Event X Sensitivity
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
- name: EEFAST
|
||||
description: External Event X Fast Mode
|
||||
bit_offset: 5
|
||||
bit_size: 2
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
fieldset/HRTIM_EECR2:
|
||||
description: "High Resolution Timer: External Events Control Register 2"
|
||||
fields:
|
||||
- name: EESRC
|
||||
description: External Event X Source
|
||||
bit_offset: 0
|
||||
bit_size: 2
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
- name: EEPOL
|
||||
description: External Event X Polarity
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
- name: EESNS
|
||||
description: External Event X Sensitivity
|
||||
bit_offset: 3
|
||||
bit_size: 2
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
fieldset/HRTIM_EECR3:
|
||||
description: "High Resolution Timer: External Events Control Register 2"
|
||||
fields:
|
||||
- name: EEF
|
||||
description: External Event X filter
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
array:
|
||||
offsets:
|
||||
- 0
|
||||
- 6
|
||||
- 12
|
||||
- 18
|
||||
- 24
|
||||
- name: EEVSD
|
||||
description: External Event Sampling Clock Division
|
||||
bit_offset: 30
|
||||
bit_size: 2
|
||||
fieldset/HRTIM_DLLCR:
|
||||
description: "High Resolution Timer: DLL Control Register"
|
||||
fields:
|
||||
- name: CAL
|
||||
description: DLL Calibration Start
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CALEN
|
||||
description: DLL Calibration Enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: CALRTE
|
||||
description: DLL Calibration Rate
|
||||
bit_offset: 2
|
||||
bit_size: 2
|
||||
fieldset/MCMPX:
|
||||
description: Master Timer Compare X Register
|
||||
fields:
|
||||
|
Loading…
x
Reference in New Issue
Block a user