Dario Nieuwenhuis
709acc1c1c
change interrupts from dict to array
2022-02-07 02:05:30 +01:00
Dario Nieuwenhuis
689c9080ee
cleanup yaml
2022-02-07 02:05:30 +01:00
Dario Nieuwenhuis
f79e304d07
u5/rcc: fix inconsistent DCMI bit names
2022-02-05 03:02:57 +01:00
Dario Nieuwenhuis
c1c3d8b354
stricter irq parsing.
2022-02-05 01:45:46 +01:00
Dario Nieuwenhuis
2a14936a5e
Split interrupt parsing to separate module
2022-02-05 01:45:34 +01:00
Dario Nieuwenhuis
183c31f534
Better instructions in readme for extracting and cleaning peripherals.
2022-02-05 01:41:52 +01:00
Dario Nieuwenhuis
048f6766fd
lpuart: cleanup v1, v2. Merge v2 and v3
2022-02-05 00:59:20 +01:00
Maarten Oosting
6b86d9e104
LPUART: Add registers
2022-02-05 00:59:20 +01:00
Maarten Oosting
e5da7538e1
LPUART: append lpuart peripherals to perimap
2022-02-05 00:59:20 +01:00
Dario Nieuwenhuis
4a6d8b3206
Merge pull request #122 from chemicstry/usb_otg
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Fix missing USB OTG pins
2022-02-05 00:06:55 +01:00
chemicstry
432619467f
Fix encoding on windows
2022-02-04 15:49:56 +02:00
chemicstry
2aaec03094
Fix USB OTG field names in RCC registers
2022-02-04 03:34:08 +02:00
chemicstry
f1d0a09b79
Fix USB OTG pin AF parsing
2022-02-04 02:32:39 +02:00
chemicstry
8e1a07b928
Fix peripheral names with underscores
2022-02-04 01:49:39 +02:00
chemicstry
ce95fe0ac5
Fix path separators on windows
2022-02-04 01:47:29 +02:00
Dario Nieuwenhuis
61bca5a789
rcc/g0: add lots of missing bits
2022-01-24 02:13:53 +01:00
Dario Nieuwenhuis
11290fd274
rcc: make GPIOxEN/IOPxEN consistent.
2022-01-24 02:13:24 +01:00
Dario Nieuwenhuis
60899938fe
Merge pull request #118 from unrelentingtech/l1flash
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Add flash for STM32L1
2022-01-14 16:18:39 +01:00
Greg V
76572f3d55
Add flash for STM32L1
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NOTE: named 'Flash' instead of 'FLASH' in SVD
2022-01-14 16:50:35 +03:00
Dario Nieuwenhuis
fcae7d1e17
Merge pull request #117 from embassy-rs/fix/spi-lsb-unification
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Unify SPI LSBFirst enums.
2022-01-14 11:27:00 +01:00
Matous Hybl
2c7984f962
Unify SPI LSBFirst enums.
2022-01-14 10:23:27 +01:00
Dario Nieuwenhuis
e5e7e26d05
Fix duplicated irqn in stm32f100
2022-01-06 16:30:33 +01:00
Dario Nieuwenhuis
0f04776eaa
rcc: l0, l1, l4: add missing enums.
2022-01-04 23:56:52 +01:00
Dario Nieuwenhuis
7061d52abd
pwr f4, f7: cleanup a bit
2022-01-04 21:10:54 +01:00
Dario Nieuwenhuis
353b2ff610
Merge pull request #116 from Tiwalun/rtc-pwr-flash-wb55
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Add Flash, RTC, PWR for STM32WB55, fix IPCC CPU registers
2022-01-04 19:59:51 +01:00
Dominik Boehi
bb6321bc87
Extract flash information for STM32WB by looking for FLASH_REG_BASE define
2022-01-04 19:38:05 +01:00
Dominik Boehi
d8189255fa
Add Flash, RTC, PWR for STM32WB55, fix IPCC CPU registers
2022-01-04 18:52:34 +01:00
Dario Nieuwenhuis
36e6571960
Add exception for STM32WL SUBGHZSPI naming.
2022-01-01 12:05:51 +01:00
Dario Nieuwenhuis
1ed34d0869
Merge pull request #114 from DCNick3/use-signals-from-mcu-xml
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Use signals from mcu xml
2022-01-01 11:28:44 +01:00
Dario Nieuwenhuis
398fb17bf4
Ignore EXTIx signals in ADCs.
2022-01-01 11:28:02 +01:00
Nikita Strygin
d50f6b4676
Use signals from MCU xml
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Use MCU xml as a source of truth for signal and pin assignments
This has some nice side-effects as exposing analog signals without
handling them as special cases and not having __some__ (or maybe all)
pins not exposed in the chip package occur in the yamls
But the most useful part probably is the better support for F1 series,
which don't have all pins defined in GPIO due to not being remappable
2022-01-01 10:52:39 +01:00
Dario Nieuwenhuis
8e9e8522d1
Sort analog pins
2022-01-01 10:51:45 +01:00
Dario Nieuwenhuis
150bba33db
Merge pull request #115 from sjoerdsimons/wip/sjoerd/stm32f1-adc
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stm32f1xx adc support
2022-01-01 10:34:42 +01:00
Sjoerd Simons
8ed35ce95b
Add registers for F1 ADC block
2021-12-29 15:51:27 +01:00
Sjoerd Simons
2616e499c6
Recognize ADC on STM32F1xx
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Translate the ADC block available in the F1 family to adc_f1
2021-12-29 15:50:38 +01:00
Dario Nieuwenhuis
73902044de
Fix typo
2021-12-23 20:32:39 +01:00
Dario Nieuwenhuis
ce7607e119
Merge pull request #112 from VasanthakumarV/f3-timers
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Assign correct register blocks for F3 Timers
2021-12-23 11:46:55 +01:00
VasanthakumarV
a5008c71d5
[manual] Map register blocks to timers for F3 chips
2021-12-23 16:10:22 +05:30
Dario Nieuwenhuis
0e9fa2f438
Merge pull request #109 from VasanthakumarV/f3-registers
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Add `SYSCFG`, `PWR`, `FLASH` and `SPI` registers for `STM32F3`
2021-12-16 08:12:07 +01:00
VasanthakumarV
b9193128ed
[manual] Make EXTICRx in SYSCFG register an array
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The four variants of EXTICRx has been manually edited into
an array of size and stride four.
The corresponding fieldset was also manually changed.
2021-12-09 13:47:55 +05:30
VasanthakumarV
fdf0cc95b9
[manual] Deduplicate PLLSRC entry of RCC_CFGR register
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I have manually removed the single bit PLLSRC under RCC_CFGR register,
and I have manually updated the `enum/PLLSRC` to have 3 variants to match
the bit_size of PLLSRC.
2021-12-09 13:24:25 +05:30
Dario Nieuwenhuis
8011bfa629
Merge pull request #111 from matoushybl/feat/fmc
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FMC
2021-12-08 20:20:52 +01:00
Matous Hybl
8402040d17
Fix generation of FMC peripheral in chip yamls. Add FMC registers.
2021-12-08 20:01:57 +01:00
VasanthakumarV
3275e41057
[manual] Add register mappings for F3
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Pattern matching for `FLASH`, `SYSCFG`, `PWR` and `SPI` registers
added for F3.
2021-12-08 15:43:23 +05:30
VasanthakumarV
ef950a6feb
[generate] Create SYSCFG, PWR, FLASH register files
2021-12-08 15:43:23 +05:30
Dario Nieuwenhuis
f6c9772cf4
usart: make v1 and v2 more consistent.
2021-12-08 04:48:21 +01:00
Ulf Lilleengen
cc3ea51778
Merge pull request #108 from embassy-rs/detect-iop-clock
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Detect iop bus
2021-12-02 11:25:27 +01:00
Ulf Lilleengen
6eab78746e
Fix wording
2021-12-02 11:23:16 +01:00
Ulf Lilleengen
57c7058739
Detect GPIO enable/reset registers on chips with separate bus for GPIO
2021-12-02 11:17:52 +01:00
Dario Nieuwenhuis
9afa81e824
Merge pull request #107 from matoushybl/timers
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Add correct timer register mapping for the H7 family.
2021-11-30 20:16:05 +01:00
