Bob McWhirter
02dd4e13f2
Parse in the dma HAL headers for the actual request numbers.
...
Then apply them to fix up where possible because the XML is crap.
2021-07-16 13:44:40 -04:00
Dario Nieuwenhuis
134d22af37
Add H7 SMPS
2021-07-16 00:38:49 +02:00
Dario Nieuwenhuis
ac29cdf3cd
Add write-only access to TDR
2021-07-15 00:47:27 +02:00
Dario Nieuwenhuis
48b70bdf76
Merge USARTv2 and USARTv3, they're identical.
2021-07-15 00:20:17 +02:00
Dario Nieuwenhuis
7112b12a9d
Cleanup USARTv2 regs.
2021-07-15 00:12:08 +02:00
Bob McWhirter
9040fafc33
Ensure the RCC reg is named DMA1EN and not just DMAEN
2021-07-12 15:55:13 -04:00
Bob McWhirter
2c3dfeb352
Reparse to include UART.
2021-06-30 14:36:04 -04:00
Bob McWhirter
c48e894dbe
USART v3 reg block.
2021-06-30 13:31:48 -04:00
Bob McWhirter
3bfe1bdee5
Rename some USART regs, needs more work.
2021-06-29 10:52:44 -04:00
Dario Nieuwenhuis
a4902ab5c3
dmamux: merge CSR and CFR
2021-06-23 04:17:18 +02:00
Dario Nieuwenhuis
ac9c476561
Split DMA/BDMA into v1 (no selection) and v2 (has request selection).
2021-06-23 04:02:06 +02:00
Dario Nieuwenhuis
e3c6e44b76
Rename DMAv1 to BDMA, to allow DMA and BDMA to coexist in H7
2021-06-23 02:47:27 +02:00
Dario Nieuwenhuis
d260d9f2cf
remove gpio_af
2021-06-23 02:34:00 +02:00
Dario Nieuwenhuis
29f70ac45f
Add DMAMUX
2021-06-23 02:30:55 +02:00
Thales Fragoso
6656c5c059
Add F0 syscfg
2021-06-22 23:53:50 +02:00
Thales Fragoso
26e4f541ba
Add F0 FLASH
2021-06-22 23:53:50 +02:00
Thales Fragoso
ae8455a336
Add F0 RCCs
2021-06-22 23:53:37 +02:00
Dominik Boehi
51395f941a
Use arrays and blocks for everything in EXTI
2021-06-21 19:13:26 +02:00
Dominik Boehi
481e607977
Add IPCC peripheral to STM32WB55
2021-06-21 19:13:24 +02:00
Dominik Boehi
454854d527
Add EXTI for STM32WB55
2021-06-21 19:12:00 +02:00
Dario Nieuwenhuis
77d4ae203b
Add DBGMCU for all chips
2021-06-21 01:27:36 +02:00
Ulf Lilleengen
3ef6421aa8
Add more peripherals for wl5x
2021-06-16 16:07:00 +02:00
Ulf Lilleengen
9161dbcac9
Regenerate with dual core support
...
* Add support for WL55 chip family
2021-06-16 15:10:42 +02:00
Bob McWhirter
c511da9664
And WB55 VREFINT.
2021-06-14 11:56:04 -04:00
Bob McWhirter
dea6d819dd
Add VREFINT for STM32L4 family and reparse.
2021-06-14 11:43:49 -04:00
Dario Nieuwenhuis
e478047c78
Merge pull request #45 from embassy-rs/eth-v2
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Eth v2
2021-06-13 20:54:17 +02:00
Thales Fragoso
6a6eed71a5
eth-v2: Remove separate eth dma and mac
2021-06-13 08:17:21 -03:00
Thales Fragoso
a7b126b078
eth-v2: Fix descriptors address fields
2021-06-13 08:16:11 -03:00
Dario Nieuwenhuis
8e71f3da8e
Merge pull request #44 from Tiwalun/stm32wb55-support
...
Add RCC and SYSCFG for STM32WB55
2021-06-11 22:46:34 +02:00
Dominik Boehi
6c872019d0
Add RCC and SYSCFG for STM32WB55
2021-06-11 22:36:40 +02:00
Thales Fragoso
e3cc9b041c
Add a single yaml for eth_v2
2021-06-11 00:15:56 -03:00
Thales Fragoso
2d0ecd1ec0
Add ethernet (v2) dma and mac
2021-06-11 00:15:56 -03:00
Bob McWhirter
f202deb4c1
Add some enums to ADC fields.
2021-06-10 15:33:17 -04:00
Bob McWhirter
b7c071aa71
Clean up a bit.
2021-06-10 10:38:02 -04:00
Bob McWhirter
fc64e88b92
Extract ADCv3 (arrayification is not possible, slight diffs in field widths)
...
Extract ADC_COMMON
Create framework for extra synthetic hand-crafted peripherals.
Add VREFINTCAL reg/block/peripheral for STM32L4+.
2021-06-10 10:38:02 -04:00
Bob McWhirter
23fed4339b
ADC v3 attempt #2 .
2021-06-10 10:37:32 -04:00
Ulf Lilleengen
af3e9e60a3
Add missing RCC block for H7AB family
2021-06-10 08:57:46 +02:00
Ulf Lilleengen
e58aa40b74
Minor register fixes for RCC L4
2021-06-07 15:31:44 +02:00
Ulf Lilleengen
06fd321be1
Fix regs
2021-06-07 13:50:49 +02:00
Ulf Lilleengen
5f350c7c25
Fix duplicate regs
2021-06-07 12:41:13 +02:00
Ulf Lilleengen
c1aae8d3d8
Run through transform again
2021-06-07 12:22:09 +02:00
Ulf Lilleengen
1d0b8db2ee
Regen and update transform
2021-06-07 12:03:15 +02:00
Ulf Lilleengen
f31ba7bfcb
Separate block for H7AB
2021-06-03 15:43:21 +02:00
Ulf Lilleengen
fea5e31f8b
Regen and remove *ON enums
2021-06-03 15:13:46 +02:00
Ulf Lilleengen
529b991404
Do merge
2021-06-03 14:31:27 +02:00
Ulf Lilleengen
332fc1728b
Add script for merging regs
2021-06-03 14:02:53 +02:00
Ulf Lilleengen
aa9257548c
Remove enums from h7 regs
2021-06-03 12:27:42 +02:00
Ulf Lilleengen
18a99a3a3b
Add RCC register for STM32F4 and STM32L4
...
Register block based in STM32F427ZI and STM32L4R9.
Use bool for reset registers.
Define clock mapping for RNG peripherals. There are no 1 <-> 1 mapping
of RNG peripheral to clock in the Cubedb sources. The mapping will
pre-select the clock source for RNG for now.
2021-06-03 11:33:24 +02:00
Ulf Lilleengen
9ad584c149
Remove enums from enable registers
...
Add transform for RCC
2021-06-02 16:32:43 +02:00
Dario Nieuwenhuis
b511ab77e9
Merge pull request #32 from lulf/add-dbgmcu-and-crs
...
Add DBGMCU for L0 and CRS from headers
2021-05-28 00:11:10 +02:00
